[PATCH] [MIPS] Remove unnecessary moves around DSP multiply-accumulate instructions

Unnecessary moves around dpadd and dpsub are caused by different pseudos being assigned to the input-output operands which correspond to the same register. Just like for the MSA multiply-accumulate instructions, this forces the same pseudo to the input-output operands, which removes unnecesary mov

[PATCH] [MIPS] Prevent allocation of a GPR for a floating mode pseudo

Similar to the mirror case of allocating an FPR for an integer mode pseudo, prevent GPRs from being allocated for a floating mode pseudo. --- gcc/config/mips/mips.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 513fc5f..ffcb14d 1006

[PATCH v2] [MIPS] Prevent allocation of a GPR for a floating mode pseudo

Similar to the mirror case of allocating an FPR for an integer mode pseudo, prevent GPRs from being allocated for a floating mode pseudo. gcc/ChangeLog: * gcc/config/mips/mips.c (mips_ira_change_pseudo_allocno_class): Limit the allocation of floating mode pseudos to FP_REGS. ---

[PATCH] [MIPS] Reject vector constants from the constant pool

This rejects vector constants from the constant pool, which removes unnecessary reloads of zero constant around function call in the test case. Tested with mips-mti-linux-gnu. gcc/ChangeLog: * config/mips/mips.c (mips_cannot_force_const_mem): Reject vector constants. gcc/testsui

[PATCH] [MIPS] Replace insert with insve for floating-point values

Currently, when a function argument of type double gets loaded into a vector register on a 32-bit target, it is firstly reloaded into two general purpose registers, and then loaded into a vector register using two insert.w instructions. This patch swaps the two insert.w instructions with one insve

[PATCH] [MIPS] Remove unnecessary moves around dpadd and dpsub

Unnecessary moves around dpadd and dpsub are caused by different pseudos being assigned to the input-output operands which correspond to the same register. This forces the same pseudo to the input-output operands, which removes unnecesary moves. Tested on mips-mti-linux-gnu. gcc/ChangeLog:

[PATCH] [MIPS] Mark built-in functions as pure

Mips built-in functions are currently not marked as pure, which invalidates pointers across built-in function calls. If a pointer is alive across built-in call, dereferencing it before and after the call will generate two load instructions instead of one. This marks the built-ins as pure, which re

[PATCH] [MIPS] PR82981 - mulditi3 pattern for MIPS64R6

This expands the existing MIPS mulditi3 pattern by adding support for MIPS64R6 multiplication instructions. gcc/ChangeLog: * config/mips/mips.md (mulditi3): Generate patterns for high doubleword and low doubleword result of multiplication on MIPS64R6. gcc/testsuite/Change

[PATCH] [MIPS] Add missing const qualifier in MSA ld intrinsic documentation

From: Mihailo Stojanovic The documentation is not reflecting the fact that the first argument of MSA ld intrinsics is a const void pointer. gcc/ * doc/extend.texi: Add const qualifier to ld intrinsics. --- gcc/doc/extend.texi | 8 1 file changed, 4 insertions(+), 4 deletions

[PATCH] [MIPS] Fix handling of MSA SUBREG moves on big-endian targets

From: Mihailo Stojanovic Hi everybody, This fixes the MSA implementation on big-endian targets which is essentially broken for things like SUBREG handling and calling convention for vector types. It borrows heavily from [1] as Aarch64 has the same problem with SVE vectors. Conceptually

[PATCH v2] [MIPS] Add machine mode to get_fcsr pattern operand

Hi, Missing machine mode for the unspec_volatile operand of get_fcsr patterns causes an ICE in simplify_subreg on n64 ABI. This adds the missing machine modes and a new test. Tested on mips64el-mti-linux-gnu. Ok for trunk and possibly backport? Cheers, Mihailo gcc/ * config/mips/mips

[PATCH v2] [MIPS] Fix handling of MSA SUBREG moves on big-endian targets

From: Mihailo Stojanovic Hi everybody, This fixes the MSA implementation on big-endian targets which is essentially broken for things like SUBREG handling and calling convention for vector types. It borrows heavily from [1] as Aarch64 has the same problem with SVE vectors. Conceptually

[PATCH] [MIPS] Add machine mode to get_fcsr pattern operand

From: Mihailo Stojanovic Hi, Missing machine mode for the unspec_volatile operand of get_fcsr patterns causes an ICE in simplify_subreg on n64 ABI. This adds the missing machine modes and a new test. Tested on mips64el-mti-linux-gnu. Ok for trunk and possibly backport? Cheers, Mihailo gcc