On Mon, Jan 9, 2023 at 7:34 PM Takayuki 'January June' Suwa
wrote:
>
> Until now, we applied COSTS_N_INSNS() (multiplying by 4) after dividing
> the instruction length by 3, so we couldn't express the difference less
> than modulo 3 in insn cost for size (e.g. 11 Bytes and 12 bytes cost the
> same
On Wed, Jan 11, 2023 at 8:26 PM Takayuki 'January June' Suwa
wrote:
>
> This branch instruction has short encoding if EQ/NE comparison against
> immediate zero when the Code Density Option is enabled, but its "length"
> attribute was only for normal encoding. This patch fixes it.
>
> This patch a
On Wed, Jan 11, 2023 at 8:26 PM Takayuki 'January June' Suwa
wrote:
>
> This patch saves one byte when the Code Density Option is enabled,
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (ctzsi2, ffssi2):
> Rearrange the emitting codes.
> ---
> gcc/config/xtensa/xtensa.md | 8 +++
On Fri, Jan 13, 2023 at 9:03 PM Takayuki 'January June' Suwa
wrote:
>
> In the before-IRA era, ORDER_REGS_FOR_LOCAL_ALLOC was called for each
> function in Xtensa, and there was register allocation table reordering
> for leaf functions to compensate for the poor performance of local-alloc.
>
> Tod
Hi Suwa-san,
On Sun, Jan 15, 2023 at 6:53 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
Hi Suwa-san,
On Mon, Jan 16, 2023 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Mon, Jan 16, 2023 at 8:12 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
Hi Suwa-san,
On Tue, Jan 17, 2023 at 8:23 PM Takayuki 'January June' Suwa
wrote:
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
>
Hi Suwa-san,
On Tue, Jan 17, 2023 at 9:25 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
On Tue, Jan 17, 2023 at 9:43 PM Takayuki 'January June' Suwa
wrote:
>
> Such operation can be done either bitwise-XOR or addition with -2147483648,
> but the latter is one byte less if TARGET_DENSITY.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (xorsi3_internal):
> Rename from
Hi Suwa-san,
On Wed, Jan 18, 2023 at 7:50 PM Takayuki 'January June' Suwa
wrote:
>
> In the previous patch, if insn is JUMP_INSN or CALL_INSN, it bypasses the reg
> check (possibly FAIL).
>
> =
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are
Hi Suwa-san,
On Wed, Jan 18, 2023 at 9:06 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x,
On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa
wrote:
> On 2023/09/06 8:01, Max Filippov wrote:
> > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
> > wrote:
> >> ;; after (prereq. TARGET_MINMAX)
> >> test0:
> >> movi.n a9, 1
> >> minua2, a2,
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1)
> and (x ==
gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* gcc/config/xte
On Fri, Sep 8, 2023 at 1:49 AM Takayuki 'January June' Suwa
wrote:
>
> An idiomatic implementation of boolean evaluation of whether a register is
> zero or not in Xtensa is to assign 0 and 1 to the temporary and destination,
> and then issue the MOV[EQ/NE]Z machine instruction
> (See 8.3.2 Instruc
gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* config/xtensa/
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-13 Max Filippov
gcc/
* config/xten
On Tue, Apr 14, 2020 at 4:40 PM augustine.sterl...@gmail.com
wrote:
>
> On Mon, Apr 13, 2020 at 4:39 PM Max Filippov wrote:
> > 2020-04-13 Max Filippov
> > gcc/
> > * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
> > (extendhisi2_internal): Add %v1 before the loa
This fixes 'non-delegitimized UNSPEC 3 found in variable location' notes
issued when building libraries which interferes with running tests.
2020-05-24 Max Filippov
gcc/
* config/xtensa/xtensa.c (xtensa_delegitimize_address): New
function.
(TARGET_DELEGITIMIZE_ADDRESS):
On Wed, May 27, 2020 at 4:35 PM augustine.sterl...@gmail.com
wrote:
>
> On Tue, May 26, 2020 at 11:43 AM Max Filippov wrote:
> >
> > This fixes 'non-delegitimized UNSPEC 3 found in variable location' notes
> > issued when building libraries which interferes with running tests.
> >
> > 2020-05-24
2020-12-14 Max Filippov
gcc/
* config/xtensa/predicates.md (addsubx_operand): Change accepted
values from 2/4/8 to 1..3.
* config/xtensa/xtensa.md (*addx, *subx): Change RTL pattern
to use 'ashift' instead of 'mult'. Update operands[3] value.
gcc/testsuite/
From: Takayuki 'January June' Suwa
2020-12-16 Takayuki 'January June' Suwa
gcc/
* config/xtensa/xtensa.c (xtensa_emit_move_sequence): Try to
replace 'l32r' with 'movi' + 'slli' when optimizing for size.
* config/xtensa/xtensa.md (movdi): Split loading DI mode constant
From: Takayuki 'January June' Suwa
2020-12-16 Takayuki 'January June' Suwa
gcc/
* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
(*lshrsi3_3x): New patterns.
gcc/testsuite/
* gcc.target/xtensa/shifts.c: New test.
---
gcc/config/xtensa/xtensa.md
2020-12-20 Max Filippov
gcc/
* config/xtensa/xtensa.md (bswapsi2, bswapdi2): New patterns.
gcc/testsuite/
* gcc.target/xtensa/bswap.c: New test.
libgcc/
* config/xtensa/lib1funcs.S (__bswapsi2, __bswapdi2): New
functions.
* config/xtensa/t-xtensa (LIB1AS
Rewrite uw_install_context without function calls to avoid register
spilling in _Unwind_RaiseException during return context installation.
2020-06-08 Max Filippov
gcc/testsuite/
* g++.target/xtensa/pr95571.C: New test.
* g++.target/xtensa/xtensa.exp: New testsuite.
libgcc/
Remove ABI reference from the ELIMINABLE_REGS to avoid static data
initialization dependency on xtensa core configuration.
2020-06-15 Max Filippov
gcc/
* config/xtensa/xtensa.c (xtensa_can_eliminate): New function.
(TARGET_CAN_ELIMINATE): New macro.
* config/xtensa/xtens
2020-06-15 Max Filippov
gcc/
* config/xtensa/elf.h (ASM_SPEC, LINK_SPEC): Pass ABI switch to
assembler/linker.
* config/xtensa/linux.h (ASM_SPEC, LINK_SPEC): Ditto.
* config/xtensa/uclinux.h (ASM_SPEC, LINK_SPEC): Ditto.
* config/xtensa/xtensa.c (xtensa_op
Hello,
this series implements -mabi option support for xtensa target allowing
to choose between windowed and call0 code generation.
Tested with xtensa-linux-uclibc, both windowed and call0, no new
regression failures. Committed to master.
Max Filippov (2):
gcc: xtensa: make register eliminatio
Remove TARGET_THREADPTR reference from TARGET_HAVE_TLS to avoid
static data initialization dependency on xtensa core configuration.
Tested with xtensa-linux-uclibc, no new regression failures.
Committed to master.
2020-06-15 Max Filippov
gcc/
* config/xtensa/xtensa.c (TARGET_HAVE_TLS):
gcc/
* ira-color.cc (update_costs_from_allocno): Check that allocno
is in the consideration_allocno_bitmap before dereferencing
ALLOCNO_COLOR_DATA (allocno).
---
This fixes the invalid memory access, but I'm not sure if that's
sufficient and there's no remaining higher level
gcc/
PR rtl-optimization/107482
* ira-color.cc (assign_hard_reg): Only call
update_costs_from_copies when retry_p is false.
---
gcc/ira-color.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
index 4a1a325e8e31..f
On Mon, Nov 7, 2022 at 12:52 PM Vladimir Makarov wrote:
> even better patch:
>
> diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
> index 4a1a325e8e3..ffe73b61c45 100644
> --- a/gcc/ira-color.cc
> +++ b/gcc/ira-color.cc
> @@ -2209,8 +2209,8 @@ assign_hard_reg (ira_allocno_t a, bool retry_p)
>
gcc/
PR target/107645
* config/m68k/predicates.md (symbolic_operand): Return false
when UNSPEC is under the CONST node.
---
Regtested with --enable-checking=all for target=m68k-linux-uclibc, no
new regressions compared to the compiler built without checking.
Ok for master?
On Sat, Nov 12, 2022 at 11:42 AM Jeff Law wrote:
> ISTM that we'd need to strip the unspec and process its argument
> instead.
I tried that first, the result was more ICEs because that pattern
wasn't recognized at later stages. Then I read the change to the
comment over the symbolic_operand predi
On Tue, Nov 15, 2022 at 7:33 PM Jeff Law wrote:
> Thanks for clarifying. ISTM that operand predicate is quite poorly named.
>
> OK for the trunk.
Thanks. Applied to master.
-- Max
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
gcc/
* config/xtensa/xtensa-opts.h: New header.
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
xtensa_strict_align.
* config/xtensa/xtensa.cc (xtensa_option_override): When
-m[no-]strict-align is not specified in the command line set
xtensa_
On Fri, Jan 20, 2023 at 8:39 PM Takayuki 'January June' Suwa
wrote:
> On 2023/01/21 0:14, Max Filippov wrote:
> > After having this many attempts and getting to the issues that are
> > really hard to detect I wonder if the target backend is the right place
> > for this optimization?
> >
> I guess
On Thu, Jan 19, 2023 at 7:33 PM Takayuki 'January June' Suwa
wrote:
>
> In the previously posted patch
> "xtensa: Make complex hard register clobber elimination more robust and
> accurate",
> the check code for insns that refer to the [DS]Cmode hard register before
> it is overwritten after it is
Hi Suwa-san,
On Mon, Jan 23, 2023 at 7:43 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
Hi Suwa-san,
On Mon, Jan 23, 2023 at 7:43 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
On Fri, May 13, 2022 at 6:35 AM Takayuki 'January June' Suwa
wrote:
>
> No functional changes.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/predicates.md (extui_fldsz_operand): Simplify.
> * gcc/config/xtensa/xtensa.cc (xtensa_mask_immediate, print_operand):
> Ditto.
> ---
>
On Fri, May 13, 2022 at 6:35 AM Takayuki 'January June' Suwa
wrote:
>
> No functional changes.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/constraints.md (M, O): Use the macro.
> * gcc/config/xtensa/predicates.md (addsubx_operand,
> extui_fldsz_operand,
> sext_fldsz_operand
On Fri, May 13, 2022 at 6:35 AM Takayuki 'January June' Suwa
wrote:
>
> This patch makes counting the number of instructions of the remainder
> (modulo 4) part more accurate.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/xtensa.cc (xtensa_expand_block_move):
> Make instruction countin
On Mon, May 23, 2022 at 8:52 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces setmemsi insn pattern of two kinds, unrolled loop and
> small loop, for fixed small length and constant initialization value.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/xtensa-protos.h
> (
On Fri, May 13, 2022 at 6:35 AM Takayuki 'January June' Suwa
wrote:
>
> This patch makes bswap[sd]i2 better register allocation, and reconstructs
> bswapsi2 in order to take advantage of GIMPLE manual byte-swapping
> recognition.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/xtensa.md (bswaps
On Thu, May 26, 2022 at 8:00 PM Takayuki 'January June' Suwa
wrote:
>
> On 2022/05/27 1:57, Max Filippov wrote:
> > is that something that can be addressed in this patch?
>
> seems hard to resolve, because the RTL-generation pass passes only 68
> bytes in that case:
...
> this behavior does not oc
On Mon, May 23, 2022 at 8:52 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces setmemsi insn pattern of two kinds, unrolled loop and
> small loop, for fixed small length and constant initialization value.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/xtensa-protos.h
> (
From: Takayuki 'January June' Suwa
This patch makes bswap[sd]i2 better register allocation, and reconstructs
bswapsi2 in order to take advantage of GIMPLE manual byte-swapping
recognition.
gcc/ChangeLog:
* config/xtensa/xtensa.md (bswapsi2): New expansion pattern.
(bswapsi2_inte
split_double operates with the 'word that comes first in memory in the
target' terminology, while gen_lowpart operates with the 'value
representing some low-order bits of X' terminology. They are not
equivalent and must be dealt with differently on little- and big-endian
targets.
gcc/
PR t
On Sun, May 29, 2022 at 4:00 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds bswaphi2 insn pattern that is one instruction less than the
> default expansion.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (bswaphi2): New insn pattern.
> ---
> gcc/config/xtensa/xtensa.md | 10
On Sun, May 29, 2022 at 4:00 AM Takayuki 'January June' Suwa
wrote:
>
> In Xtensa ISA, there is no single machine instruction that calculates unary
> bitwise negation. But a few optimizers assume that bitwise negation can be
> done by a single insn.
>
> As a result, '((x < 0) ? ~x : x)' cannot be
On Sun, May 29, 2022 at 4:00 AM Takayuki 'January June' Suwa
wrote:
>
> In Xtensa ISA, there is no single machine instruction that calculates unary
> bitwise negation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*andsi3_bitcmpl):
> New insn_and_split pattern.
>
> gcc/testsuit
On Sun, May 29, 2022 at 4:00 AM Takayuki 'January June' Suwa
wrote:
>
> > (clrsb:m x)
> > Represents the number of redundant leading sign bits in x, represented
> > as an integer of mode m, starting at the most significant bit position.
>
> This explanation is just what the NSA instruction (not
Hi Suwa-san,
On Thu, Jun 9, 2022 at 9:26 PM Takayuki 'January June' Suwa
wrote:
>
> Now apply to almost any size of aligned block under such circumstances.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_expand_block_set_small_loop):
> Pass through the block length / loop
Hi Suwa-san,
On Fri, Jun 10, 2022 at 8:28 AM Takayuki 'January June' Suwa
wrote:
>
> This patch revises the previous implementation of constant synthesis.
>
> First, changed to use define_split machine description pattern and to run
> after reload pass, in order not to interfere some optimization
On Sat, Jun 11, 2022 at 1:31 AM Takayuki 'January June' Suwa
wrote:
> > this change results in a bunch of ICEs in the tests like this:
> > during RTL pass: split2
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:
On Sat, Jun 11, 2022 at 1:31 AM Takayuki 'January June' Suwa
wrote:
> > this change results in a bunch of ICEs in the tests like this:
> > during RTL pass: split2
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:
On Thu, Jun 9, 2022 at 9:26 PM Takayuki 'January June' Suwa
wrote:
>
> umulsidi3 is faster than umuldi3 even if library call, and is also
> prerequisite for fast constant division by multiplication.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (mulsidi3, umulsidi3):
> Split int
On Thu, Jun 9, 2022 at 9:26 PM Takayuki 'January June' Suwa
wrote:
>
> This patch implements a new target-specific relative RTL insn cost function
> because of suboptimal cost estimation by default, and fixes several "length"
> insn attributes (related to the cost estimation).
>
> And also introdu
From: Takayuki 'January June' Suwa
Now apply to almost any size of aligned block under such circumstances.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_block_set_small_loop):
Pass through the block length / loop count conditions if
zero-overhead looping is con
From: Takayuki 'January June' Suwa
This patch revises the previous implementation of constant synthesis.
First, changed to use define_split machine description pattern and to run
after reload pass, in order not to interfere some optimizations such as
the loop invariant motion.
Second, not only
gcc/testsuite/
* g++.target/xtensa/pr95571.C (__xtensa_libgcc_window_spill):
New definition.
---
gcc/testsuite/g++.target/xtensa/pr95571.C | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/testsuite/g++.target/xtensa/pr95571.C
b/gcc/testsuite/g++.target/xtensa/pr95571.
On Sat, Jun 11, 2022 at 11:43 PM Takayuki 'January June' Suwa
wrote:
>
> No need to describe the "false side" conditional insn patterns anymore.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-protos.h (xtensa_emit_branch):
> Remove the first argument.
> (xtensa_emit_bit_bran
Hi Suwa-san,
On Sat, Jun 11, 2022 at 11:43 PM Takayuki 'January June' Suwa
wrote:
>
> This patch offers several insn-and-split patterns for bitwise AND with
> register and constant that cannot fit into a "MOVI Ax, simm12" instruction,
> but can be represented as:
>
> i. 1's least significant N
On Mon, Jun 13, 2022 at 9:39 AM Takayuki 'January June' Suwa
wrote:
>
> Changes from v1:
> (*shift_per_byte_omit_AND_1): changed to be split as early as possible
>
>
> ===
> This patch introduces funnel shifter utilization, and rearranges existing
> "per-byte shift" insn patterns.
>
> gcc/Change
On Sat, Jun 11, 2022 at 11:43 PM Takayuki 'January June' Suwa
wrote:
>
> No need to describe the "false side" conditional insn patterns anymore.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-protos.h (xtensa_emit_branch):
> Remove the first argument.
> (xtensa_emit_bit_bran
On Sat, Jun 11, 2022 at 11:43 PM Takayuki 'January June' Suwa
wrote:
>
> In Xtensa ISA, there is no single machine instruction that calculates unary
> bitwise negation, but a few similar fused instructions are exist:
>
>"BALL Ax, Ay, label" // if ((~Ax & Ay) == 0) goto label;
>"BNALL Ax,
On Mon, Jun 13, 2022 at 9:39 AM Takayuki 'January June' Suwa
wrote:
>
> On 2022/06/13 12:49, Max Filippov wrote:
> > Hi Suwa-san,
> hi!
>
> > This change produces a bunch of regression test failures in big-endian
> > configuration:
> bad news X(
> that point is what i was a little worried about...
Hi Suwa-san,
On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces support for sibling call optimization, when call0
> ABI is in effect.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-protos.h (xtensa_prepare_expand_call,
> xtensa_emit_sibcal
On Wed, Jun 15, 2022 at 5:23 AM Takayuki 'January June' Suwa
wrote:
>
> On 2022/06/15 5:17, Max Filippov wrote:
> > Hi Suwa-san,
> hi!
>
> > This change results in a bunch of new regression test failures:
> > The code generated for e.g. gcc.c-torture/execute/921208-2.c looks like
> > this:
> oh,
On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> This patch offers better RTL representations against straightforward
> derivations from some tree optimizers' canonicalized forms.
>
> - rounding up to even, such as '(x + (x & 1))', is canonicalized to
> '((x + 1) & -2)', b
On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> When spilled DFmode registers are reloaded in, once loaded into a pair of
> SImode regs and then copied from that regs. Such unwanted reg-reg moves
> seems not to be eliminated at the "cprop_hardreg" stage, despite no problem
On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> RTL expansion of substitution to [DS]Cmode hard register includes obstructive
> register clobber.
>
> A simplest example:
>
> double _Complex test(double _Complex c) {
> return c;
> }
>
> will be converted to:
>
On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
>
> gcc/ChangeLog:
> * doc/invoke.texi: Document -mextra-l32r-costs= option.
> ---
> gcc/doc/invoke.texi | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
Committed to master.
--
Thanks.
-- Max
On Fri, Jun 17, 2022 at 6:48 AM Takayuki 'January June' Suwa
wrote:
>
> Storing integer constants into litpool in the early stage of compilation
> hinders some integer optimizations. In fact, such integer constants are
> not subject to the constant folding process.
>
> For example:
>
> extern
On Sun, Jun 19, 2022 at 12:15 PM Takayuki 'January June' Suwa
wrote:
>
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_emit_move_sequence):
> Use can_create_pseudo_p(), instead of using individual
> reload_in_progress and reload_completed.
On Sun, Jun 19, 2022 at 12:15 PM Takayuki 'January June' Suwa
wrote:
>
> These instructions will all be converted to L32R ones with litpool entries
> by the assembler.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p):
> Consider relaxed MOVI instructions as
On Tue, Jun 21, 2022 at 12:52 PM Takayuki 'January June' Suwa
wrote:
>
> Fortify buffer overflow message reported.
> (see https://github.com/earlephilhower/esp-quick-toolchain/issues/36)
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (bswapsi2_internal):
> Enlarge the buffer that
On Sun, Jun 26, 2022 at 7:53 AM Takayuki 'January June' Suwa
wrote:
>
> Such constants are often subject to the constant synthesis:
>
> int test(int a) {
> return a - 31999;
> }
>
> test:
> movia3, 1
> addmi a3, a3, -0x7d00
> add a2, a2, a3
>
Hello,
this series addresses the long standing issue with xtensa configuration
support by adding a way to configure toolchain for a specific xtensa
core at runtime using the xtensa-dynconfig [1] library as a plugin.
On a platform with shared library support single toolchain binary
becomes capable
Now that gcc provides __XCHAL_* definitions use them instead of XCHAL_*
definitions from the include/xtensa-config.h. That makes libgcc
dynamically configurable for the target xtensa core.
libgcc/
* config/xtensa/crti.S (xtensa-config.h): Replace #inlcude with
xtensa-config-builtin
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that trie
On Mon, Nov 28, 2022 at 4:46 PM Max Filippov wrote:
>
> Hello,
>
> this series addresses the long standing issue with xtensa configuration
> support by adding a way to configure toolchain for a specific xtensa
> core at runtime using the xtensa-dynconfig [1] library as a plugin.
> On a platform wi
libgcc/
* config/xtensa/xtensa-config-builtin.h (XCHAL_NUM_AREGS)
(XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE, XCHAL_ICACHE_LINESIZE)
(XCHAL_DCACHE_LINESIZE, XCHAL_MMU_MIN_PTE_PAGE_SIZE)
(XSHAL_ABI): Remove stray symbols from macro definitions.
---
libgcc/config/xtensa/xt
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