On 16 January 2015 at 18:10, Christophe Lyon wrote:
> On 16 January 2015 at 16:58, Tejas Belagod wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>> * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
OK /Marcus
On 16 January 2015 at 18:06, Tejas Belagod wrote:
>> +
>> +void vsri_extra(void)
>> +{
>> +/* Test cases with maximum shift amount (this amount is different
>> + * from vsli. */
>> +
>
>
> Nit. Comment Formatting. Similarly, few other places.
>
> Otherwise, LGTM.
>
> Tejas.
>
w.r.t the u
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
> vXXXl.inc.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
> vXXXw.inc.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
>
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c: New file.
OK
/Marcus
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:17, Christophe Lyon wrote:
> This patch series is a follow-up of the conversion of my existing
> testsuite into DejaGnu. It does not yet cover all the tests I wrote,
> but I chose to post this set to have a chance to have it accepted
> before stage 4. I will have 35 more f
On 19 January 2015 at 15:43, Christophe Lyon wrote:
> On 19 January 2015 at 14:29, Marcus Shawcroft
> wrote:
>> On 16 January 2015 at 17:52, Christophe Lyon
>> wrote:
>>
>>>> OK provided, as per the previous couple, that we don;t regression or
>>
On 19/01/15 21:05, James Greenhalgh wrote:
On Mon, Jan 19, 2015 at 08:57:31PM +, Gerald Pfeifer wrote:
On Monday 2015-01-19 17:52, James Greenhalgh wrote:
OK after the Cortex-A57 scheduling description goes in to the ARM port?
Yes, thanks, except that once will be sufficient. ;-) (The cu
On 20 January 2015 at 14:57, Renlin Li wrote:
> gcc/ChangeLog:
>
> 2015-01-20 Renlin Li
>
> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
> the comment.
> * config/aarch64/aarch64.md (tlsle_small_): Add left shift 12-bit
> for higher part.
OK /Marcus
On 20 January 2015 at 15:28, Christophe Lyon wrote:
> On 16 January 2015 at 17:24, Tejas Belagod wrote:
>>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33 };
>>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x,
On 20 January 2015 at 15:24, Christophe Lyon wrote:
> Here is an updated version, where I have removed a few more useless
> variables than you noticed: the [u]int64x1 as well as the 128 bits
> ones.
OK /Marcus
On 20 January 2015 at 15:30, Christophe Lyon wrote:
+ /* Apply a unary operator named INSN_NAME. */
>>>
>>>
>>> Unary op?
>>>
>> Hmm cut & paste issue. Thanks
>>
> Here is an updated versoin, also renaming VPADD into VPXXX, since it's
> in a template.
Updated version is OK /Marcus
On 20 January 2015 at 15:32, Christophe Lyon wrote:
>> No poly or float for vmovl.
>>
> Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2
> variants are necessary.
This version is OK /Marcus
On 20 January 2015 at 15:33, Christophe Lyon wrote:
> On 16 January 2015 at 19:27, Tejas Belagod wrote:
>>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x, 0x, 0x, 0x,
>>> +0x, 0x, 0x, 0x };
>>> +VECT_VAR_DECL(expected,hfloat,3
On 20 January 2015 at 15:34, Christophe Lyon wrote:
> On 16 January 2015 at 19:29, Tejas Belagod wrote:
>>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>>> +0x33, 0x33, 0x33, 0x33,
>>> +0x33, 0x3
On 20 January 2015 at 15:35, Christophe Lyon wrote:
>> Hmm changed my mind: vpaddl takes only one vector as input, although
>> it does add 2 vector elements.
>>
> Here is an updated version, removing poly, float and int8 variants.
OK /Marcus
On 27 January 2015 at 14:31, Jiong Wang wrote:
> 2015-01-19 Ramana Radhakrishnan
> Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (tb1): Clobber CC reg instead
> of scratch reg.
> (cb1): Likewise.
> * config/aarch64/iterators.md (bcond): New define_code_attr.
OK
On 28 January 2015 at 09:24, James Greenhalgh wrote:
> 2015-01-28 James Greenhalgh
>
> * config/aarch64/aarch64-simd.md (aarch64_abs): New.
> * config/aarch64/aarch64-simd-builtins.def (abs): Split by
> integer and floating point variants.
> * config/aarch64/ite
On 28 January 2015 at 17:41, Mike Stump wrote:
> On Jan 27, 2015, at 8:24 AM, Alex Velenko wrote:
>> This patch fixes aarch64/atomic-op-consume.c test to expect safe "LDAXR"
>> instruction to be generated when __ATOMIC_CONSUME semantics is requested.
>
> Did you see:
>
> /* Workaround for Bugzi
On 30 January 2015 at 12:09, Alan Lawrence wrote:
> This was posted towards the end of stage 3, a few days before stage 4
> started. Is it now too late to "ping" ?
>
> --Alan
>> gcc/ChangeLog:
>>
>> * config/aarch64/arm_neon.h (vst1_lane_f32, vst1_lane_f64,
>> vst1_lane_p8, vst1_l
2015-01-25 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(_ARM_FPSRC): Add DN and AHP fields.
(clean_results): Force DN=1 on AArch64.
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
* gcc.target/aarch64/advsimd-int
On 12 January 2015 at 15:52, Kyrill Tkachov wrote:
> Hi all,
>
> As raised in https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01237.html and
> discussed in that thread, using __builtin_sqrt for vsqrt_f64 may end up in a
> call to the library sqrt at -O0. To avoid that this patch uses a target
> buil
On 4 February 2015 at 12:06, James Greenhalgh wrote:
>
> Hi,
>
> HAVE_DESIGNATED_INITIALIZERS is not set for C++, so the NAMED_PARAM macros
> using it provide false security when we compile aarch64.c. Removing this
> is an obvious cleanup and gets rid of some confusing dead code.
>
> This patch re
On 4 February 2015 at 12:18, Kyrill Tkachov wrote:
> Hi all,
>
> This patch makes use of std::swap in every peephole2 of aarch64-ldp-stp.md
> instead of manually swapping rtxen.
> No functional change, just a cleanup.
> Bootstrapped and tested on aarch64.
>
> I'm proposing this for next stage1 tog
On 4 February 2015 at 10:35, Matthew Wahab wrote:
> Hello,
>
> The Cortex-A72 is an ARMv8 core with the same architectural features as the
> Cortex-A57. This patch adds support for the command line option
> -mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option, only
> the name being
On 28 January 2015 at 10:01, Thomas Preud'homme
wrote:
>> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
>> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
>>
>> Hi Andrew,
>>
>> cortex-a57-fma-steering.c is really meant to be autosufficient with
>> aarch64_register_fma_steering being
On 4 February 2015 at 17:34, Gerald Pfeifer wrote:
> On Wednesday 2015-02-04 16:19, Matthew Wahab wrote:
>>
>> This patch documents in gcc-5/changes.html the addition of support for the
>> Cortex-A72 to the ARM and the AArch64 backends.
>
>
> Looks good to me, but you may want to wait a bit for AR
On 8 February 2015 at 02:24, Andrew Pinski wrote:
> Here is the updated patch with Jakub's comments included and added a
> testcase for the 0, 0 case.
>
> Thanks,
> Andrew Pinski
> ChangeLog:
>
> PR target/64893
> * config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins
On 10 February 2015 at 16:06, James Greenhalgh wrote:
>
> Hi,
>
> As is already done for mips and hppa, we should XFAIL this test on
> AArch64 as we don't currently use the store_by_pieces infrastructure.
>
> We may in future want to tweak this, but for GCC 5.0 the safe thing
> to do is just to XF
On 2 February 2015 at 04:51, Hurugalawadi, Naveen
wrote:
> Hi,
>
> Please find attached the patch that handles the operations on
> SYMBOL_SMALL_TPREL appropriately.
> It fixes gcc.dg/tls/opt-11.c regression on ilp32.
>
> Please review the patch and let us know if its okay?
> Regression tested on a
On 9 February 2015 at 05:41, Andrew Pinski wrote:
> The problem here is that we get a symbol_ref which is SImode but for
> the sibcall patterns we only match symbol_refs which use DImode. I
> added a new testcase that tests the non-value sibcall pattern too.
>
> OK? Bootstrapped and tested on aa
On 18 February 2015 at 04:45, Hurugalawadi, Naveen
wrote:
> Hi Marcus,
>
> Thanks for the review.
>
>>> OK, but fix the trailing white space in the patch
>
> Done. Committed with the modification.
>
>>> Can you prepare a backport into 4.9
>
> ILP32 support is not completely added in 4.9 and hence
> case SYMBOL_SMALL_GOTTPREL:
>{
> - rtx tmp_reg = gen_reg_rtx (Pmode);
> + /* In ILP32, the mode of dest can be either SImode or DImode,
> + while the got entry is always of SImode size. The mode of
> + dest depends on how dest is used: if dest is assign
On 18 February 2015 at 11:35, Kyrill Tkachov wrote:
> Ok for trunk and 4.9?
>
> Thanks,
> Kyrill
>
> 2015-02-17 Kyrylo Tkachov
>
> * config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_3):
> Mark operand 0 as earlyclobber in 2nd alternative.
> (1st define_split below *aarch64_lshr
On 11 February 2015 at 10:57, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> PR target/64997
> * config/aarch64/aarch64.md (*xor_one_cmpl3): Use FP_REGNUM_P
> as split condition; force split via '#' in output pattern.
OK /Marcus
On 29 October 2014 10:03, Kyrill Tkachov wrote:
> Hi all,
>
> This patch fixes an issue with the final_prescan workaround for the
> Cortex-A53 erratum 835769
> where calling recog_memoized could modify the recog data for the
> multiply-accumulate instruction
> when looking at a preceding asm block
On 29 October 2014 10:05, Kyrill Tkachov wrote:
> Hi all,
>
> This is the backport of the trunk patch posted at
> https://gcc.gnu.org/ml/gcc-patches/2014-10/msg03019.html.
> It is essentially the same content (only the diff context differs).
>
> Jakub, this is a regression fix so, if ok'd, can we
On 29 October 2014 10:05, Kyrill Tkachov wrote:
> Hi all,
>
> This is the 4.8 backport of the trunk patch
> (https://gcc.gnu.org/ml/gcc-patches/2014-10/msg03019.html).
> Tested similarly.
>
> Ok for that branch?
OK once the 4.9 fix is committed. /Marcus
On 1 October 2014 09:26, Tejas Belagod wrote:
> Hi,
>
> Returning to this old thread,
>
> https://gcc.gnu.org/ml/gcc-patches/2014-06/msg02285.html
>
> here is a patch after a few rounds of review comments, specifically:
>
> https://gcc.gnu.org/ml/gcc-patches/2014-06/msg02248.html
> https://gcc.gnu
On 25 September 2014 04:45, Michael Collison
wrote:
> On certain patterns in atomics.md the constraint 'n' is used in combination
> with the predicate atomic_op_operand. The constraint is too general and
> allows constants that are disallowed by the predicate. This causes an ICE In
> final_scan_in
On 25 September 2014 14:37, James Greenhalgh wrote:
>
> Hi,
>
> This patch fixes an annoying gotcha when adding new cores or piepline
> models in builds for AArch64. The "generic_sched" attribute also needs
> updating in addition to aarch64-tune.md.
>
> I see no good reason for this, we can genera
On 25 September 2014 17:32, Jiong Wang wrote:
>
> patch updated, please review.
>
>
> 2014-09-25 Jiong Wang
> 2014-09-25 Wilco Dijkstra
>
> gcc/
> PR target/63293
> * config/aarch64/aarch64.c (aarch64_expand_epiloue): Add barriers before
> stack adjustment.
OK /Marcus
On 29 October 2014 10:34, Tejas Belagod wrote:
> On 10/10/14 15:48, David Sherwood wrote:
>> I have a fix (originally written by Tejas Belagod) for the following bug:
In which case you should add his name along side yours in the ChangeLog entry...
>> ChangeLog:
>>
>> gcc/:
>> 2014-10-
On 10 October 2014 16:19, Alan Hayward wrote:
> This patch is dependant on "[AArch64] [BE] [1/2] Make large opaque integer
> modes endianness-safe.”
>
> It fixes up movoi/ci/xi for Big Endian, so that we end up with the lsb of
> a big-endian integer to be in the low byte of the highest-numbered
>
On 13 October 2014 11:01, David Sherwood wrote:
> Hi,
>
> This is the second patch of the work to fix:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810
>
> and removes the CANNOT_CHANGE_MODE_CLASS macro, which now permits subregs of
> vector registers to work correctly on aarch64_be.
>
> NOT
On 31 October 2014 14:37, Renlin Li wrote:
> Hi all,
>
> This is a simple patch to add arch-related macros defined ACLE 2.0.
>
> aarch64-none-elf target is tested on the model, no new issues.
>
> Is this Okay for trunk?
>
> gcc/ChangeLog:
>
> 2014-10-31 Renlin Li
>
> * config/aarch64/aarch6
On 5 November 2014 12:08, Christophe Lyon wrote:
> On 31 October 2014 18:15, Ramana Radhakrishnan
> wrote:
>> On Wed, Oct 29, 2014 at 1:22 PM, Christophe Lyon
>> wrote:
>>> Hi,
>>>
>>> Following discussions after Thomas's patches improving bswap support
>>> https://gcc.gnu.org/ml/gcc-patches/201
On 26 October 2014 16:50, Christophe Lyon wrote:
> I've just realized afterwards that the tests aren't guarded against
> targets not supporting Neon.
>
> How about adding the attached small patch?
+if {[istarget arm*-*-*]
+&& ![check_effective_target_arm_neon_ok]} then {
+ return
+}
+
Umm,
On 22 October 2014 15:20, Kyrill Tkachov wrote:
> Hi all,
>
> This is the 4.8 backport of the LINK_SPEC changes to pass down the linker
> option
> --fix-cortex-a53-835769
>
> Bootstrapped and tested on aarch64-none-linux-gnu.
> This depends on the patches under review at:
> https://gcc.gnu.org/ml/
On 30 October 2014 08:54, Gopalasubramanian, Ganesh
wrote:
> 2014-10-30 Ganesh Gopalasubramanian
Check the whitespace in your ChangeLog line.
> * config/arm/types.md (define_attr "type"): Add prefetch.
The existing schedulers use 'load1'. We can of course split that into
two introdu
On 30 September 2014 16:00, Jiong Wang wrote:
> gcc/
> * config/aarch64/aarch64.h (CALL_USED_REGISTERS): Mark LR as caller-save.
> (EPILOGUE_USES): Guard the check by epilogue_completed.
> * config/aarch64/aarch64.c (aarch64_layout_frame): Explictly check for LR.
> (aarch64_can_eliminate)
On 31 October 2014 11:21, Kyrill Tkachov wrote:
> Hi all,
>
> Following up from https://gcc.gnu.org/ml/gcc-patches/2014-10/msg03153.html
> this fixes up the aarch64 port
> accordingly to guard CUMULATIVE_ARGS properly so that we can remove the enum
> keyword from machine_mode.
OK /Marcus
On 11 November 2014 11:27, James Greenhalgh wrote:
> 2014-11-11 James Greenhalgh
>
> * config/aarch64/aarch64-simd.md
> (aarch64_simd_bsl_internal): Remove float cases, canonicalize.
> (aarch64_simd_bsl): Add gen_lowpart expressions where we
> are punning betwee
On 6 November 2014 10:19, Alan Lawrence wrote:
> This generates out-of-range errors at compile- (rather than assemble-)time
> for the vqdm*_lane intrinsics, and also provides a single place to do
> bigendian lane-swapping for all those intrinsics (and others to follow in
> later patches). This all
On 7 June 2016 at 17:56, Kyrill Tkachov wrote:
> Ok for trunk?
>
> Thanks,
> Kyrill
>
> 2016-06-07 Kyrylo Tkachov
> James Greenhalgh
>
> * config/aarch64/arm_neon.h (vcopyq_lane_f32, vcopyq_lane_f64,
> vcopyq_lane_p8, vcopyq_lane_p16, vcopyq_lane_s8, vcopyq_lane_s16,
>
On 17 May 2016 at 10:13, James Greenhalgh wrote:
>
> Hi,
>
> As in the ARM port [1] , the AArch64 port wants to put out "b = a" to set
> an alias. This doesn't cause us any trouble yet, as the AArch64 port doesn't
> warn for this construct - but at the same time there is no reason for us
> not to
On 17 May 2016 at 10:06, James Greenhalgh wrote:
>
> Hi,
>
> This is just a simplification, it probably makes life easier for register
> allocation in some corner cases and seems the right thing to do. We don't
> use the internal version elsewhere, so we're safe to delete it and change
> the types
On 17 May 2016 at 12:02, James Greenhalgh wrote:
> On Tue, May 17, 2016 at 11:32:36AM +0100, Marcus Shawcroft wrote:
>> On 17 May 2016 at 10:06, James Greenhalgh wrote:
>> >
>> > Hi,
>> >
>> > This is just a simplification, it probably makes lif
On 28 July 2015 at 16:51, Renlin Li wrote:
> 2015-07-28 Renlin Li
>
> * gcc.target/aarch64/arm_align_max_pwr.c: Make it a compile test case,
> check the assembly.
> * gcc.target/aarch64/arm_align_max_stack_pwr.c: Likewise.
Hi,
#include
#include
Test cases should not rel
On 5 August 2015 at 17:46, Renlin Li wrote:
> Hi Kyrill,
>
>
> On 30/07/15 17:08, Kyrill Tkachov wrote:
>>
>> Hi Renlin,
>>
>> On 30/07/15 16:50, Renlin Li wrote:
>>>
>>> Hi all,
>>>
>>> This insn should match the following similar rtx pattern and remove the
>>> redundant zero_extend operation if
On 18 August 2015 at 09:51, Matthew Wahab wrote:
> gcc/testsuite
> 2015-08-18 Matthew Wahab
>
> * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Adjust
> dg-options to disable LSE extensions.
> * gcc.target/aarch64/atomic-op-acq_rel.c: Likewise.
> * gcc.
On 18 August 2015 at 10:25, Alex Velenko wrote:
>
>
> On 31/07/15 12:04, Alex Velenko wrote:
>>
>> On 29/07/15 23:14, Jeff Law wrote:
>>>
>>> On 07/28/2015 12:18 PM, Alex Velenko wrote:
On 21/04/15 06:27, Jeff Law wrote:
>
> On 04/20/2015 01:09 AM, Shiva Chen wrote:
>>
>>
On 20 August 2015 at 09:15, James Greenhalgh wrote:
> 2015-08-19 James Greenhalgh
>
> * common/config/aarch64/aarch64-common.c
> (AARCH64_CPU_NAME_LENGTH): Delete.
> (aarch64_option_extension): New.
> (all_extensions): Likewise.
> (processor_name_to_arch
On 20 August 2015 at 09:31, James Greenhalgh wrote:
>
> Hi,
>
> Steve's patch in 2013 [1] to fix the MIPS newlib/libgfortran build
> causes subtle issues for an ARM/AArch64 newlib/libgfortran build. The
> problem is that ARM/AArch64 (and SH) define a stub function for
> ftruncate, which we would p
On 19 June 2015 at 10:15, Jiong Wang wrote:
>
> Rename test source from tlsle.c into tls.c for reuse purpose.
>
> tls.c will be used as test source file for all TLS test, we just need to
> specify different tls options in different testcases.
>
> 2015-06-19 Jiong Wang
>
> gcc/testsuite/
> * g
ed
> later for linker IE model to LE model optimization.
>
> 2015-06-19 Marcus Shawcroft
> Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (UNSPEC_GOTTINYTLS): New UNSPEC.
> (tlsie_tiny_): New define_insn.
> (tlsie_tiny_sidi): Ditto.
> * config/aarc
> 2015-08-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Rename
> SYMBOL_TLSLE to SYMBOL_TLSLE24.
> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Likewise
> (aarch64_expand_mov_immediate): Likewise
> (aarch64_print_operand): Likewise
> 2015-08-19 Marcus Shawcroft
> Jiong Wang
> gcc/
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): Set default
> tls size for tiny, small, large memory model.
> (aarch64_load_symref_appropriately): Support new symbol types.
> (aarch64
On 19 August 2015 at 15:26, Jiong Wang wrote:
> 2015-08-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.opt (mtls-size): New entry.
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function.
> (aarch64_override_options_internal): Call initialize_aarch64_tls_size.
> * d
On 25 August 2015 at 15:15, Jiong Wang wrote:
> 2015-08-25 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.opt (mtls-size): New entry.
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function.
> (aarch64_override_options_internal): Call initialize_aarch64_tls_size.
> * d
On 25 August 2015 at 14:12, Andre Vieira wrote:
> gcc/ChangeLog:
> 2015-08-07 Ramana Radhakrishnan
> Andre Vieira
>
> * config/aarch64/aarch64.md (*condjump): Handle functions > 1 Mib.
> (*cb1): Likewise.
> (*tb1): Likewise.
> (*cb1): Likewise.
>
On 27 July 2015 at 15:33, Ramana Radhakrishnan
wrote:
> Ramana Radhakrishnan
>
> PR target/63304
> * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle
> nopcrelative_literal_loads.
> (aarch64_classify_address): Likewise.
> (aarch64_constan
On 14 December 2015 at 11:01, James Greenhalgh wrote:
> On Wed, Dec 09, 2015 at 01:13:20PM +0000, Marcus Shawcroft wrote:
>> On 27 November 2015 at 13:01, James Greenhalgh
>> wrote:
>>
>> > 2015-11-27 James Greenhalgh
>> >
>>
On 10 September 2015 at 12:28, Jiong Wang wrote:
>
> TLS instruction sequences are always with fixed format, there is no need
> to use operand modifier, we can hardcode the relocation modifiers into
> instruction pattern, all those redundant checks in aarch64_print_operand
> can be removed.
>
> OK
On 11 January 2016 at 08:12, Bilyan Borisov wrote:
> 2015-XX-XX Bilyan Borisov
>
> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): New
> macro
> definition.
>
> gcc/testsuite/
>
> 2015-XX-XX Bilyan Borisov
>
> * gcc.target/aarch64/fesetround-checking-bare
On 11 January 2016 at 10:46, Alan Lawrence wrote:
> However, the test doesn't really look at whether we're using glibc vs
> musl/bionic/uclibc, only at whether we are targeting -linux-gnu or
> -none-elf.
Fair point, the test case is not aligned with the implementation.
Rather than hang the test
On 18 December 2015 at 12:13, James Greenhalgh wrote:
> Looking back at the patch just before I hit commit, the 4.9 backport was
> a little different (as we still have a CANNOT_CHANGE_MODE_CLASS there).
> We can drop the aarch64-protos.h and aarch64.h changes, and we need to
> change the sense of
On 27 November 2014 at 11:27, Renlin Li wrote:
> gcc/ChangeLog:
>
> 2014-11-27 Renlin Li
>
> * config/aarch64/aarch64.c (aarch64_parse_cpu): Don't define
> selected_tune.
> (aarch64_override_options): Use selected_cpu's tuning.
>
OK and this is also broken in 4.9, could you prepare a
On 24 November 2014 at 17:49, Andrew Pinski wrote:
> I had some local patches in my tree which adds a bswap tree code.
> This breaks the aarch64 back-end vectorizing of byteswaps as we use
> the standard mechanism to see if a tree code vectorizes (optabs).
> Since it make sense to have consistent
On 18 November 2014 at 08:34, Bin Cheng wrote:
> 2014-11-18 Bin Cheng
>
> * config/aarch64/aarch64.md (load_pair): Split to
> load_pairsi, load_pairdi, load_pairsf and load_pairdf.
> (load_pairsi, load_pairdi, load_pairsf, load_pairdf): Split
> from load_pair.
On 19 November 2014 at 06:14, Yangfei (Felix) wrote:
> Index: gcc/ChangeLog
> ===
> --- gcc/ChangeLog (revision 217717)
> +++ gcc/ChangeLog (working copy)
> @@ -1,3 +1,14 @@
> +2014-11-13 Felix Yang
> + Shany
On 21 November 2014 at 18:44, Philipp Tomsich
wrote:
> +;; Machine description for AppliedMicro xgene1 core.
> +;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
> +;; Contributed by Theobroma Systems Design und Consulting GmbH.
> +;;See http://www.theobroma-systems.com fo
On 3 December 2014 at 15:30, Renlin Li wrote:
> 2014-12-03 Renlin Li
>
> * config/aarch64/aarch64-opts.h (AARCH64_CORE): Rename IDENT to SCHED.
> * config/aarch64/aarch64.h (AARCH64_CORE): Likewise.
> * config/aarch64/aarch64.c (AARCH64_CORE): Rename X to IDENT, IDENT to
> SCHED.
On 21 November 2014 at 18:44, Philipp Tomsich
wrote:
> +2014-11-19 Philipp Tomsich
> +
> + * config/aarch64/aarch64-cores.def (xgene1): Update/add the
> + xgene1 (APM XGene-1) core definition.
> + * gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
> + * con
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