[PATCH 2/3] LoongArch: Redundant sign extension elimination optimization.

From: liwei We found that the current combine optimization pass in gcc cannot handle the following redundant sign extension situations: (insn 77 76 78 5 (set (reg:SI 143) (plus:SI (subreg/s/u:SI (reg/v:DI 104 [ len ]) 0) (const_int 1 [0x1]))) {addsi3} (expr_list:REG_DEAD

[PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations.

There are two mode iterators defined in the loongarch.md: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) and (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) Replace the mode in the bit arithmetic from GPR to X. Since the bitwise operation instruction does

[PATCH 3/3] LoongArch: Redundant sign extension elimination optimization 2.

From: liwei Eliminate the redundant sign extension that exists after the conditional move when the target register is SImode. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Adjust. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sig

[PATCH v1 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.

The instructions defined in LoongArch Reference Manual v1.1 are not the instruction set v1.1 version. The CPU defined later may only support some instructions in LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and related definitions are removed here. gcc/ChangeLog:

[PATCH v1 0/2] Delete ISA_BASE_LA64V110 related definitions.

ction. It is recommended that the software determines the running process based on this information rather than the version number of the Loongson architecture. So delete the ISA_BASE_LA64V110 related definitions here. Lulu Cheng (1): LoongArch: Remove the definition of ISA_BASE_LA64V110 from the

[PATCH v1 1/2] LoongArch: Switch loongarch-def from C to C++ to make it possible.

From: Xi Ruoyao We'll use HOST_WIDE_INT in LoongArch static properties in following patches. Switch loongarch-def from C to C++ to make it possible. To keep the same readability as C99 designated initializers, create a std::array like data structure with position setter function, and add field s

[PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions.

the version number of the Loongson architecture. So delete the ISA_BASE_LA64V110 related definitions here. *** BLURB HERE *** Lulu Cheng (1): LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code. Xi Ruoyao (1): LoongArch: Switch loongarch-def from C to C++ to make it possibl

[PATCH v2 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.

The instructions defined in LoongArch Reference Manual v1.1 are not the instruction set v1.1 version. The CPU defined later may only support some instructions in LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and related definitions are removed here. gcc/ChangeLog:

[PATCH v2 1/2] LoongArch: Switch loongarch-def from C to C++ to make it possible.

From: Xi Ruoyao We'll use HOST_WIDE_INT in LoongArch static properties in following patches. To keep the same readability as C99 designated initializers, create a std::array like data structure with position setter function, and add field setter functions for structs used in loongarch-def.cc. R

[PATCH v4] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731].

Co-authored-by: Yang Yujie gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_classify_address): Add precessint for CONST_INT. (loongarch_print_operand_reloc): Operand modifier 'c' is supported. (loongarch_print_operand): Increase the processing of '%c'.

Re: [PATCH v4] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731].

Hi, Richard:  Could you please help me look at this document? Is there any problem with my modification? Thanks! 在 2022/12/27 下午2:42, Lulu Cheng 写道: Co-authored-by: Yang Yujie gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_classify_address): Add precessint for

[PATCH v5] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731].

Co-authored-by: Yang Yujie gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_classify_address): Add precessint for CONST_INT. (loongarch_print_operand_reloc): Operand modifier 'c' is supported. (loongarch_print_operand): Increase the processing of '%c'.

Re: [PATCH v5] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731].

Ping? 在 2023/1/13 上午11:27, Lulu Cheng 写道: Co-authored-by: Yang Yujie gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_classify_address): Add precessint for CONST_INT. (loongarch_print_operand_reloc): Operand modifier 'c' is

[PATCH v6] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731].

Co-authored-by: Yang Yujie gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_classify_address): Add precessint for CONST_INT. (loongarch_print_operand_reloc): Operand modifier 'c' is supported. (loongarch_print_operand): Increase the processing of '%c'.

[PATCH v1] libffi: Backport of LoongArch support for libffi.

This is a backport of , and contains modifications to commit 5a4774cd4d, as well as the LoongArch schema portion of commit ee22ecbd11. This is needed for libgo. libffi/ChangeLog: * configure.host: Add LoongArch support. * Makefi

[PATCH v2] libffi: Backport of LoongArch support for libffi.

v1 -> v2: Modify the changelog information and add PR libffi/108682. This is a backport of , and contains modifications to commit 5a4774cd4d, as well as the LoongArch schema portion of commit ee22ecbd11. This is needed for libgo. libffi

[PATCH v1] LoongArch: Remove the symbolic extension instruction due to the SLT directive.

Since the slt instruction does not distinguish between 32-bit and 64-bit operations under the LoongArch 64-bit architecture, if the operands of slt are of SImode, symbol expansion is required before operation. But similar to the following test case, symbol expansion can be omitted: exte

[PATCH v2] LoongArch: Remove redundant sign extension instructions caused by SLT instructions.

v1 -> v2: 1. Modify description information Since the SLT instruction does not distinguish between 64-bit operations and 32-bit operations under the 64-bit LoongArch architecture, if the operand of slt is SImode, the sign extension of the operand needs to be displayed. But similar to t

[PATCH v1] LoongArch: Enable '-free' starting at -O2.

gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-free' on O2 and above. * doc/invoke.texi: Modify the description information of the '-free' compilation option and add the LoongArch description. gcc/testsuite/ChangeLog: * gcc.

[PATCH v2] LoongArch: Enable '-free' starting at -O2.

v1 -> v2: 1. Modify Changelog information format. gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-free' on O2 and above. * doc/invoke.texi: Modify the description information of the '-free' compilation option and add the LoongArch

[PATCH v1] LoongArch: Optimize fixed-point and floating-point conversion operations.

Before optimization, the operation of taking fixed-point numbers from memory and then forcing type conversion needs to be loaded into fixed-point registers before conversion. After the optimization is completed, the fixed-point value is directly transferred to the floating-point register for type c

[PATCH 1/2] LoongArch: Optimize switch with sign-extended index.

The patch refers to the submission of RISCV 7bbce9b50302959286381d9177818642bceaf301. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_extend_comparands): In unsigned QImode test, check for sign extended subreg and/or constant operands, and do a sign extend in tha

[PATCH v1] LoongArch: Optimized multiply instruction generation.

1. Can generate mulh.w[u] instruction. 2. Can generate mulw.d.wu instruction. gcc/ChangeLog: * config/loongarch/loongarch.md (mulsidi3_64bit): (muldi3_highpart): Modify template name. (mulsi3_highpart): Likewise. (mulsidi3_64bit): Field unsigned ext

[PATCH v1] LoongArch: Fix bug of 'di3_fake'.

PR 111334 gcc/ChangeLog: * config/loongarch/loongarch.md: Fix bug of di3_fake. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr111334.c: New test. --- gcc/config/loongarch/loongarch.md | 14 +-- gcc/testsuite/gcc.target/loongarch/pr111334.c | 39 ++

[PATCH v1] LoongArch: Added code generation support for call36 function calls.

When compiling with '-mcmodel=medium', the function call is made through 'pcaddu18i+jirl' if binutils supports call36, otherwise the native implementation 'pcalau12i+jirl' is used. gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36)

[PATCH v2] LoongArch: Add code generation support for call36 function calls.

When compiling with '-mcmodel=medium', the function call is made through 'pcaddu18i+jirl' if binutils supports call36, otherwise the native implementation 'pcalau12i+jirl' is used. gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36)

[PATCH v1 3/3] LoongArch: atomic_load and atomic_store are implemented using dbar grading.

Because the la464 memory model design allows the same address load out of order, so in the following test example, the Load of 23 lines may be executed first over the load of 21 lines, resulting in an error. So when memmodel is MEMMODEL_RELAXED, the load instruction will be followed by "dbar 0x700

[PATCH v1 0/3] Add LoongarchV1.1 instructions support.

Lulu Cheng (3): LoongArch: Add LA664 support. LoongArch: Implement atomic operations using LoongArch1.1 instructions. LoongArch: atomic_load and atomic_store are implemented using dbar grading. gcc/config.gcc| 10 +- .../loongarch/genopts

[PATCH v1 1/3] LoongArch: Add LA664 support.

Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1. Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664. gcc/ChangeLog: * config.gcc: Support LA664. * config/loongarch/genopts/loongarch-strings: Likewis

[PATCH v1 2/3] LoongArch: Implement atomic operations using LoongArch1.1 instructions.

1. short and char type calls for atomic_add_fetch and __atomic_fetch_add are implemented using amadd{_db}.{b/h}. 2. Use amcas{_db}.{b/h/w/d} to implement __atomic_compare_exchange_n and __atomic_compare_exchange. 3. The short and char types of the functions __atomic_exchange and __atomic_excha

[PATCH] LoongArch: Modify MUSL_DYNAMIC_LINKER.

Use no suffix at all in the musl dynamic linker name for hard float ABI. Use -sf and -sp suffixes in musl dynamic linker name for soft float and single precision ABIs. The following table outlines the musl interpreter names for the LoongArch64 ABI names. musl interpreter| LoongArch64 A

[PATCH v2] LoongArch: Add intrinsic function descriptions for LSX and LASX instructions to doc.

From: chenxiaolong gcc/ChangeLog: * doc/extend.texi: Add information about the intrinsic function of the vector instruction. Change-Id: I0117d6f5d68731f1596b6c3016fd82f3d5e2a98d --- gcc/doc/extend.texi | 1662 +++ 1 file changed, 1662 in

[PATCH v2] LoongArch: Fix bug of 'di3_fake'.

PR 111334 gcc/ChangeLog: * config/loongarch/loongarch.md: Fix bug of 'di3_fake'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr111334.c: New test. --- v1 -> v2: Modify the template "*3", the SI type division operation is not supported under t

[PATCH] LoongArch: Change the value of branch_cost from 2 to 6.

gcc/ChangeLog: * config/loongarch/loongarch-def.c: Modify the default value of branch_cost. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmov_ii.c: New test. --- gcc/config/loongarch/loongarch-def.c | 4 ++-- gcc/testsuite/gcc.target/loongarch/cmov_ii.c | 16

[PATCH] LoongArch: gcc: Modify gas uleb128 support test.

From: mengqinggang Add "ld conftest.o -o conftest" process, then the "objdump -dr" contents is right. Because gas write zero to objdec file and generate R_LARCH_ADD_ULEB128/R_LARCH_SUB_ULEB128 reloc pair to calcualte uleb128 format symbol subtraction after ld relaxation. gcc/ChangeLog:

[PATCH v1] LoongArch: Check whether binutils supports the relax function. If supported, explicit relocs are turned off by default.

gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/genopts/loongarch.opt.in: Add compilation option mrelax. And set the initial value of explicit-relocs according to the detection status. * config/loongarch/gnu-user.h: When compiling with -mno-relax,

[PATCH v1] LoongArch: Add floating point conditional move support.

gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_expand_conditional_move): Modify the return value type of a function. * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Added floating point conditional transfer implementat

[PATCH] LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NOP.

There are two reasons for removing this macro definition: 1. The default in the assembler is to use the nop instruction for filling. 2. For assembly directives: .align [abs-expr[, abs-expr[, abs-expr]]] The third expression it is the maximum number of bytes that should be skipped by this alig

Re: Ping: [PATCH v2] LoongArch: Tweak IOR rtx_cost for bstrins

LGTM! Thanks very much! 在 2024/6/26 下午3:53, Xi Ruoyao 写道: Ping. On Sun, 2024-06-16 at 01:50 +0800, Xi Ruoyao wrote: Consider     c &= 0xfff;     a &= ~0xfff;     b &= ~0xfff;     a |= c;     b |= c; This can be done with 2 bstrins instructions.  But we need to recognize it in loongarc

[PATCH 1/2] LoongArch: Fix explicit-relocs-{extreme-, }tls-desc.c tests.

After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX. Cause these two tests to fail. To guarantee that these two tests pass, add the compilation option '-fno-late-combine-instructions'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c:

[PATCH 2/2] LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.

The following two FAIL items have been fixed: FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movcf2fr\\t\$f[0-9]+,\$fcc FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movfr2gr.s\\t\$r4 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_i

Re: [PATCH 2/2] LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.

在 2024/7/2 上午11:50, Xi Ruoyao 写道: On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote: +static int +loongarch_insn_cost (rtx_insn *insn, bool speed) +{ +  rtx x = PATTERN (insn); +  int cost = pattern_cost (x, speed); + +  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr

Re: [pushed][PATCH 1/2] LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests.

Pushed to r15-1764. 在 2024/7/2 上午11:21, Lulu Cheng 写道: After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX. Cause these two tests to fail. To guarantee that these two tests pass, add the compilation option '-fno-late-combine-instructions'. gcc/testsuite

Re:[pushed] [PATCH 2/2] LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.

Modified and pushed to r15-1765. 在 2024/7/2 上午11:50, Xi Ruoyao 写道: On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote: +static int +loongarch_insn_cost (rtx_insn *insn, bool speed) +{ +  rtx x = PATTERN (insn); +  int cost = pattern_cost (x, speed); + +  /* On LA464, prevent movcf2fr and

[PATCH 1/2] LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Replace UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE. * config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete. gcc/testsuite/ChangeLog: * gcc

[PATCH 2/2] LoongArch: Remove unreachable codes.

gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_split_move): Delete. (loongarch_hard_regno_mode_ok_uncached): Likewise. * config/loongarch/loongarch.md (move_doubleword_fpr): Likewise. (load_low): Likewise. (load_high): Likewise.

Re:[pushed] [PATCH 1/2] LoongArch: TFmode is not allowed to be stored in the float register.

Pushed to r15-1986. 在 2024/7/4 下午5:56, Lulu Cheng 写道: PR target/115752 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Replace UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE. * config/loongarch/loongarch.h

Re:[pushed] [PATCH 2/2] LoongArch: Remove unreachable codes.

Pushed to r15-1987. 在 2024/7/4 下午5:56, Lulu Cheng 写道: gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_split_move): Delete. (loongarch_hard_regno_mode_ok_uncached): Likewise. * config/loongarch/loongarch.md (move_doubleword_fpr): Likewise

[PATCH] LoongArch: Organize the code related to split move and merge the same functions.

gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_split_128bit_move): Delete. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move): Delete. (loongarch_split_256bit_move_p): Delete. (loongarch_split_vector_move): Add a

Re: [PATCH] LoongArch: Implement scalar isinf, isnormal, and isfinite via fclass

在 2024/7/11 下午7:45, Xi Ruoyao 写道: Doing so can avoid loading FP constants from the memory. It also partially fixes PR 66462 as fclass does not signal on sNaN. gcc/ChangeLog: * config/loongarch/loongarch.md (extendsidi2): Add ("=r", "f") alternative and use movfr2gr.s for it.

Re:[pushed] [PATCH] LoongArch: Organize the code related to split move and merge the same functions.

Pushed to r15-2167. 在 2024/7/13 下午5:04, Lulu Cheng 写道: gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_split_128bit_move): Delete. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move): Delete

Re: [PATCH] LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115169]

LGTM! Thanks! 在 2024/5/22 下午7:24, Xi Ruoyao 写道: gcc/ChangeLog: PR target/115169 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Guard REGNO with REG_P. --- Bootstrapped with --enable-checking=all. Ok for trunk and 14? gcc/config/loongarch/loong

Re: [PATCH 47/52] loongarch: New hook implementation loongarch_c_mode_for_floating_type

Ok! Thanks! Lulu Cheng 在 2024/6/3 上午11:01, Kewen Lin 写道: This is to add new port specific hook implementation loongarch_c_mode_for_floating_type, remove macro defines for FLOAT_TYPE_SIZE and DOUBLE_TYPE_SIZE, and rename LONG_DOUBLE_TYPE_SIZE to LA_LONG_DOUBLE_TYPE_SIZE as we poison

[PATCH v1 1/2] LoongArch: Drop vcond{,u} expanders.

Optabs vcond{,u} will be removed for GCC 15. Since regtest shows no fallout, dropping the expanders, now. gcc/ChangeLog: PR target/114189 * config/loongarch/lasx.md (vcondu): Delete. (vcond): Likewise. * config/loongarch/lsx.md (vcondu): Likewise. (vcond):

[PATCH v1 2/2] LoongArch: Provide ashr lshr and ashl RTL pattern for vectors.

We support vashr vlshr and vashl. However, in r15-1638 support optimize x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31. To support this optimization, vector ashr lshr and ashl need to be implemented. gcc/ChangeLog: * config/loongarch/loongarch.md (insn): Ad

Re:[pushed] [PATCH v2] LoongArch: Use iorn and andn standard pattern names.

 Pushed to r15-2877. 在 2024/8/2 上午9:19, Lulu Cheng 写道: R15-1890 introduced new optabs iorc and andc, and its corresponding internal functions BIT_{ANDC,IORC}, and if targets defines such optabs for vector modes. And in r15-2258 the iorc and andc were renamed to iorn and andn. So we changed the

Re: [pushed][PATCH v1 1/2] LoongArch: Drop vcond{,u} expanders.

Pushed to r15-2878. 在 2024/8/8 下午2:47, Lulu Cheng 写道: Optabs vcond{,u} will be removed for GCC 15. Since regtest shows no fallout, dropping the expanders, now. gcc/ChangeLog: PR target/114189 * config/loongarch/lasx.md (vcondu): Delete. (vcond): Likewise

Re: [pushed][PATCH v1 2/2] LoongArch: Provide ashr lshr and ashl RTL pattern for vectors.

Pushed to r15-2879. 在 2024/8/8 下午2:47, Lulu Cheng 写道: We support vashr vlshr and vashl. However, in r15-1638 support optimize x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31. To support this optimization, vector ashr lshr and ashl need to be

Re: [PATCH] LoongArch: Fix mode size comparision in loongarch_expand_conditional_move

在 2024/6/12 上午11:06, Xi Ruoyao 写道: We were comparing a mode size with word_mode, but word_mode is an enum value thus this does not really make any sense. (Un)luckily E_DImode happens to be 8 so this seemed to work, but let's make it correct so it won't blow up when we add LA32 support or add a

Re: [PATCH] LoongArch: Use bstrins for "value & (-1u << const)"

LGTM! Thanks! 在 2024/6/9 下午9:48, Xi Ruoyao 写道: A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and pair, and twice fast as a srli/slli pair. When the src reg and the dst reg happens to be the same, the move instruction can be optimized away. gcc/ChangeLog: * conf

Re: [PATCH] LoongArch: NFC: Dedup and sort the comment in loongarch_print_operand_reloc

I think that's fine. Thanks! 在 2024/6/16 下午5:11, Xi Ruoyao 写道: gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): Dedup and sort the comment describing modifiers. --- It's a non-functional change thus I've not tested it. Ok for trunk? gcc/confi

Re: Ping: [PATCH] LoongArch: Only transform move/move/bstrins to srai/bstrins when -Os

 ;; We always avoid the shift operation in bstrins__for_ior_mask -;; if possible, but the result may be sub-optimal when one of the masks +;; if possible, but the result may be larger when one of the masks  ;; is (1 << N) - 1 and one of the src register is the dest register.  ;; For example

[PATCH] LoongArch: Use iorn and andn standard pattern names for scalar modes.

gcc/ChangeLog: * config/loongarch/loongarch.md (n): Rename to ... (n3): This. --- gcc/config/loongarch/loongarch.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 459ad30b9bb..4e4ddd5

Re: [PATCH] LoongArch: Use iorn and andn standard pattern names for scalar modes.

在 2024/7/27 下午4:41, Xi Ruoyao 写道: On Sat, 2024-07-27 at 16:36 +0800, Lulu Cheng wrote: gcc/ChangeLog: * config/loongarch/loongarch.md (n): Rename to ... (n3): This. Ok. Note that [x]vorn3 and [x]vandn3 should be renamed as well. Uh, I just forgot about them, I'm modi

[PATCH] LoongArch: Use iorn and andn standard pattern names for scalar modes.

gcc/ChangeLog: * config/loongarch/loongarch.md (n): Rename to ... (n3): This. --- gcc/config/loongarch/loongarch.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 459ad30b9bb..4e4ddd5

[PATCH] LoongArch: Use iorn and andn standard pattern names.

gcc/ChangeLog: * config/loongarch/lasx.md (xvandn3): Rename to ... (andn3): This. (xvorn3): Rename to ... (iorn3): This. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v): Defined as the modified name. (CODE_FOR_lsx_vorn_v): Lik

Re: [PATCH] LoongArch: Use iorn and andn standard pattern names.

在 2024/7/28 上午3:30, Andrew Pinski 写道: On Sat, Jul 27, 2024 at 1:55 AM Lulu Cheng wrote: gcc/ChangeLog: * config/loongarch/lasx.md (xvandn3): Rename to ... (andn3): This. (xvorn3): Rename to ... (iorn3): This. * config/loongarch/loongarch

Re: [PATCH] LoongArch: Expand some SImode operations through "si3_extend" instructions if TARGET_64BIT

在 2024/7/26 下午8:43, Xi Ruoyao 写道: We already had "si3_extend" insns and we hoped the fwprop or combine passes can use them to remove unnecessary sign extensions. But this does not always work: for cases like x << 1 | y, the compiler tends to do (sign_extend:DI (ior:SI (ashift:SI (

Re: [PATCH] LoongArch: Relax ins_zero_bitmask_operand and remove and3_align

在 2024/7/29 下午3:59, Xi Ruoyao 写道: In r15-1207 I was too stupid to realize we just need to relax ins_zero_bitmask_operand to allow using bstrins for aligning, instead of adding a new split. And, "> 12" in ins_zero_bitmask_operand also makes no sense: it rejects bstrins for things like "x & ~4l"

Re: [PATCH] LoongArch: Rework bswap{hi,si,di}2 definition

在 2024/7/29 下午3:58, Xi Ruoyao 写道: Per a gcc-help thread we are generating sub-optimal code for __builtin_bswap{32,64}. To fix it: - Use a single revb.d instruction for bswapdi2. - Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT, revb.2h + rotri.w for !TARGET_64BIT. - Use a s

Re: [PATCH] LoongArch: Rework bswap{hi,si,di}2 definition

在 2024/7/31 下午6:25, Xi Ruoyao 写道: On Wed, 2024-07-31 at 16:57 +0800, Lulu Cheng wrote: 在 2024/7/29 下午3:58, Xi Ruoyao 写道: Per a gcc-help thread we are generating sub-optimal code for __builtin_bswap{32,64}.  To fix it: - Use a single revb.d instruction for bswapdi2. - Use a single revb.2w

[PATCH v2] LoongArch: Use iorn and andn standard pattern names.

R15-1890 introduced new optabs iorc and andc, and its corresponding internal functions BIT_{ANDC,IORC}, and if targets defines such optabs for vector modes. And in r15-2258 the iorc and andc were renamed to iorn and andn. So we changed the andn and iorn implementation templates to the standard tem

[PATCH v2] LoongArch: Use iorn and andn standard pattern names.

R15-1890 introduced new optabs iorc and andc, and its corresponding internal functions BIT_{ANDC,IORC}, and if targets defines such optabs for vector modes. And in r15-2258 the iorc and andc were renamed to iorn and andn. So we changed the andn and iorn implementation templates to the standard tem

Re:[pushed] [PATCH 0/1] LoongArch: Remove gawk extension from a generator script.

Pushed to r15-2660. 在 2024/7/23 上午10:04, Yang Yujie 写道: Builds for the LoongArch target fail if the system "awk" is not "gawk". This patch removes this unnecessary requirement. Thanks to Jan-Benedict Glaw for finding and reporting this issue. Yang Yujie (1): LoongArch: Remove gawk extensio

Re: [pushed][PATCH] LoongArch: Add indexes for some compilation options.

Pushed to r14-9984. 在 2024/4/9 下午4:19, Lulu Cheng 写道: gcc/ChangeLog: * config/loongarch/loongarch.opt.urls: Regenerate. * config/mn10300/mn10300.opt.urls: Likewise. * config/msp430/msp430.opt.urls: Likewise. * config/nds32/nds32-elf.opt.urls: Likewise

[PATCH] gcc-13/changes.html (LoongArch): Fix link.

--- htdocs/gcc-13/changes.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 4384c329..15a309d6 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -625,7 +625,7 @@ You may also want to chec

Re: [PATCH 1/2] LoongArch: Define ISA versions

在 2024/4/19 下午10:27, Xi Ruoyao 写道: On Fri, 2024-04-19 at 19:04 +0800, Yang Yujie wrote:  @table @samp  @item native -This selects the CPU to generate code for at compilation time by determining -the processor type of the compiling machine.  Using @option{-march=native} -enables all instructio

Re: [pushed][PATCH v4 2/2] LoongArch: Define builtin macros for ISA evolutions

Pushed to r14-10084. 在 2024/4/23 上午10:42, Yang Yujie 写道: Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Add loongarch-evolution.o. * co

Re:[pushed] [PATCH v4 1/2] LoongArch: Define ISA versions

Pushed to r14-10083. 在 2024/4/23 上午10:42, Yang Yujie 写道: These ISA versions are defined as -march= parameters and are recommended for building binaries for distribution. Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the Loo

[PATCH] wwwdocs: gcc-14/changes.html: Add Loongarch changes.

--- htdocs/gcc-14/changes.html | 156 + 1 file changed, 156 insertions(+) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 9509487c..f0f0efe0 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -877,6 +877,162 @

Re: [pushed][PATCH] wwwdocs: gcc-14/changes.html: Add Loongarch changes.

在 2024/4/23 上午11:43, Lulu Cheng 写道: --- htdocs/gcc-14/changes.html | 156 + 1 file changed, 156 insertions(+) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 9509487c..f0f0efe0 100644 --- a/htdocs/gcc-14/changes.html +++ b

Re: [PATCH] LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861]

LGTM! Thanks. 在 2024/4/26 下午9:52, Xi Ruoyao 写道: Without the constrants, the compiler attempts to use a stack slot as the target, causing an ICE building the kernel with -Os: drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1: error: could not split insn (insn:TI 1764 67 1745 (s

[PATCH][gcc-13] LoongArch: Fix eh_return epilogue for normal returns.

From: Yang Yujie On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be overwritten on normal return paths and breaks a rare case of libgcc'

[PATCH][gcc-12] LoongArch: Fix eh_return epilogue for normal returns.

From: Yang Yujie On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be overwritten on normal return paths and breaks a rare case of libgcc'

Re: [pushed][PATCH][gcc-12] LoongArch: Fix eh_return epilogue for normal returns.

Pushed to r12-10403. 在 2024/4/29 下午4:09, Lulu Cheng 写道: From: Yang Yujie On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be

Re: [pushed][PATCH][gcc-13] LoongArch: Fix eh_return epilogue for normal returns.

Pushed to r13-8661. 在 2024/4/29 下午4:09, Lulu Cheng 写道: From: Yang Yujie On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be

Re: [pushed] [PATCH v4 1/2] LoongArch: Define ISA versions

dme-ov-file#target-presets has a detailed description of -march. -march=la64v1.0 will open lsx by default. On Tue, 2024-04-23 at 11:31 +0800, Lulu Cheng wrote: Pushed to r14-10083. 在 2024/4/23 上午10:42, Yang Yujie 写道: These ISA versions are defined as -march= parameters and are recommended

Re: [PATCH v3] LoongArch: Optimize immediate load.

在 2022/11/4 上午10:22, Xi Ruoyao 写道: On Tue, 2022-11-01 at 20:04 +0800, Lulu Cheng wrote: gcc/ChangeLog: * config/loongarch/constraints.md (x): New constraint. * config/loongarch/loongarch.cc (struct loongarch_address_info): Adds a method to load the immediate 32 to

Re: [PATCH v3] LoongArch: Optimize immediate load.

在 2022/11/4 上午10:56, Xi Ruoyao 写道: On Fri, 2022-11-04 at 10:33 +0800, Lulu Cheng wrote: 在 2022/11/4 上午10:22, Xi Ruoyao 写道: On Tue, 2022-11-01 at 20:04 +0800, Lulu Cheng wrote: gcc/ChangeLog:  * config/loongarch/constraints.md (x): New constraint.  * config/loongarch

Re: [PATCH] LoongArch: fix signed overflow in loongarch_emit_int_compare

在 2022/11/4 下午2:39, Xi Ruoyao 写道: Signed overflow is an undefined behavior, so we need to prevent it from happening, instead of "checking" the result. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_emit_int_compare): Avoid signed overflow. --- Bootstrapped and regt

Re: [PATCH] LoongArch: Add fcopysign instructions

在 2022/11/4 下午10:37, Xi Ruoyao 写道: Add fcopysign.{s,d} with the names copysign{sf,df}3 so GCC will expand __builtin_copysign{f,} to a single instruction. Link: https://sourceware.org/pipermail/libc-alpha/2022-November/143177.html gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC

Re: [PATCH v2] LoongArch: fix signed overflow in loongarch_emit_int_compare

LGTM. Thanks! 在 2022/11/9 下午3:26, Xi Ruoyao 写道: Signed overflow is an undefined behavior, so we need to prevent it from happening, instead of "checking" the result. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_emit_int_compare): Avoid signed overflow. --- v1 -> v

Re: [PATCH 2/4] LoongArch: Add ftint{, rm, rp}.{w, l}.{s, d} instructions

There is a paragraph in the explanation information for the compile parameter '-fno-fp-int-builtin-inexact' in the gcc.pdf document:     "Do not allow the built-in functions ceil, floor, round and trunc, and their　float and long double variants,     to generate code that raises the “inexact”　

Re: [PATCH v2 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions

在 2022/11/9 下午9:53, Xi Ruoyao 写道: +;; Convert floating-point numbers to integers +(define_insn "2" + [(set (match_operand:ANYFI 0 "register_operand" "=f") + (unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")] + LRINT))] + "TARGET_HARD_FLOAT && + ( +||

Re: [PATCH v2 1/4] LoongArch: Rename frint_ to rint2

LGTM! Thanks. 在 2022/11/9 下午9:53, Xi Ruoyao 写道: Use standard name so __builtin_rint{,f} can be expanded to one instruction. gcc/ChangeLog: * config/loongarch/loongarch.md (frint_): Rename to .. (rint2): .. this. gcc/testsuite/ChangeLog: * gcc.target/loongarch/frint.c

Re: [PATCH v2 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions

I have no more questions. Thanks. 在 2022/11/11 下午1:29, Xi Ruoyao 写道: Lulu: So I think the code is correct: + ( +|| flag_fp_int_builtin_inexact +|| !flag_trapping_math)" is 1 for lrint, 0 for lceil and lfloor. As N3054 says: The lrint and llrint functions provide floating-to-

Re: [PATCH v2 3/4] LoongArch: Add fscaleb.{s,d} instructions as ldexp{sf,df}3

在 2022/11/9 下午9:53, Xi Ruoyao 写道: This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} with -fno-math-errno. IMODE is added because we can't hard code SI for operand 2: fscaleb.d instruction always take the high half of both source registers into account. See my_ldexp_long in t

Re: [PATCH v2 4/4] LoongArch: Add flogb.{s, d} instructions and expand logb{sf,df}2

LGTM! Thanks. 在 2022/11/9 下午9:53, Xi Ruoyao 写道: On LoongArch, flogb instructions extract the exponent of a non-negative floating point value, but produces NaN for negative values. So we need to add a fabs instruction when we expand logb. gcc/ChangeLog: * config/loongarch/loongarch.md

Re: [PATCH v2 3/4] LoongArch: Add fscaleb.{s,d} instructions as ldexp{sf,df}3

在 2022/11/12 下午12:40, Xi Ruoyao 写道: On Sat, 2022-11-12 at 11:54 +0800, Lulu Cheng wrote: 在 2022/11/9 下午9:53, Xi Ruoyao 写道: This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} with -fno-math-errno. IMODE is added because we can't hard code SI for operand 2: fsca

Re: [PATCH v2 0/4] LoongArch: Add some floating-point operations

在 2022/11/12 下午3:08, Xi Ruoyao 写道: On Wed, 2022-11-09 at 21:53 +0800, Xi Ruoyao wrote: These patches allow to expand the following builtins to floating point instructions for LoongArch: - __builtin_rint{,f} - __builtin_{l,ll}rint{,f} - __builtin_{l,ll}floor{,f} - __builtin_{l,ll}ceil{,f} - __

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