Adapt and Robostify testcases.
juzhe.zh...@rivai.ai
*From:* Kito Cheng <mailto:kito.ch...@gmail.com>
*Date:* 2023-10-16 23:38
*To:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*CC:* GCC Patch
Hi Jeff,
Can you replace riscv_vector with riscv_v? That way this will still
work after Joern commits his change to standardize on the riscv_v target
selector.
OK with that change, no need to wait for a review on V2, just go ahead
and blast it in.
No problem, I'll tweak it later and submi
This little path fix a failed testcase when use -cmodel=medany.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Split check.
---
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/gcc/tests
Committed, thanks Juzhe.
On 2023/10/17 17:58, juzhe.zh...@rivai.ai wrote:
OK
juzhe.zh...@rivai.ai
*From:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*Date:* 2023-10-17 17:57
*To:* gcc-patches <mailto:gc
725
Lehua Ding (14):
RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info
RISC-V: P2: Refactor and cleanup demand system
RISC-V: P3: Refactor class vector_infos_manager to pre_vsetvl
RISC-V: P4: move method from class pass_vsetvl to pre_vsetvl
RISC-V: P5: combine phase 1 and 2 int
This sub-patch combine avl_info/vl_vtype_info/vector_insn_info to
a single class vsetvl_info.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (avl_info::avl_info): Removed.
(avl_info::single_source_equal_p): Ditto.
(avl_info::multiple_source_equal_p): Ditto.
(avl_inf
This sub-patch refactor vector_infos_manager to a pre_vsetvl class
which is responsible for the entire lazy vsetvl jobs. There is no need
to introduce a separate vsetvl infos manager, because vsetvl infos are
modified by the optimization code.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
This sub-patch combine phase 1 and 2 to use the new demand system and
delay the insert of vsetvl insn into phase 4.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
New.
(pass_vsetvl::compute_local_backward_infos): Removed.
(pass_vsetvl:
This sub-patch refactor the demand system. I split the demand information
into three parts. They are sew and lmul related (sew_lmul_demand_type),
tail and mask policy related (policy_demand_type) and avl related
(avl_demand_type). Then we define three interfaces avaiable_with,
compatible_with and m
This sub-patch remove the method about optimize vsetvl infos into
class pre_vsetvl.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info): Removed.
(pass_vsetvl::get_block_info): Removed.
(pass_vsetvl::update_vector_info): Removed.
(pass_vset
This patch adjust move the code phase 2 and 3 from pass_vsetvl to
pre_vsetvl class.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
New.
(pre_vsetvl::pre_global_vsetvl_info): New.
(pass_vsetvl::prune_expressions): Removed.
(p
This sub-patch add some helper functions for computing reaching defintion data
and three computational functions for different object. These three functions
are used by phase 2 and 3.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (bitmap_union_of_preds_with_entry): New.
(compute_r
This sub-patch deletes partial post optimize code(which implement
in the main phase) and move the remain cleanup code to pre_vsetvl class.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::cleaup): New.
(pre_vsetvl::remove_avl_operand): New.
(pre_vsetvl::remove_un
This sub-patch delete the unused header file riscv-vsetvl.h
since we no need export any function.
gcc/ChangeLog:
* config/riscv/t-riscv: Removed riscv-vsetvl.h
* config/riscv/riscv-vsetvl.h: Removed.
---
gcc/config/riscv/riscv-vsetvl.h | 59 -
gcc
This sub-patch move the modification of rtl codes from pass_vsetvl
into pre_vsetvl class.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): New.
(pass_vsetvl::can_refine_vsetvl_p): Removed.
(pass_vsetvl::refine_vsetvls): Removed.
(pass_vsetvl
This sub-patch adjust vector_block_info codes and rename to
vsetvl_block_info.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (class vsetvl_block_info): New.
* config/riscv/riscv-vsetvl.h (struct vector_block_info): Removed.
---
gcc/config/riscv/riscv-vsetvl.cc | 55 +
This sub-patch delete unused helper functions and reorganize
the position of the remain functions.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (debug): Removed.
(enum vsetvl_type): Moved.
(enum emit_type): Moved.
(vlmax_avl_p): Removed.
(vlmul_to_str): Mo
This sub-patch adjust some testcases and add some bugfix
testcases.
PR target/111037
PR target/111234
PR target/111725
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-1.c: Adjust.
* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Adjust.
This sub-patch reoriganize the functions that used to modify RTL.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (has_no_uses): Moved.
(validate_change_or_fail): Moved.
(gen_vsetvl_pat): Removed.
(emit_vsetvl_insn): Removed.
(eliminate_insn): Removed.
mes vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c -O3 -g
scan-assembler-times vsetvli 15
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c -O3 -g
scan-assembler-times vsetvli 15
On 10/17/23 04:34, Lehua Ding wrote:
This patch refactors and cleanups the vsetvl pa
Committed, thanks Robin.
On 2023/10/18 15:53, Robin Dapp wrote:
LGTM.
Regards
Robin
--
Best,
Lehua (RiVAI)
lehua.d...@rivai.ai
vsetvli 15
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c -O3 -g
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c -O3 -g
scan-assembler-times vsetvli 15
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c -O3 -g
scan-assembler-times vsetvli 1
725
Lehua Ding (11):
RISC-V: P1: Refactor
avl_info/vl_vtype_info/vector_insn_info/vector_block_info
RISC-V: P2: Refactor and cleanup demand system
RISC-V: P3: Refactor vector_infos_manager
RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
RISC-V: P5: combine phase 1 and 2
RISC-V:
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (incompatible_avl_p): Removed.
(different_sew_p): Removed.
(different_lmul_p): Removed.
(different_ratio_p): Removed.
(different_tail_policy_p): Removed.
(different_mask_policy_p): Removed.
(possi
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info): Removed.
(pass_vsetvl::get_block_info): Removed.
(pass_vsetvl::update_vector_info): Removed.
(pass_vsetvl::update_block_info): Removed.
(pass_vsetvl::simple_vsetvl): Removed.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (avl_info::avl_info): Removed.
(avl_info::single_source_equal_p): Removed.
(avl_info::multiple_source_equal_p): Removed.
(avl_info::operator=): Removed.
(avl_info::operator==): Removed.
(avl_info::operato
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager): Removed.
(vector_infos_manager::create_expr): Removed.
(class pre_vsetvl): New class.
(vector_infos_manager::get_expr_id): Removed.
(vector_infos_manager::all_same_r
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
New.
(pass_vsetvl::compute_local_backward_infos): Removed.
(pass_vsetvl::need_vsetvl): Removed.
(pass_vsetvl::transfer_before): Removed.
(pass_vsetvl::transfer_after): Remov
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): New.
(pre_vsetvl::cleaup): New.
(pre_vsetvl::remove_avl_operand): New.
(pre_vsetvl::remove_unused_dest_operand): New.
(pass_vsetvl::get_vsetvl_at_end): Removed.
(local_avl_compa
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (debug): Removed.
(bitmap_union_of_preds_with_entry): New.
(compute_reaching_defintion): New.
(vlmax_avl_p): New.
(enum vsetvl_type): Moved.
(enum emit_type): Moved.
(vlmul_to_str): Moved.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
New.
(pre_vsetvl::pre_global_vsetvl_info): New.
(pass_vsetvl::prune_expressions): Removed.
(pass_vsetvl::compute_local_properties): Removed.
(pass_vsetvl::earliest_fusion
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_avl_def_data): New.
(pre_vsetvl::compute_vsetvl_def_data): New.
(pre_vsetvl::compute_lcm_local_properties): New.
---
gcc/config/riscv/riscv-vsetvl.cc | 395 +++
1 file changed,
PR target/111037
PR target/111234
PR target/111725
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-1.c: Adjust.
* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Adjust.
* gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Adjust.
*
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.def (DEF_INCOMPATIBLE_COND): Removed.
(DEF_SEW_LMUL_RULE): New.
(DEF_SEW_LMUL_FUSE_RULE): Removed.
(DEF_POLICY_RULE): New.
(DEF_UNAVAILABLE_COND): Removed.
(DEF_AVL_RULE): New.
(sew_lmul): New.
vli 15
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c -O3 -g
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c -O3 -g
scan-assembler-times vsetvli 15
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c -O3 -g
scan-assembler-times vsetvli
Okay, thanks anyway.
On 2023/10/19 16:38, Robin Dapp wrote:
Hi Lehua,
thanks for the extensive rework. I'm going to let Juzhe handle the review
since it's his pass and he knows it best. Delegated it to him in patchwork.
Regards
Robin
--
Best,
Lehua (RiVAI)
lehua.d...@rivai.ai
Hi,
This patch adds some missed ForEachMacros to the contrib/clang-format file,
which allows the clang-format tool to format gcc code correctly.
Best,
Lehua
---
contrib/clang-format | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/contrib/clang-format b/contrib/clan
Hi,
This patch fixes the problem that the loop in the tsvc s176 function is
optimized and removed because `iterations/LEN_1D` is 0 (where iterations
is set to 1, LEN_1D is set to 32000 in tsvc.h).
This testcase passed on x86 and AArch64 system.
Best,
Lehua
gcc/testsuite/ChangeLog:
> It's odd that the checksum doesn't depend on the number of iterations done ...
This is because the difference between the calculated result (32063.902344) and
the expected result (32000.00) is small. The current check is that the
result
is considered correct as long as the `value/expected`
> I stitched together appropriate ChangeLog entries and pushed this to
the
> trunk (I don't think Lehua has write access).
Thank you!
Best,
Lehua
Hi,
This patch remove the duplicate `#include "riscv-vector-switch.def"` statement
and add #undef for ENTRY and TUPLE_ENTRY macros later.
Best,
Lehua
---
gcc/config/riscv/riscv-v.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/ri
Hi,
This patch remove the duplicate `#include "riscv-vector-switch.def"` statement
and add #undef for ENTRY and TUPLE_ENTRY macros later.
Best,
Lehua
gcc/ChangeLog:
* config/riscv/riscv-v.cc (struct mode_vtype_group): Remove duplicate
#include.
(ENTRY): Undef.
(TUPLE_EN
> LGTM.
> Thanks.
> Will merge it soon.
Thank you for such a prompt reply.
Hi,
This patch fix the PR 110119.
The reason for this bug is that in the case where the vector register is set
to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option),
TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed
through two scalar register
Hi,
The reason for this bug is that in the case where the vector register is set
to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option),
TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed
through two scalar registers, but when GCC calls FUNCTION_V
Resubmitted a new, more standardized patch(bellow is the new patch link),
thanks.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621683.html
Fix all comment from Juzhe, thanks. Below is the new patch. Please use the
attachment if there is a problem with the format of the patch below.
PR 110119
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for
vector mode
(riscv_pass_by_refer
> so this is intended to fix the PR as well as unblock while we continue
> with the preliminary ABI separately?
Yes, and I will send the new prerelease vector calling convention later.
Best,
Lehua
The V2 patch address comments from Juzhe, thanks.
Hi,
The reason for this bug is that in the case where the vector register is set
to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option),
TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed
through
> \ No newline at end of file
> Add newline for each test.
Address this comment, below is the V2 patch link.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621698.html
Best,
Lehua
> Nit for test.
> +/* { dg-options "-march=rv64gczve32x
> +--param=riscv-autovec-preference=fixed-vlmax" } */
> To
> +/* { dg-options "-march=rv64gc_zve32x
--param=riscv-autovec-preference=fixed-vlmax" } */
Fixed in the V2 patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621698.html), t
Hi,
This tiny patch add a check for extension starts with 'z' or 's' in `-march`
option. Currently this unknown extension will be passed to the assembler, which
then reports an error. With this patch, the compiler will throw a compilation
error if the extension starts with 'z' or 's' is not a stan
Hi,
This tiny patch add --append option to mklog.py that support add generated
ChangeLog to the corresponding patch file. With this option there is no need
to manually copy the generated ChangeLog to the patch file. e.g.:
Run `mklog.py -a /path/to/this/patch` will add the generated ChangeLog
```
Commited to the trunk, thanks Jeff.
-- Original --
From: "Jeff Law"
Hi,
This tiny patch add a check for extension starts with 'z' or 's' in `-march`
option. Currently this unknown extension will be passed to the assembler, which
then reports an error. With this patch, the compiler will throw a compilation
error if the extension starts with 'z' or 's' is not a stan
Thanks for review. I uploaded version V2, which addresses Kito's comments,
along with two changes. The first is to reduce repeated errors, which are
currently
reported at least twice. The second is to report as many mistakes as possible.
V2 URL: https://gcc.gnu.org/pipermail/gcc-patches/2023-Jul
Hi,
This patch fix target/PR110696, recursively add all implied extensions.
Best,
Lehua
PR target/110696
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::handle_implied_ext): recur add all implied extensions.
(riscv_subset_list::check_implied_ex
Commited to the trunk, thank you.
-- Original --
From: "Kito Cheng"
Committed to the trunk, thanks Richard and Juzhe.
1. bootstrap and regression are pass on i386 target (by Pan).
2. no new failed testcases on AArch64 target.
Best,
Lehua
-- Original --
From:
Hi,
Since the latter patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624689.html)
forbidden VLEN > 4096, the testcase attribute-20.c is no long need. This is
obvious.
Best,
Lehua
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-20.c: Removed.
---
gcc/testsuite/gcc.ta
Committed to the trunk, thank you.
-- Original --
From:
"juzhe.zh...@rivai.ai"
Hi,
This patch fix testcase failed when I build RISC-V GCC with -mcmodel=medany
as default. If set to medany, stack_save_restore.c testcase will fail because of
the reduced use of s3 registers in assembly (thus calling __riscv_save/store_3
instead of __riscv_save/store_4). Explicitly add -mcmodel=
Hi Robin,
> Wouldn't you rather want to adjust the test to not check for one
register
> number but 3 or 4 instead?
I think the purpose of this testcase is to check whether the modifications to
the stack frame are as expected, so it is necessary to specify exactly whether
three or four registers
Committed to the trunk, thanks Robin.
> LGTM, thanks:)
Committed to the trunk, thanks Kito and Juzhe.
Hi Robin,
> In general I'm fine with this small change of course, I just wonder if
> the testcase is not brittle anyway. From what I can tell the respective
> change is independent of the actual number of registers so maybe it's enough
> to
> not compare the fully body but just make sure the addi
Committed V2 patch, thank you so much.
-- Original --
From:
"Robin Dapp"
Commited to the trunk, thank you so much.
Hi,
This little patch fix two bugs of mklog.py with --append option.
The first bug is that the regexp used is not accurate enough to
determine the top of diff area. The second bug is that if `---`
is not a true start, it needs to be added back to the patch file.
contrib/ChangeLog:
* mklo
I have posted below the vector register calling convention rules from in the
proposal[1]:
v0 is used to pass the first vector mask argument to a function, and to return
vector mask result from a function. v8-v23 are used to pass vector data
arguments, vector tuple arguments and the rest vector mas
-doc/blob/master/rvv-intrinsic-rfc.md#type-system
[3]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
Lehua Ding (3):
RISC-V: Part-1: Select suitable vector registers for vector type args
and returns
RISC-V: Part-2: Save/Restore vector registers which
Functions which follow vector calling convention variant need be annotated by
.variant_cc directive according the RISC-V Assembly Programmer's Manual and
RISC-V ELF Specification[2].
[1]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
[2]
https://github.com/
Because functions which follow vector calling convention variant has
callee-saved vector reigsters but functions which follow standard calling
convention don't have. We need to distinguish which function callee is so that
we can tell GCC exactly which vector registers callee will clobber. So I enco
Commited, thanks Richard.
Bootstrap and regression passed.
-- Original --
From:
"Richard Biener"
Commited, thanks Richard.
Bootstrap and regression passed.
-- Original --
From:
"Richard Biener"
Hi Martin,
> this patch caused flake8 to complain about contrib/mklog.py:
>
> $ flake8 contrib/mklog.py
> contrib/mklog.py:377:80: E501 line too long (85 > 79 characters)
> contrib/mklog.py:388:26: E127 continuation line over-indented for
visual indent
> contrib/mklog.py:388:36: W605 invalid es
> I am no python expert but the following seems to work:
Thank you so much, it works for me.
Lehua
Hi Martin,
By the way, is there a standard format required for these Python files?
I see that other Python files have similar format error when checked
using flake8. If so, it feels necessary to configure a git hook on git
server
to do this check.
Best,
Lehua
Hi Martin,
Thank you for telling me about the Python code format specification.
I'm no idea how to add checks for pushed commits.
Anyway, first make sure I don't introduce new format errors myself.
Best,
Lehua
From: Ju-Zhe Zhong
PS: Submitted on behalf of Juzhe Zhong
Hi, Richard and Richi.
This patch support floating-point in-order reduction for loop length control.
Consider this following case:
float foo (float *__restrict a, int n)
{
float result = 1.0;
for (int i = 0; i < n; i++)
result +
Hi Richard,
Bootstrap and regression are passed on X86 and
no new testcases fail on AArch64 with V5 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625293.html
V5 patch is ok for trunk?
Best,
Lehua
Commited V5 to the trunk, thanks Richard.
Best,
Lehua
Committed to the trunk, thanks Kito and Robin.
Best,
Lehua
Hi,
Gentle Ping.
I sent a V2 patch as below for an additional fix Python code format error,
which Martin reported, thanks.
Best,
Lehua
contrib/ChangeLog:
* mklog.py: Fix bugs.
---
contrib/mklog.py | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/contrib/mklo
Gentle PING^2, thanks!
Hi Kito,
> > +machine_mode m1_mode = TARGET_VECTOR_ELEN_64
> > +? (TARGET_MIN_VLEN >= 128 ? VNx2DImode : VNx1DImode)
> > +: VNx1SImode;
> This should update since JuZhe has update the mode system :P
Yes, thanks reminder.
> > @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style)
> > Start of
Committed to trunk, thanks Richard and Juzhe.
Committed to the trunk, thanks Kito and Juzhe.
Committed to the trunk, thanks Kito and Juzhe.
Hi,
This patch fix PR110943 which will produce some error code. This is because
the error combine of some pred_mov pattern. Consider this code:
```
#include
void foo9 (void *base, void *out, size_t vl)
{
int64_t scalar = *(int64_t*)(base + 100);
vint64m2_t v = __riscv_vmv_v_x_i64m2 (0,
Hi Jeff,
> The pattern's operand 0 explicitly allows MEMs as do the constraints.
> So forcing the operand into a register just seems like it's papering
> over the real problem.
The added of force_reg code is address the problem preduced after address the
error combine.
The more restrict condti
-doc/blob/master/rvv-intrinsic-rfc.md#type-system
[3]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
Lehua Ding (3):
RISC-V: Part-1: Select suitable vector registers for vector type args
and returns
RISC-V: Part-2: Save/Restore vector registers which
I have posted below the vector register calling convention rules from in the
proposal[1]:
v0 is used to pass the first vector mask argument to a function, and to return
vector mask result from a function. v8-v23 are used to pass vector data
arguments, vector tuple arguments and the rest vector mas
Because functions which follow vector calling convention variant has
callee-saved vector reigsters but functions which follow standard calling
convention don't have. We need to distinguish which function callee is so that
we can tell GCC exactly which vector registers callee will clobber. So I enco
Functions which follow vector calling convention variant need be annotated by
.variant_cc directive according the RISC-V Assembly Programmer's Manual and
RISC-V ELF Specification[2].
[1]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
[2]
https://github.com/
Thanks so much for Kito's online and offline comments.
I have upload V2 patchs which address all comments.
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626935.html
Best,
Lehua
-- Original --
From:
Hi Richard,
Thanks review.
> Just to mention at some point you want to think about the OpenMP SIMD ABI
which
> includes a mangling scheme but would also open up to have different
> calling conventions.> So please keep that usage case in mind, possibly
allowing the vector
> calling convention
Hi,
This patch fix PR110943 which will produce some error code. This is because
the error combine of some pred_mov pattern. Consider this code:
```
void foo9 (void *base, void *out, size_t vl)
{
int64_t scalar = *(int64_t*)(base + 100);
vint64m2_t v = __riscv_vmv_v_x_i64m2 (0, 1);
*(
Hi Jeff,
After reconsidering I think the split of pattern you mention
makes sense to me. I have split the `@pred_movhttps://gcc.gnu.org/pipermail/gcc-patches/2023-August/626981.html
Best,
Lehua
Hi,
This patch revert the convert from vmv.s.x to vmv.v.i and add new pattern
optimize the special case when the scalar operand is zero.
Currently, the broadcast pattern where the scalar operand is a imm
will be converted to vmv.v.i from vmv.s.x and the mask operand will be
converted from 00..01
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