[PATCH 1/7 v2] RISC-V: Add basic XAndes vendor extension support.

This patch add basic support for the following XAndes ISA extensions: XANDESPERF XANDESBFHCVT XANDESVBFHCVT XANDESVSINTLOAD XANDESVPACKFPH XANDESVDOT gcc/ChangeLog: * config/riscv/riscv-ext.def: Include riscv-ext-andes.def. * config/riscv/riscv-ext.opt (riscv_xandes_subext): New

[PATCH 0/7 v2] Add Xandes vender extension support.

he original form [PATCH 6/7] Removed "nds_vfpmad" temporarily before uploading Andes pipeline model. Thanks for your review. Kuan-Lin Chen (7): RISC-V: Add basic XAndes vendor extension support. RISC-V: Add support for the XAndesperf ISA extension. RISC-V: Add support for the XAn

[PATCH 3/7 v2] RISC-V: Add support for the XAndesbfhcvt ISA extension.

This extension defines instructions to perform scalar floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a scalar floating point register. gcc/ChangeLog: * config/riscv/andes.def: Add nds_fcvt_s_bf16 and

[PATCH 7/7 v2] RISC-V: Add support for the XAndesvdot ISA extension.

This extension defines vector instructions to calculae of the signed/unsigned dot product of four SEW/4-bit data and accumulate the result into a SEWbit element for all elements in a vector register. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New class.

[PATCH 2/7 v2] RISC-V: Add support for the XAndesperf ISA extension.

This patch adds support for the XAndesperf ISA extension. The 32-bit AndeStar V5 extension includes branch instructions, load effective address instructions, and string processing instructions for performance improvement. New INSN patterns are added into the new file andes.md as a seprated vender e

[PATCH 4/7 v2] RISC-V: Add support for the XAndesvbfhcvt ISA extension.

This patch add support for XAndesvbfhcvt ISA extension. This extension defines instructions to perform vector floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a vector register. gcc/ChangeLog: * common/

[PATCH 5/7 v2] RISC-V: Add support for the XAndesvsintload ISA extension.

This extension defines vector load instructions to move sign-extended or zero-extended INT4 data into 8-bit vector register elements. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_nibbleload): New class. * config/riscv/andes-vector-builtins-bases.h (nds

[PATCH 6/7 v2] RISC-V: Add support for the XAndesvpackfph ISA extension.

This extension defines vector instructions to extract a pair of FP16 data from a floating-point register. Multiply the top FP16 data with the FP16 elements and add the result with the bottom FP16 data. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_FP_16