Re: [PATCH] fixed testcase riscv/pr103302.c

Hi ShiHua: Thanks for the fix, committed with Andrew's comment and minor fix for commit comment. On Thu, Dec 23, 2021 at 3:41 PM Andrew Pinski via Gcc-patches wrote: > > On Wed, Dec 22, 2021 at 11:37 PM wrote: > > > > From: LiaoShihua > > > > because riscv32 not support __int128, so sk

Re: [PATCH 1/2] RISC-V: Allow extension name contain digit

Committed On Fri, Dec 3, 2021 at 11:51 PM Kito Cheng wrote: > > RISC-V spec only allow alphabetical name for extension before, however > vector extension add several extension named with digits, so we try to > extend the naming rule. > > Ref: > https://github.com/riscv/riscv-isa-manual/pull/718 >

Re: [PATCH 2/2] RISC-V: Minimal support of vector extensions

Committed with minor changelog fix On Fri, Dec 3, 2021 at 11:52 PM Kito Cheng wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.c (riscv_implied_info): Add > vector extensions. > (riscv_ext_version_table): Add version info for vector extensions. > (r

Re: Re: [PATCH] RISC-V: Fix Bug 109092

Committed with commit log tweak: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=02880e7803b19c357718abd2f0d567b4a761f318 On Wed, Mar 15, 2023 at 11:06 AM juzhe.zh...@rivai.ai wrote: > > Yes, I have write access. However, I am new to commit patch to GCC trunk. > I didn't figure out how to commit pa

Re: [PATCH] RISC-V: Fix bugs of internal tests.

Committed with git log tweak: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c413abed869e7e34a86855a015413418f3c6b595 On Mon, Mar 13, 2023 at 3:52 PM wrote: > > From: Ju-Zhe Zhong > > Co-authored-by: kito-cheng > Co-authored-by: kito-cheng > > This patch fixed a bunch of bugs reported by kito.c

Re: [PATCH] RISC-V: Fix PR109228

committed as https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=116a8678840f9f52ec14639ff07e302a8c429f32 with few comment tweak. On Wed, Mar 22, 2023 at 1:06 PM wrote: > > From: Ju-Zhe Zhong > > This patch fix PR109228 > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228 > > gcc/ChangeLog: > >

Re: [PATCH] RISC-V: Fix ICE in LRA for LMUL < 1 vector spillings

Committed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=cd0c433e5faba9a18f64881cd761a53a530aa798 with comment tweak. On Wed, Mar 22, 2023 at 10:50 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global. > (e

Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen

LGTM, but pending this to the GCC 14 queue. On Wed, Mar 22, 2023 at 8:16 PM wrote: > > From: Ju-Zhe Zhong > > Current expansion of vmsge will make RA produce redundant vmv1r.v. > > testcase: > void f1 (void * in, void *out, int32_t x) > { > vbool32_t mask = *(vbool32_t*)in; > asm volatil

Re: [PATCH] RISC-V: Fix RVV ICE && runtine fail

committd as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a481eed8fd01837cdf011ea9a17853505080a888 with comment tweaks On Mon, Mar 20, 2023 at 12:30 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc (eliminate_insn): Fix bugs. > (insert_vsetv

Re: Re: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics.

committed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0e2715176df3787d1470d7b9bde26b1b5e16e1e2 On Mon, Mar 20, 2023 at 8:51 AM juzhe.zh...@rivai.ai wrote: > > The last patch. Kito is still keep testing with pressure tests. > > > > juzhe.zh...@rivai.ai > > From: Jeff Law > Date: 2023-03-20 0

Re: [PATCH] RISC-V: Fix ICE of RVV compare intrinsic

committed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6f6eba35b9f06d35ff7bea81969fe905a5584bdc On Fri, Mar 10, 2023 at 4:09 PM wrote: > > From: Ju-Zhe Zhong > > vfrsub_vf_m.cpp: In function 'int main()': > vfrsub_vf_m.cpp:5:43: error: invalid argument to built-in function >5 | vbool3

Re: [PATCH] RISC-V: Fix loss of function to script 'multilib-generator'

Nice catch, committed to the trunk! On Tue, Mar 21, 2023 at 3:39 PM Songhe Zhu wrote: > > The arch 'rv32imac' will not be created when excuting > './multilib-generator rv32imc-ilp32--a' > > The output is: > MULTILIB_OPTIONS = march=rv32imc mabi=ilp32 > MULTILIB_DIRNAMES = rv32imc ilp32 > MULTILIB

Re: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment

committed, thanks for the reminder :) On Mon, Mar 13, 2023 at 9:40 AM Li, Pan2 via Gcc-patches wrote: > > Kindly reminder for this PR. Thank you all in advance. > > Pan > > -Original Message- > From: Li, Pan2 > Sent: Wednesday, March 8, 2023 7:31 PM > To: gcc-patches@gcc.gnu.org > Cc: juz

Re: [PATCH] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987]

Committed 2 weeks ago but apparently I didn't send mail to say that, thanks Vineet. On Thu, Mar 2, 2023 at 3:56 AM Philipp Tomsich wrote: > > On Wed, 1 Mar 2023 at 20:53, Vineet Gupta wrote: > > > > This showed up as dynamic icount regression in SPEC 531.deepsjeng with > > upstream > > gcc (vs.

Re: [PATCH] RISC-V: Add Z*inx incompatible check in gcc.

HI Jiawei: Thanks for the fix! Two comments: - Could you add testcase like https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/arch-12.c - And I would prefer those check happened in riscv_subset_list::parse @gcc/common/config/riscv/riscv-common.cc On Sun, Mar 26, 2023 at

Re: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair

OK for trunk, thanks :) On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner < christoph.muell...@vrull.eu> wrote: > From: Christoph Müllner > > This patch adds missing mode specifiers for XTheadMemPair INSNs. > > gcc/ChangeLog: > PR target/109296 > * config/riscv/thead.md: Add mis

[PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312]

RVV intrinsic has defined a macro to identity the version of RVV intrinsic spec, we missed that before, thanksful we are catch this before release. gcc/ChangeLog: PR target/109312 * config/riscv/riscv-c.cc (riscv_ext_version_value): New. (riscv_cpu_cpp_builtins): Define __

Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.

I would prefer those checking happened in riscv_subset_list::parse@gcc/common/config/riscv/riscv-common.cc that could be reused when we adding target attribute. And I plan integrate the arch-canonicalize script to just reusing whole arch string parser in GCC 14, so it would be great to have all ch

Re: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.

Maybe something like this? diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index acfd7b92563..aa7edc8cfec 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1155,6 +1155,10 @@ riscv_subset_list::pars

Re: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312]

Applied to trunk :) 於 2023年3月28日 週二，22:34寫道： > LGTM。 > > > > juzhe.zh...@rivai.ai > > From: Kito Cheng > Date: 2023-03-28 22:26 > To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong; > jeffreyalaw > CC: Kito Cheng > Subject: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR10931

Re: [PATCH v3] RISC-V: Add Z*inx imcompatible check in gcc

Thanks Jiawei, committed to trunk! On Wed, Mar 29, 2023 at 12:55 AM Jiawei wrote: > > Z*inx is conflict with float extensions, add incompatible check when > z*inx and f extension both enabled. > > Since all float extension imply f extension and all z*inx extension > imply zfinx extension, so we j

[committed] RISC-V: Fix missing file dependency in RISC-V back-end [PR109328]

gcc/ChangeLog: PR target/109328 * config/riscv/t-riscv: Add missing dependencies. Co-authored-by: Andrew Pinski --- gcc/config/riscv/t-riscv | 43 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/gcc/config/riscv/t-riscv b/

Re: [PATCH] RISC-V: Fix reload fail issue on vector mac instructions

Committed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=802ab7d0db5b5aa46edc8d82526d97258c599927 , thanks On Wed, Mar 29, 2023 at 10:48 AM wrote: > > From: Juzhe-Zhong > > Co-authored-by: kito-cheng > Co-authored-by: kito-cheng > > This path fix ICE of ternary intrinsic: > bug.C:144:2: err

Re: [PATCH] RISC-V: Fix ICE && codegen error of scalar move in RV32 system.

Commit as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=db4f7a9b47d148b5074ac15910124c746fb7a96f with more commit log On Wed, Mar 29, 2023 at 10:43 AM wrote: > > From: Juzhe-Zhong > > bug.C:144:2: error: unrecognizable insn: > 144 | } > | ^ > (insn 684 683 685 26 (set (reg:SI 513) >

Re: [PATCH] riscv: Fix bootstrap [PR109384]

ok, thanks! On Tue, Apr 4, 2023 at 5:01 PM Jakub Jelinek via Gcc-patches wrote: > > Hi! > > The following patch unbreaks riscv bootstrap, where it previously failed > on -Werror=format-diag warning promoted to error. > > Ok for trunk? > > Or shall it say e.g. > "%<-march=%s%>: % extension conflic

Re: [PATCH] riscv: Fix genrvv-type-indexer dependencies

LGTM, thanks :) On Thu, Apr 6, 2023 at 5:46 PM Jakub Jelinek via Gcc-patches wrote: > > Hi! > > I've noticed > make: Circular build/genrvv-type-indexer.o <- gtype-desc.h dependency dropped. > > The following patch fixes that. The RTL_BASE_H variable includes a lot of > headers which the generato

Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 2e91d019f6c..90c69b52bb4 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -43,6 +43,7 @@ > #include "optabs.h" > #include "tm-constrs.h" > #include "rtx-vector-builder.h" > +#include

Re: [PATCH] RISC-V: Add RVV auto-vectorization testcase

You included asm output by accidently :P On Thu, Apr 6, 2023 at 10:45 PM wrote: > > From: Juzhe-Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV > auto-vectorization. > * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase. >

Re: [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern

Is changes for riscv-vsetvl.cc necessary for autovec? or is it additional optimization for the autovec use case? I would suggest splitting that if it's later one. And plz split out fixed-vlmax part into separated patch, that would be easier to review. On Thu, Apr 6, 2023 at 10:44 PM wrote: > > F

Re: [PATCH v2] RISC-V: Fix regression of -fzero-call-used-regs=all

Generally LGTM, just one more comment :) > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 2e91d019f6c..aad046240ee 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl) > } > } >

Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all

> > Do you need to save/restore the vector configuration before and after > > clearing the vector registers?If so, that seems to be missing. If > > not, it seems like a comment explaining why would be useful. > > I'll add some comments in the code and want to explain here first. > We need not

Re: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

Let me give more explanation why RISC-V vector need so many modes than AArch64. The following will use "RVV" as an abbreviation for "RISC-V Vector" instructions. There are two key points here: - RVV has a concept called LMUL - you can understand that as register grouping, we can group up to 8 ad

Re: [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all

Hi Yanzhang: Thanks, applied to trunk now, and also congrats for your first patch on GCC! On Tue, Apr 11, 2023 at 8:00 PM Wang, Yanzhang wrote: > > Hi Kito, Juzhe, Jeff, > > Thanks for your kindly reviews. I have modified based on the comments and ran > the testsuite on my local. Could you plea

Re: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

Hi Richard: > > In order to model LMUL in backend, we have to the combination of > > scalar type and LMUL; possible LMUL is 1, 2, 4, 8, 1/2, 1/4, 1/8 - 8 > > different types of LMUL, and we'll have QI, HI, SI, DI, HF, SF and DF, > > so basically we'll have 7 (LMUL type) * 7 (scalar type) here. > >

Re: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

> > The concept of fractional LMUL is the same as the concept of AArch64's > > partial SVE vectors, > > so they can only access the lowest part, like SVE's partial vector. > > > > We want to spill/restore the exact size of those modes (1/2, 1/4, > > 1/8), so adding dedicated modes for those partial

Re: [PATCH] RISC-V: Fix PR109479

OK for trunk, but plz improve the coverage of the testcase, e.g. vint16mf4_t has fixed too but not tested in testcase. On Wed, Apr 12, 2023 at 7:09 PM wrote: > > From: Ju-Zhe Zhong > > Fix supporting data type according to RVV ISA. > For vint64m*_t, we should only allow them in zve64* instead of

Re: [PATCH] RISC-V: Fix pr109479 RVV ISA inconsistency bug

Thanks for the quick response! verified and pushed to trunk. On Wed, Apr 12, 2023 at 9:56 PM wrote: > > From: Ju-Zhe Zhong > > Fix supporting data type according to RVV ISA. > For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b > (>=64b). > Ideally, we should make error

Re: [PATCH] RISC-V: Set the ABI for the RVV tests

Ok, thanks :) Palmer Dabbelt 於 2023年4月13日 週四，23:12寫道： > The RVV test harness currently sets the ISA according to the target > tuple, but doesn't also set the ABI. This just sets the ABI to match > the ISA, though we should really also be respecting the user's specific > ISA to test. > > gcc/test

Re: [PATCH] RISC-V: Update multilib-generator to handle V

Thanks for catch this, I didn't enable multilib for linux toolchain for a while, I guess we should implement TARGET_COMPUTE_MULTILIB for linux targets to simplify the damm multilib files, but I agree it's too late in the release cycle, so let's fix that in this way for now. So LGTM and OK for trun

Re: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.

OK, thanks for the patch :) On Fri, Apr 14, 2023 at 11:27 AM Li, Pan2 via Gcc-patches wrote: > > Thanks juzhe, update new version [PATCH v3] for even more checks. > > Pan > > From: juzhe.zh...@rivai.ai > Sent: Friday, April 14, 2023 10:46 AM > To: Li, Pan2 ; gcc-patches > Cc: Kito.cheng ; Wang,

Re: [PATCH] RISC-V: Update multilib-generator to handle V

Wait, take second round review: > * All extensions were being prefixed with an underscore, which leads to > some odd combinations like "rv32gc_v", this just adds underscores to > the multi-letter extensions. > * The input base ISAs were being canonicalized, which resulted in some > odd multi

Re: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.

Pushed to trunk :) On Mon, Apr 17, 2023 at 9:47 AM Li, Pan2 via Gcc-patches wrote: > > BTW, this patch will be in GCC 13 or master? The underlying patches may > depend on this tests for ensuring correctness. > > Pan > > -Original Message- > From: Li, Pan2 > Sent: Friday, April 14, 2023 2

[committed] RISC-V: Fix testsuite fail on RV32

gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-2.c: Adjust include way for riscv_vector.h * gcc.target/riscv/rvv/base/spill-sp-adjust.c: Add missing -mabi. --- gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-2.c | 2 +- gcc/testsuite/gcc.tar

[PATCH] Docs: Add doc for RISC-V vector intrinsics

Document which version of RISC-V vector intrinsics has implemented in GCC. gcc/ChangeLog: * doc/extend.texi (Target Builtins): Add RISC-V Vector Intrinsics. (RISC-V Vector Intrinsics): Document GCC implemented which version of RISC-V vector intrinsics and its refer

Re: [PATCH] RISC-V: Adjust the parsing order of extensions to be consistent with riscv-spec and binutils.

Thanks, applied to trunk :) On Tue, Apr 18, 2023 at 5:27 PM Jin Ma wrote: > > The current order of gcc and binutils parsing extensions is inconsistent. > > According to latest risc-v spec, the canonical order in which extension names > must > appear in the name string specified in Table 29.1 is

Re: [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv.

I would prefer drop this patch from this patch series since I believe https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juzhe.zh...@rivai.ai/ is the right fix for this issue. On Tue, Apr 18, 2023 at 2:40 AM Michael Collison wrote: > > From: Kevin Lee > > Kevin Lee > gcc/Chan

Re: [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

Wait, VNx1DImode can be really evaluate to just one element if -march=rv64g_zve64x, I thinks this should be just fixed on backend by this patch: https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juzhe.zh...@rivai.ai/ On Tue, Apr 18, 2023 at 2:12 PM Richard Biener via Gcc-patc

Re: [PATCH] RISC-V: Update multilib-generator to handle V

> Yep, if I drop the non-canonicial strings via > > diff --git a/gcc/config/riscv/multilib-generator > b/gcc/config/riscv/multilib-generator > index 58b7198b243..a63a4d69c18 100755 > --- a/gcc/config/riscv/multilib-generator > +++ b/gcc/config/riscv/multilib-generator > @@ -174

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