[PATCH] Don't call init_caller_save if LRA enabled

LRA generate caller-save register store/restore during split register, not generate by caller-save.c:save_call_clobbered_regs, so initialize this module by init_caller_save is meaningless if LRA enabled 2014-06-05 Kito Cheng * ira.c (ira): Don't call init_caller_save if LRA enabled

[PATCH] Pass correct memory attributes for build constant

Hi all: This patch is fix constant memory's symbol_ref don't have right alignment info since `exp` don't set alignment (and should not set alignment info for `exp`) , use `decl` to set_mem_attributes for right alignment info. ChangLog 2014-06-25 Kito Cheng

Re: [PATCH] Pass correct memory attributes for build constant

@ sp needed ldr lr, [sp], #4 bx lr ... On Thu, Jun 26, 2014 at 5:01 AM, Jeff Law wrote: > On 06/25/14 09:35, Kito Cheng wrote: >> >> Hi all: >>This patch is fix constant memory's symbol_ref don't have right >> alignment info since `exp`

Re: [PATCH] Pass correct memory attributes for build constant

>>test.c: >>extern bar(unsigned char p[3][2]); >>void foo(int i) >>{ >> unsigned char data[3][2] = {{1,1}, {1,0}, {1,1}}; >> >> bar(data); >>} > First, note, I'm not an ARM expert. However, the first question I > have is are we sure the initializer is always going to be suitably > aligned?

Re: [patch] fix regrename pass to ensure renamings produce valid insns

Hi all: This patch seem will broken when disable assert checking for c6x Index: gcc/config/c6x/c6x.c === --- gcc/config/c6x/c6x.c (revision 225104) +++ gcc/config/c6x/c6x.c (working copy) @@ -3516,7 +3516,7 @@ try_rename_operands

Drop -Wswitch-bool warning in function.c

Bootstrapped & regression-tested on x86_64-linux-gnu :) 2015-07-08 Kito Cheng * function.c (stack_protect_epilogue): Use if rather than switch for check targetm.have_stack_protect_test(). From 0306990aac578167872a80ab55085d335e2bea14 Mon Sep 17 00:00:00 2001 From: Kito C

Re: Drop -Wswitch-bool warning in function.c

bool type :) On Wed, Jul 8, 2015 at 9:30 PM, Marek Polacek wrote: > On Wed, Jul 08, 2015 at 04:49:19PM +0800, Kito Cheng wrote: >> Bootstrapped & regression-tested on x86_64-linux-gnu :) >> >> 2015-07-08 Kito Cheng >> >> * function.c (stack_protect_

Re: Drop -Wswitch-bool warning in function.c

Hi Jeff: Thanks your review and approve, however I don't have commit right yet, can you help me to commit it :) thanks On Thu, Jul 9, 2015 at 5:00 AM, Jeff Law wrote: > On 07/08/2015 02:49 AM, Kito Cheng wrote: >> >> Bootstrapped & regression-tested on x86_64-linux

[PATCH] Update libgcc.texi to match implementation in libgcc/libgcc2.c

Hi all: This patch update `Bit operations` section in libgcc.text, most bit operation function is take an unsigned integer instead of signed integer in libgcc/libgcc2.c [1], and it seem more make sense :) ChangeLog 2014-10-28 Kito Cheng * doc/libgcc.texi: Update text to match

Re: [PATCH] Update libgcc.texi to match implementation in libgcc/libgcc2.c

ping! On Tue, Oct 28, 2014 at 11:19 AM, Kito Cheng wrote: > Hi all: > > This patch update `Bit operations` section in libgcc.text, most bit > operation function is take an unsigned integer instead of signed > integer in libgcc/libgcc2.c [1], and it seem more make sense :) > >

[PATCH] Check -shared is available for pr87906's tesstcase

gcc/testsuite/ChangeLog: * g++.dg/lto/pr87906_0.C: Add dg-require-effective-target shared check. --- gcc/testsuite/g++.dg/lto/pr87906_0.C | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/g++.dg/lto/pr87906_0.C b/gcc/testsuite/g++.dg/lto/pr87906_0.C index 434d9fbe142..6a0

[PATCH][COMMITTED] RISC-V: Fix testcase on rv64

/gcc.target/riscv/attribute-10.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d878013c432..e54fa5760bd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-08-01 Kito Cheng

[PATCH] RISC-V: Promote type correctly for libcalls

- argument and return value for libcall won't promote at default_promote_function_mode_always_promote, however we expect it should sign-extend as normal function. - Witout this patch, this test case will fail at -march=rv64i -mabi=lp64. - The implementation of riscv_promote_function_mode

[PATCH] Check -shared is available for tesstcases

gcc/testsuite/ChangeLog: * g++.dg/lto/pr87906_0.C: Add dg-require-effective-target shared check. * g++.dg/lto/pr89330_0.C: Ditto. --- gcc/testsuite/g++.dg/lto/pr87906_0.C | 1 + gcc/testsuite/g++.dg/lto/pr89330_0.C | 1 + 2 files changed, 2 insertions(+) diff --git a/gcc/testsuit

Re: [PATCH] Check -shared is available for pr87906's tesstcase

This patch is deprecated, newer one is here: https://gcc.gnu.org/ml/gcc-patches/2019-08/msg00026.html and it include fix for another testcase. On Wed, Jul 31, 2019 at 5:22 PM Kito Cheng wrote: > > gcc/testsuite/ChangeLog: > > * g++.dg/lto/pr87906_0.C: Add dg-require-effe

Re: [PATCH] Check -shared is available for tesstcases

Committed as r273994 with minor change, since pr89330_0.C has fixed by r273973 On Fri, Aug 2, 2019 at 4:41 AM Jim Wilson wrote: > > On Thu, Aug 1, 2019 at 4:58 AM Kito Cheng wrote: > > gcc/testsuite/ChangeLog: > > * g++.dg/lto/pr87906_0.C: Add dg-require-effec

Re: [PATCH] RISC-V: Promote type correctly for libcalls

> > gcc/ChangeLog > > * config/riscv/riscv.c (riscv_promote_function_mode): New. > > (TARGET_PROMOTE_FUNCTION_MODE): Use riscv_promote_function_mode. > > gcc/testsuite/ChangeLog > > * gcc.target/riscv/promote-type-for-libcall.c: New. > > Yes, this looks correct to me, though

[PATCH v2] RISC-V: Promote type correctly for libcalls

- argument and return value for libcall won't promote at default_promote_function_mode_always_promote, however we expect it should sign-extend as normal function. - Witout this patch, this test case will fail at -march=rv64i -mabi=lp64. - The implementation of riscv_promote_function_mode

Re: [PATCH v2] RISC-V: Promote type correctly for libcalls

Committed as r274107 Hi Jakub, Richard: This patch is fix ABI bug for libcall on RISC-V, we've also tested on gcc 8 and 9, it's ok for gcc 9 and 8? Thanks. On Fri, Aug 2, 2019 at 11:52 PM Jim Wilson wrote: > > On Fri, Aug 2, 2019 at 12:11 AM Kito Cheng wrote: &

[PATCH] RISC-V: Handle extensions combination correctly in multilib-generator.

Input string consist of four parts: --- and generator doing combination with part, but it just append the extension at the end of arch string, it might generate invalid arch. For example, without this patch `./multilib-generator rv32imafc-ilp32--d` will generate: MULTILIB_OPTIONS = march=rv32

Re: [PATCH v2] RISC-V: Promote type correctly for libcalls

Committed to gcc-9 as r274108 and gcc-8 as r274113 On Mon, Aug 5, 2019 at 3:29 PM Richard Biener wrote: > > On Mon, 5 Aug 2019, Kito Cheng wrote: > > > Committed as r274107 > > > > Hi Jakub, Richard: > > > > This patch is fix ABI bug for libcall on RISC-

Re: [PATCH] RISC-V: Handle extensions combination correctly in multilib-generator.

Hi Jim. Andreas: Thanks your review :) Committed with English improvements and ChangeLog update as r274137 On Tue, Aug 6, 2019 at 5:48 AM Jim Wilson wrote: > > On Mon, Aug 5, 2019 at 1:20 AM Kito Cheng wrote: > > gcc/ChangeLog > > * gcc/config/riscv/multilib

[PATCH] RISC-V: Handle g extension in multilib-generator

gcc/ChangeLog * gcc/config/riscv/multilib-generator: (canonical_order): Add 'g'. (arch_canonicalize): Support rv32g and rv64g and fix error handling. --- gcc/config/riscv/multilib-generator | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/confi

Re: [PATCH] RISC-V: Handle g extension in multilib-generator

Committed as r274156 On Wed, Aug 7, 2019 at 3:37 AM Jim Wilson wrote: > > On Mon, Aug 5, 2019 at 11:56 PM Kito Cheng wrote: > > gcc/ChangeLog > > * gcc/config/riscv/multilib-generator: (canonical_order): Add 'g'. > > (arch_canonicalize): Sup

[PATCH] PR target/91441 - Turn off -fsanitize=kernel-address if TARGET_ASAN_SHADOW_OFFSET is not implemented.

- -fsanitize=kernel-address will call targetm.asan_shadow_offset () at asan_shadow_offset, so it will crash if TARGET_ASAN_SHADOW_OFFSET is not implemented, that's mean -fsanitize=kernel-address is not supported for target without TARGET_ASAN_SHADOW_OFFSET implementation. gcc/ChangeLog:

Re: [PATCH] PR target/91441 - Turn off -fsanitize=kernel-address if TARGET_ASAN_SHADOW_OFFSET is not implemented.

Hi Jeff: Thanks, committed as r274631. On Fri, Aug 16, 2019 at 11:51 PM Jeff Law wrote: > > On 8/15/19 8:45 PM, Kito Cheng wrote: > > - -fsanitize=kernel-address will call targetm.asan_shadow_offset () > >at asan_shadow_offset, so it will crash if TARGET_ASAN_SHADOW_OF

[PATCH] RISC-V: Add testcase for testing li pseudo instruction

gcc/testsuite/ChangeLog: gcc.target/riscv/li.c: New test. --- gcc/testsuite/gcc.target/riscv/li.c | 36 + 1 file changed, 36 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/li.c diff --git a/gcc/testsuite/gcc.target/riscv/li.c b/gcc/testsuite

Re: [PATCH] RISC-V: Add testcase for testing li pseudo instruction

Committed as r274920 On Sat, Aug 24, 2019 at 6:08 AM Jim Wilson wrote: > > On Fri, Aug 23, 2019 at 12:13 AM Kito Cheng wrote: > > gcc/testsuite/ChangeLog: > > gcc.target/riscv/li.c: New test. > > Thanks. This looks good. > > This is incidentally a test

Re: [PATCH] RISC-V: Allow more load/stores to be compressed

Hi Craig: Some general review comment: - Split new pass into new file. - Add new option to enable/disable this pass. - Could you extend this patch to support lw/sw/ld/sd/flw/fsw/fld/fsd? I think there is lots of common logic for supporting other types compressed load/store instruction, but I'd

Re: [PATCH] RISC-V: Fix bad insn splits with paradoxical subregs.

Hi Jakub, Richard: This commit is fixing wrong code gen for RISC-V, does it OK to backport to GCC 9 branch? On Fri, Sep 6, 2019 at 4:34 AM Jim Wilson wrote: > > Shifting by more than the size of a SUBREG_REG doesn't work, so we either > need to disable splits if an input is paradoxical, or else

Re: [PATCH] RISC-V: Fix bad insn splits with paradoxical subregs.

Hi Richard: Got it, thanks :) On Wed, Sep 18, 2019 at 6:25 PM Richard Biener wrote: > > On Wed, 18 Sep 2019, Kito Cheng wrote: > > > Hi Jakub, Richard: > > > > This commit is fixing wrong code gen for RISC-V, does it OK to > > backport to GCC 9 branch? > &

[COMMITTED][GCC9] Backport RISC-V: Fix bad insn splits with paradoxical subregs.

+++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-09-19 Kito Cheng + + Backport from mainline + 2019-09-05 Jakub Jelinek + Jim Wilson + + PR target/91635 + * config/riscv/riscv.md (zero_extendsidi2, zero_extendhi2, + extend2): Don't split if + paradoxical_subreg_p (operands[0]). + (*lshrsi

[COMMITTED][GCC9] Backport RISC-V: Fix more splitters accidentally calling gen_reg_rtx.

og @@ -1,3 +1,32 @@ +2019-09-20 Kito Cheng + + Backport from mainline + 2019-09-18 Jim Wilson + + PR target/91683 + * config/riscv/riscv-protos.h (riscv_split_symbol): New bool parameter. + (riscv_move_integer): Likewise. + * config/riscv/riscv.c (riscv_split_integer): Pass FAL

[PATCH] Update soft-fp from glibc.

tions. - 69a01461ee1417578d2ba20aac935828b50f1118 soft-fp/extended.h soft-fp/half.h soft-fp/single.h soft-fp/double.h soft-fp/quad.h - Do not use packed structures in soft-fp. - 049375e2b5fc707436fd5d80337c253beededb2d libgcc/ChangeLog 2018-11-07 Kito Cheng * soft-fp/adddf3.c: Update from

Re: [patches] Re: [PATCH] Update soft-fp from glibc.

Hi Joseph: I don't have commit right, could you help me to commit that, thanks :) On Thu, Nov 8, 2018 at 1:14 AM Joseph Myers wrote: > > This patch is OK. > > -- > Joseph S. Myers > jos...@codesourcery.com

[PATCH, committed] Add myself to MAINTAINERS

ChangeLog: 2019-07-08 Kito Cheng * MAINTAINERS (Write After Approval): Add myself. --- MAINTAINERS (revision 273194) +++ MAINTAINERS (revision 273195) @@ -651,6 +651,7 @@ Jon Ziegler Roman Zippel Josef Zlomek

Re: [PATCH, committed] Add myself to MAINTAINERS

Hi Rainer: Thanks your reminder, I've fix it now. On Mon, Jul 8, 2019 at 4:14 PM Rainer Orth wrote: > > Kito Cheng writes: > > > ChangeLog: > > > > 2019-07-08 Kito Cheng > > > > * MAINTAINERS (Write After Approval): Add myse

Re: [PATCH, committed] Add myself to MAINTAINERS

Hi Jakub: Thanks, fixed and checked with maintainers-verify.sh now. 2019-07-08 Kito Cheng * MAINTAINERS (Write After Approval): Remove myself, already listed in RISC-V port maitainer. Index: MAINTAINERS

Re: [PATCH] RISC-V: Fix splitter for 32-bit AND on 64-bit target.

Hi I'd like to back port this patch to GCC 8 and 9, should I send another patch mail or just wait ack from release manager? On Mon, Jul 8, 2019 at 6:48 PM Jim Wilson wrote: > > Fixes github.com/riscv/riscv-gcc issue #161. We were accidentally using > BITS_PER_WORD to compute shift counts when

[COMMITTED][GCC9] Backport RISC-V: Fix splitter for 32-bit AND on 64-bit target.

cv.md (lshrsi3_zero_extend_3+1): Use operands[1] bitsize instead of BITS_PER_WORD. gcc/testsuite/ * gcc.target/riscv/shift-shift-2.c: Add one more test. gcc/ChangeLog: 2019-07-18 Kito Cheng Backport from mainline 2019-07-08 Andrew Waterman Jim Wilson * config/riscv/riscv.md (lshrsi3_zero_exten

[PATCH] [NDS32] Fix nds32_split_ashiftdi3 with large shift amount

From: Kito Cheng ChangeLog: gcc/ * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Fix wrong code gen with large shift amount. --- gcc/config/nds32/nds32-md-auxiliary.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/gcc

[PATCH v2 0/2] RISC-V: Support ELF attribute for GCC

This version 2 of patch series for of RISC-V ELF attribute[1], first version can be found in[2-4]. Most changes between last version is typo fixing and coding sytle fix, and a missing re-generated configure file. [1] https://github.com/riscv/riscv-elf-psabi-doc/pull/71 [2] [PATCH 0/2] RISC-V: Su

[PATCH v2 2/2] RISC-V: Support ELF attribute

From: Kito Cheng This patch added a configure time option, --with-riscv-attribute=[yes|no|default], run time option, -mriscv-attribute to control the output of ELF attribute. This feature is only enabled by default for ELF/Bare mental target configuration. Kito Cheng Monk Chiang

[PATCH v2 1/2] RISC-V: Accept version, supervisor ext and more than one NSE for -march.

From: Kito Cheng Kito Cheng Monk Chiang ChangeLog: gcc: * common/config/riscv/riscv-common.c: Include config/riscv/riscv-protos.h. (INCLUDE_STRING): Defined. (RISCV_DONT_CARE_VERSION): Defined. (riscv_subset_t): Declare. (riscv_subset_t

[PATCH] RISC-V: Update testcase.

From: Kito Cheng gcc.target/riscv/arch-1.c getting failed after r269586, because it wrapping all option names in gcc internal messages with %< and %>, it make option name will print with single quote, and then mis-match the result in the test case. gcc/testsuite: Kito Cheng Cha

[PATCH 2/7] [NDS32] Fix testsuite for nds32 target

From: Kito Cheng Chung-Ju Wu Shiva Chen ChangeLog: gcc/testsuite/ * gcc.c-torture/execute/20010122-1.c: Add -malways-save-lp for nds32. * gcc.c-torture/execute/pr60822.c: Add -mcmodel=large for nds32. * gcc.c-torture/execute/pr79286.c: Ditto

[PATCH 1/7] [NDS32] Provide one valid nds32 assembly instruction to check assembler debugging options and features.

From: Chung-Ju Wu Chung-Ju Wu ChangeLog gcc/ * configure.ac: Add nds32 target for dwarf2 debug_line checking. * configure: Regenerated. --- gcc/configure| 2 +- gcc/configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/configure b/gcc/conf

[PATCH 3/7] [NDS32] Rewrite PIC/TLS patterns.

From: Monk Chiang Monk Chiang Kito Cheng Shiva Chen ChangeLog gcc/ * config/nds32/nds32-md-auxiliary.c (nds32_legitimize_pic_address): Use new PIC pattern. (nds32_legitimize_tls_address): Use new TLS pattern. (nds32_output_symrel): New. * config

[PATCH 4/7] [NDS32] nds32*-linux target using init_array/finit_array for ctor/dtor.

From: Monk Chiang Monk Chiang ChangeLog * config.gcc (nds32*-*-linux*): Set gcc_cv_initfini_array to yes. --- gcc/config.gcc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config.gcc b/gcc/config.gcc index 3eb2e80..a6d63dd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@

[PATCH 5/7] [NDS32] Refine force unwind, linux kernel only using RT_SIGRETURN.

From: Monk Chiang Monk Chiang ChangeLog libgcc/ * config/nds32/linux-unwind.h (SIGRETURN): Remove. (RT_SIGRETURN): Update. (nds32_fallback_frame_state): Update. --- libgcc/config/nds32/linux-unwind.h | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff

[PATCH 6/7] [NDS32] Handle subreg correctly in wext_odd_dep_p.

From: Kito Cheng Kito Cheng Shiva Chen ChangeLog: gcc/ * config/nds32/nds32-pipelines-auxiliary.c (wext_odd_dep_p): Handle subreg. gcc/testsuite * gcc.target/nds32/wext-dep.c: New. --- gcc/config/nds32/nds32-pipelines-auxiliary.c | 16 gcc

[PATCH 7/7] [NDS32] Fix nds32_split_ashiftdi3 with large shift amount

From: Kito Cheng Kito Cheng Shiva Chen ChangeLog: gcc/ * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Fix wrong code gen with large shift amount. gcc/testsuite/ * gcc.target/nds32/ashiftdi3.c: New. --- gcc/config/nds32/nds32-md-auxiliary.c | 21

[PATCH 1/2] RISC-V: Accept version, supervisor ext and more than one NSE for -march.

From: Kito Cheng Kito Cheng Monk Chiang ChangeLog: gcc: * common/config/riscv/riscv-common.c: Include config/riscv/riscv-protos.h. (INCLUDE_STRING): Defined. (RISCV_DONT_CARE_VERSION): Defined. (riscv_subset_t): Declare. (riscv_subset_list

[PATCH 2/2] RISC-V: Support ELF attribute

From: Kito Cheng This patch added a configure time option, --with-riscv-attribute=[yes|no|default], run time option, -mriscv-attribute to control the output of ELF attribute. This feature is only enabled by default for ELF/Bare mental target configuration. Kito Cheng Monk Chiang ChangeLog

[PATCH 0/2] RISC-V: Support ELF attribute for GCC.

This patch series is implementation of RISC-V ELF attribute[1], it consists of two part, first part is improve the -march string parser, in order to support arch string with version and all kind of extension in the RISC-V ISA spec v2.2[2], and second part is attribute directive generation, includin

Re: Init df for split pass since some target use REG_NOTE in split pattern

Hi Steven: You are right, I have build arm toolchain today, it's crash when building libgcc since there is no valid CFG in split_all_insns_noflow. Hi Jeff: Maybe we need split_reg_dead_p and split_reg_unused_p like peephole2 have peep2_reg_dead_p? On Wed, Aug 10, 2016 at 3:54 AM, Steven Bossch

Re: [PATCH] [RISCV] Add RTEMS support

Hi Sebastian: LGTM, I've test riscv32-rtems-gcc is buildable. Thanks for you patch :) Hi Palmer: Could you help to commit this patch ? Thanks. On Thu, Jul 27, 2017 at 7:05 PM, Sebastian Huber wrote: > gcc/ > * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*). > * config/riscv/

[PATCH] PR79079 Fix __builtin_mul_overflow code gen for !TRULY_NOOP_TRUNCATION target

h-overflow-12.c/builtin-arith-overflow-p-12.c and no introduce new regression on x86-64 and riscv32 gcc/ChangeLog: 2017-01-16 Kito Cheng Kuan-Lin Chen PR target/PR79079 * gcc/internal-fn.c (expand_mul_overflow): Use convert_modes instead of gen_low

Re: [PATCH] PR79079 Fix __builtin_mul_overflow code gen for !TRULY_NOOP_TRUNCATION target

trunk and gcc-6-branch ? gcc/ChangeLog: 2017-01-16 Kito Cheng Kuan-Lin Chen PR target/PR79079 * internal-fn.c (expand_mul_overflow): Use convert_modes instead of gen_lowpart. On Mon, Jan 16, 2017 at 6:13 PM, Matthew Fortune wrote: > Kito Cheng writes:

Re: [PATCH] PR79079 Fix __builtin_mul_overflow code gen for !TRULY_NOOP_TRUNCATION target

Hi Jakub: Got it, thanks, however I don't have commit right yet, can you commit it? On Tue, Jan 17, 2017 at 6:13 PM, Jakub Jelinek wrote: > On Tue, Jan 17, 2017 at 06:09:29PM +0800, Kito Cheng wrote: >> Hi Jakub: >> >> Thanks for your review, attachment is v2 patch, i

Re: FIx riscv port building with the trunk

Hi Jeff: It's make older gcc version can't build RISC-V port, how about use gcc_fallthrough instead? diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index f4c1f23..d1af07f5 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2089,13 +2089,13 @@ riscv_emit_flo

Re: [PATCH] Add RISC-V Maintainers

ping. On Thu, Feb 9, 2017 at 2:50 AM, Palmer Dabbelt wrote: > 2017-02-08 Palmer Dabbelt > > * MAINTAINERS (CPU Port Maintainers): Add Kito Cheng, Palmer Dabbelt, > and Andrew Waterman as the RISC-V maintainers. > --- > ChangeLog | 5 + > MAINTAINE

Check fpic is ok for target in pr69102.c

Hi all: pr69102.c use -fPIC flag in dg-options but not check is available for target, so I add "dg-require-effective-target fpic" for it. ChangeLog 2016-07-05 Kito Cheng * gcc.c-torture/compile/pr69102.c: Require fpic support. From caa51d92e620694ee1365ce0f77ac2b152662982

Re: Check fpic is ok for target in pr69102.c

Hi Mike: thanks for your review :) On Wed, Jul 6, 2016 at 2:54 AM, Mike Stump wrote: > On Jul 5, 2016, at 1:39 AM, Kito Cheng wrote: >> >> pr69102.c use -fPIC flag in dg-options but not check is available for >> target, so I add "dg-require-effective-target fpic&q

Init df for split pass since some target use REG_NOTE in split pattern

Hi all: Some target(for example i386, sh and h8300) use find_regno_note in split pattern but df infrastructure seem not initialize at split pass, so it may got wrong note since it's out-of-date. ChangeLog 2016-07-25 Kito Cheng * gcc/recog.c (split_all_insns): Initialize df for

Re: Init df for split pass since some target use REG_NOTE in split pattern

mode, offset); operands[1] = simplify_gen_subreg ( SImode, operands[1], DImode, offset); }) On Tue, Jul 26, 2016 at 3:48 AM, Jeff Law wrote: > On 07/25/2016 12:35 PM, Richard Biener wrote: >> >> On July 25, 2016 5:56:29 PM GMT+02:00, Jeff Law wrote: &

Re: Init df for split pass since some target use REG_NOTE in split pattern

Hi Jeff: > This seems better suited as a generic optimization than hidden away in a > backend. > > AFAICT you're just noticing a word of the output operand is dead and eliding > the load/store for that word. > > In fact, I'm a bit surprised nothing has optimized this away by the time > reload/LRA i

[PATCH] Fix PR78230

gcc/testsuite/ChangeLog: 2016-11-09 Kito Cheng PR target/78230 * gcc.dg/torture/pr66178.c (test): Use uintptr_t instead of int. (test2) Ditto. From 73ff22745720ecfc2a33148f68ff7e0f36c1144b Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 9 Nov 2016 10:39:59 +0800

Re: [PATCH] Fix PR78230

This change also verified with gcc 6.1 and 5.4 it can pass with gcc 6.1 and make gcc 5.4 ICE after this change. On Wed, Nov 9, 2016 at 10:43 AM, Kito Cheng wrote: > gcc/testsuite/ChangeLog: > > 2016-11-09 Kito Cheng > > PR target/78230 > * gcc.dg/torture/pr6

Re: [PATCH] Fix PR78230

Hi Jeff: Thanks your review and approve, however I don't have commit right yet, can you help me to commit it :) thanks On Wed, Nov 23, 2016 at 1:04 AM, Jeff Law wrote: > > On 11/08/2016 07:43 PM, Kito Cheng wrote: >> >> gcc/testsuite/ChangeLog: >> >> 2016-

[PATCH] LRA: Fix caller-save store/restore instruction for large mode

this on IRC, so I don't send the patch last year, however ARM guys seem got this problem too, so I think it's time to send this patch :) ChangeLog 2015-01-05 Kito Cheng * lra-constraints.c (split_reg): Fix caller-save store/restore instruction genera

Re: [PATCH] LRA: Fix caller-save store/restore instruction for large mode

Hi Jeff: It's updated patch,bootstrapped and run regression tested on arm-eabi, arm-none-linux-uclibcgnueabi, x86_64-unknown-linux-gnu and nds32le-elf without introducing regression. Thanks for your review :) 2015-01-07 Kito Cheng PR target/64348 * lra-constrai

Re: [PATCH] LRA: Fix caller-save store/restore instruction for large mode

icate this case into gcc.target/arm/ :) /* { dg-do compile } */ /* { dg-options "-O3 -fPIC -marm -mcpu=cortex-a8" } */ On Wed, Jan 7, 2015 at 4:50 PM, Bin.Cheng wrote: > On Wed, Jan 7, 2015 at 4:03 PM, Kito Cheng wrote: >> Hi Jeff: >> >> It's updated patch,bootstr

Re: [PATCH] LRA: Fix caller-save store/restore instruction for large mode

Hi Jeff: After discussion with Bin, he prefer just use gcc.c-torture/execute/scal-to-vec1.c instead of introduce new one, do you have any further comment on this patch? On Thu, Jan 8, 2015 at 9:29 AM, Bin.Cheng wrote: > On Wed, Jan 7, 2015 at 8:28 PM, Kito Cheng wrote: >> Hi Bin: >

Re: [PATCH] Add missing size directive for arm-*-elf

On Tue, Sep 9, 2014 at 10:06 PM, Andreas Schwab wrote: > Kito Cheng writes: > >> .align 2 >> bufbuf.4078: >> .space 8 >> ... >> .ident "GCC: (GNU) 5.0.0 20140828 (experimental)" >> >> >> And then the size info will missing: >>

Re: [PATCH] Add header guard to several header files.

Updated patch On Wed, Sep 17, 2014 at 9:17 PM, Kito Cheng wrote: > Updated patch > > On Mon, Sep 8, 2014 at 9:46 PM, Kito Cheng wrote: >> >> ping! >> >> On Tue, Sep 2, 2014 at 12:37 AM, Kito Cheng wrote: >> > Hi Joseph: >> > >> > Th

Re: [PATCH] Add header guard to several header files.

Hi Joseph: Here is updated patch and ChangeLog, However I don't have commit write yet, can you help me to commit it? thanks btw, I has already signed FSF agreement:) 2014-09-19 Kito Cheng except.h: Fix header guard. addresses.h: Add missing header guard. cfghooks.h: Lik

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

Hi Jeff: > I fixed up some minor whitespace issues and committed your patch. Thanks for your help :)

Re: Patch committed: Fix ChangeLog entry

Thanks :) On Wed, Jan 22, 2014 at 1:15 AM, Richard Sandiford wrote: > Ian Lance Taylor writes: >> This patch moves to the gcc/ChangeLog file a gcc ChangeLog entry that >> was incorrectly added to the top-level ChangeLog file. Changes to >> ChangeLog files do not themselves get ChangeLog entries

[PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

od for optimize code size but get worse for performance such as nds32. so I think make it's became a C expression style marco is the solution, let back-end decide when we need HONOR_REG_ALLOC_ORDER instead of decide it during build time. 2014-02-26 Kito Cheng * defaults.h (HONOR_REG_

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

ode] - 1); +cost += add_cost; +full_cost += add_cost; + } + } + if (min_cost > cost) min_cost = cost; if (min_full_cost > full_cost) On Wed, Feb 26, 2014 at 11:47 PM, Kito Cheng wrote: > This patch change the usage for HONOR_REG_ALLOC_ORDER, currently it's >

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

Ping. On Thu, Feb 27, 2014 at 12:32 PM, Kito Cheng wrote: > Hi all: > > Sorry for repeat patch content in last mail, here is the clean version > for this patch. > > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index 7ca47a7..1638332 100644 > --- a/gcc/conf

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

19,21 @@ assign_hard_reg (ira_allocno_t a, bool retry_p) >>>continue; >>> cost = costs[i]; >>> full_cost = full_costs[i]; >>> -#ifndef HONOR_REG_ALLOC_ORDER >>> - if ((saved_nregs = calculate_saved_nregs (hard_regno, mode)) != 0) >

[PATCH] Prevent out of bound access for multilib_options

`q` will out of bound access if `*q` already reach the end of multilib_options, so check it before increment to prevent condition check part out of bound access. btw, this bug is detected by address sanitizer. 2014-04-09 Kito Cheng * gcc.c (used_arg): Prevent out of bound access for

Re: [PATCH] Prevent out of bound access for multilib_options

dzone:f9 Global init order: f6 Poisoned by user: f7 ASan internal: fe ==26436== ABORTING On Wed, Apr 9, 2014 at 10:03 PM, Jakub Jelinek wrote: > On Wed, Apr 09, 2014 at 10:00:38PM +0800, Kito Cheng wrote: >> `q` will out of bound access if `*q` already reac

Re: [PATCH] Prevent out of bound access for multilib_options

ns) so the `if` is not taken at gcc.c:7509 next, `q++` at gcc.c:7493, it's now `q` == multilib_options + strlen(multilib_options) + 1!!! and finally access `*q` for check `*q` != '\0', out of bound access. On Wed, Apr 9, 2014 at 10:21 PM, Kito Cheng wrote: > for ex

Re: [PATCH] Prevent out of bound access for multilib_options

Hi Jakub: Thanks your review and approve, however I don't have commit right yet, can you help me to commit it :) And here is updated patch in attachment, thanks! On Mon, Apr 14, 2014 at 8:12 PM, Jakub Jelinek wrote: > On Wed, Apr 09, 2014 at 10:00:38PM +0800, Kito Cheng wrote: >>

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

Hi Vladimir: > Although this patch is safe. I guess it could wait for stage 1 as right now > we don't need this functionality. > > The patch is ok for the stage1 which is probably about a month away. ping is this patch ok now? thanks:) > Thanks for the patch.

Re: [PATCH] Change HONOR_REG_ALLOC_ORDER to a marco for C expression

Hi Vladimir: thanks your replay and approve, however I don't have commit right yet, can you help to commit it? thanks! On Wed, Apr 16, 2014 at 8:10 PM, Vladimir Makarov wrote: > On 2014-04-15, 9:26 AM, Kito Cheng wrote: >> >> Hi Vladimir: >> >>> Although th

Re: [RFC PATCH] RISC-V: Implement riscv_minimal_hwprobe_feature_bits

I suggest not handling the extension implication rules. This way, it can simplify the logic and reduce the cost of run-time checks. Also, you need to consider situations where that extension can't be detected. And last, I would like to defer this until run-time resolver patch coming, but welcome

Re: [PATCH] RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode

LGTM, I just saw that yesterday as well, fortunately, I haven't started fixing yet. :P On Tue, Oct 15, 2024 at 9:43 AM wrote: > > From: Pan Li > > Some saturation related alu testcases missed additional option > for expand check, which result in some UNRESOLVED issues. This > patch would like

Re: [PATCH v8] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

Pushed with minor fixes for non-linux build :) On Mon, Oct 14, 2024 at 4:25 PM Kito Cheng wrote: > > LGTM, will commit after pass my local build/test :) > > On Mon, Oct 14, 2024 at 4:08 PM Yangyu Chen > wrote: > > > > From: Kito Cheng > > > > This provi

Re: [PATCH v7] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

> + if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_C) > +{ > + SET_EXT (C); > + SET_EXT (ZCA); > + if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_FD) > + { > + SET_EXT (ZCF); Zcf if F is specified (RV32 only) https://github.com/riscv/riscv-isa-manual/blob/main/src/

Re: [PATCH v7] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

On Mon, Oct 14, 2024 at 1:40 PM Yangyu Chen wrote: > > > > > On Oct 14, 2024, at 12:32, Kito Cheng wrote: > > > > I prefer not to handle the extension implication rules, as it's easy > > for them to get out of sync, and this should be the linux kernel

Re: [PATCH v7] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

I prefer not to handle the extension implication rules, as it's easy for them to get out of sync, and this should be the linux kernel's responsibility rather than libgcc's. > +struct { > + unsigned vendorID; This field is gone since it moved to __riscv_cpu_model > + unsigned length; > + unsig

Re: [PATCH v8] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

LGTM, will commit after pass my local build/test :) On Mon, Oct 14, 2024 at 4:08 PM Yangyu Chen wrote: > > From: Kito Cheng > > This provides a common abstraction layer to probe the available extensions at > run-time. These functions can be used to implement function multi-versio

Re: [PATCH] RISC-V: Add detailed comments on processing implied extensions.

Pushed to the trunk :) On Mon, Oct 14, 2024 at 6:31 PM Yangyu Chen wrote: > > In some cases, we don't need to handle implied extensions. Add detailed > comments to help developers understand what implied ISAs should be > considered. > > libgcc/ChangeLog: > > * config/riscv/feature_bits.c

Re: [PATCH v1 4/4] RISC-V: Add testcases for form 1 of scalar signed SAT_TRUNC

LGTM 於 2024年10月8日 週二 16:36 寫道： > From: Pan Li > > Form 1: > #define DEF_SAT_S_TRUNC_FMT_1(WT, NT, NT_MIN, NT_MAX) \ > NT __attribute__((noinline)) \ > sat_s_trunc_##WT##_to_##NT##_fmt_1 (WT x) \ > {

Re: [PATCH v6] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

; } __riscv_cpu_model; On Fri, Oct 4, 2024 at 2:24 AM Yangyu Chen wrote: > > From: Kito Cheng > > This provides a common abstraction layer to probe the available extensions at > run-time. These functions can be used to implement function multi-versioning > or > to detect availabl

Re: [PATCH] RISC-V: Add an implicit dependency for Zawrs

LGTM, and let me know if you need my help to commit that :) On Mon, Sep 30, 2024 at 9:37 AM Xiao Zeng wrote: > > There is a description in > : > > "The instructions in the Zawrs extension are only useful in conjunction > with th

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