From: Juzhe-Zhong
Hi, this patch support the new coming fixed-point intrinsics:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
Insert fixed-point rounding mode configuration by mode switching target hook.
Mode switching target hook is implemented applying LCM (Lazy code Motion
From: Juzhe-Zhong
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard.
So include Richard as co-author.
Co-Authored-By: Richard Sandiford
gcc/ChangeLog:
* config/riscv/autovec.md (vcond): New
From: Ju-Zhe Zhong
Address comments from Richard that splits the patch of fixing multiple-rgroup
handling of length counting elements.
This patch is fixing issue of handling multiple-rgroup of length is counting
elements
Before this patch, multiple rgroup run fail:
FAIL: gcc.target/riscv/rvv/a
From: Juzhe-Zhong
Since satisfies_constraint_vi (x) belongs to RVV region.
We make this condition inside riscv_v_ext_vector_mode_p to make codes
more reasonable.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Reorganize the codes.
---
gcc/config/riscv/riscv.cc | 12
From: Ju-Zhe Zhong
Address comments from Richard that splits the patch of fixing multiple-rgroup
handling of length counting elements.
This patch is fixing issue of handling multiple-rgroup of length is counting
elements
Before this patch, multiple rgroup run fail:
FAIL: gcc.target/riscv/rvv/a
From: Ju-Zhe Zhong
gcc/ChangeLog:
* tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New function.
(vect_set_loop_controls_directly): Add decrement IV support.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc: Ditto.
* tree-vec
From: Juzhe-Zhong
Just notice this following fail in the regression:
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c (test for excess
errors)
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c (test for
excess errors)
gcc/testsuite/ChangeLog
From: Juzhe-Zhong
Since the current framework is hard to maintain and
hard to be used in the future possible auto-vectorization patterns.
We will need to keep adding more helpers and arguments during the
auto-vectorization supporting. We should refactor the framework
now for the future use
From: Juzhe-Zhong
This patch is to refactor the framework of RVV auto-vectorization.
Since we find out are keep adding helpers && wrappers when implementing
auto-vectorization.
It will make the RVV auto-vectorizaiton very messy.
After double check my downstream RVV GCC, assemble
From: Juzhe-Zhong
This patch is to refactor the framework of RVV auto-vectorization.
Since we find out are keep adding helpers && wrappers when implementing
auto-vectorization.
It will make the RVV auto-vectorizaiton very messy.
After double check my downstream RVV GCC, assemble
From: Juzhe-Zhong
I just notice the warning:
../../../riscv-gcc/gcc/config/riscv/vector.md:618:1: warning: source missing a
mode?
gcc/ChangeLog:
* config/riscv/vector.md: Add mode.
---
gcc/config/riscv/vector.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc
From: Juzhe-Zhong
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard.
So include Richard as co-author.
Co-Authored-By: Richard Sandiford
gcc/ChangeLog:
* config/riscv/autovec.md (@vcond_mask_): New
From: Juzhe-Zhong
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard.
So include Richard as co-author.
Co-Authored-By: Richard Sandiford
gcc/ChangeLog:
* config/riscv/autovec.md (@vcond_mask_): New
From: Juzhe-Zhong
This simple patch fixes the magic number, replaced by enum to make code
more reasonable.
Ok for trunk ?
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vec_series): Fix magic number.
(expand_const_vector): Ditto.
(legitimize_move): Ditto
From: Juzhe-Zhong
This simple patch fixes the magic number, remove magic number make codes more
reasonable.
Ok for trunk ?
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vec_series): Remove magic number.
(expand_const_vector): Ditto.
(legitimize_move): Ditto
From: Juzhe-Zhong
For VLMAX situation, rtx len = ops[m_op_num] is incorrect since
the last element the ops array should be ops[m_op_num - 1];
I notice this issue when I am debugging code.
This is a code bug even though the following codes will hide this issue.
We still should need this minor
From: Juzhe-Zhong
To fix this issue, we seperate Vl operand and normal operands.
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust for new interface.
* config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand.
(emit_nonvlmax_insn): Add AVL operand.
* config
From: Juzhe-Zhong
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard.
So include Richard as co-author.
Co-Authored-By: Richard Sandiford
gcc/ChangeLog:
* config/riscv/autovec.md (@vcond_mask_): New
From: Juzhe-Zhong
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard.
So include Richard as co-author.
And this patch is the prerequisite patch for my current middle-end work.
Without this patch, I can&#
From: Juzhe-Zhong
This patch is adding mask logic auto-vectorization.
define the pattern as "define_insn_and_split" to allow
combine PASS easily combine series instructions.
For example:
combine vmxor.mm + vmnot.m into vmxnor.mm
Build success and regression PASS
Ok for trunk ?
gcc
From: Juzhe-Zhong
This patch is adding mask logic auto-vectorization.
define the pattern as "define_insn_and_split" to allow
combine PASS easily combine series instructions.
For example:
combine vmxor.mm + vmnot.m into vmxnor.mm
Build success and regression PASS
And committed.
From: Juzhe-Zhong
An obvious fix to make all enum naming consistent.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum frm_field_enum): Add FRM_ prefix.
---
gcc/config/riscv/riscv-protos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv
From: Juzhe-Zhong
According to RVV ISA:
The conversions use the dynamic rounding mode in frm, except for the rtz
variants, which round towards zero.
So rtz conversion patterns should not have FRM dependency.
We can't support mode switching for FRM yet since rvv intrinsic doc is not
up
From: Ju-Zhe Zhong
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rg
From: Ju-Zhe Zhong
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rg
From: Ju-Zhe Zhong
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rg
From: Juzhe-Zhong
Currenty mode switching incorrect codegen for the following case:
void fn (void);
void f (void * in, void *out, int32_t x, int n, int m)
{
for (int i = 0; i < n; i++) {
vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v,
From: Juzhe-Zhong
Currently mode switching incorrect codegen for the following case:
void fn (void);
void f (void * in, void *out, int32_t x, int n, int m)
{
for (int i = 0; i < n; i++) {
vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v,
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
(DEF_RVV_FRM_ENUM): New macro.
(handle_pragma_vector): Add FRM enum
* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
(RNE): Ditto
From: Ju-Zhe Zhong
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rg
From: Ju-Zhe Zhong
Fix format for Richard.
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step
From: Ju-Zhe Zhong
This patch is adding SELECT_VL middle-end support
allow target have target dependent optimization in case of
length calculation.
This patch is inspired by RVV ISA and LLVM:
https://reviews.llvm.org/D99750
The SELECT_VL is same behavior as LLVM "get_vector_length" with
these f
From: Juzhe-Zhong
Fix ICE of zero-scratch-regs-3.c:
bug.c:7:1: internal compiler error: Segmentation fault
7 | }
| ^
0x1647b23 crash_signal
../../../riscv-gcc/gcc/toplev.cc:314
0x147053f maybe_legitimize_operand
../../../riscv-gcc/gcc/optabs.cc:7947
0x1470dc2
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict VL
and drop VL in ops.
---
gcc/config/riscv/riscv.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index
From: Juzhe-Zhong
Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974
PR target/109974
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test
From: zhongjuzhe
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Change "static void" to "void".
* config.gcc: Add riscv-selftests.o
* config/riscv/predicates.md: Allow const_poly_int.
* config/riscv/riscv-protos.h (riscv_reinit): New function.
(risc
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Define RVV mask
modes.
(ADJUST_NUNITS): Adjust NUNITS using riscv_vector_chunks.
(ADJUST_ALIGNMENT): Adjust alignment.
(ADJUST_BYTESIZE): Adjust bytesize.
(RVV_MODES): New
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes.
(ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks.
(ADJUST_ALIGNMENT): Adjust alignment.
(ADJUST_BYTESIZE): Adjust bytesize using riscv_vector_chunks.
From: Ju-Zhe Zhong
This patch is a fix patch for:
https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601643.html
Suppress the warning as follows:
../../../riscv-gcc/gcc/poly-int.h: In function
‘poly_int64 eval_value(rtx, std::map&)’:
../../../riscv-gcc/gcc/poly-int.h:845:48: warning:
‘*((
From: Ju-Zhe Zhong
This patch fix issue: PR 99407
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99407
The enhancement implementation is simple:
1.Search gimple statement in program reverse order.
2.Queue the store statement which may be possible kill the def
of previous store statement.
3.Perfo
From: Ju-Zhe Zhong
This patch fix issue: PR 99407
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99407
The enhancement implementation is simple:
1.Search gimple statement in program reverse order.
2.Queue the store statement which may be possible kill the def
of previous store statement.
3.Perfo
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config.gcc: Add riscv-vector-builtins.o.
* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV builtin
function.
* config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p): New
function.
* config/riscv/riscv.c
From: Ju-Zhe Zhong
gcc/ChangeLog:
* tree-vect-loop.cc (vect_phi_first_order_recurrence_p): New function.
(vect_analyze_scalar_cycles_1): Classify first-order recurrence phi.
(vect_analyze_loop_operations): Add first-order recurrence
autovectorization support.
(ve
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config.gcc: Add riscv_vector.h.
* config/riscv/riscv-builtins.cc: Add RVV builtin types support.
* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): New function.
(riscv_register_pragmas): Ditto.
* config/riscv/riscv-pro
From: Ju-Zhe Zhong
Hi, After fixing previous ICE.
I add full implementation (insert permutation to get correct result.)
The gimple IR is correct now I think:
# t_21 = PHI <_4(6), t_12(9)>
# i_22 = PHI
# vectp_a.6_26 = PHI
# vect_vec_recur_.9_9 = PHI
# vectp_b.11_7 = PHI
# curr_c
From: Ju-Zhe Zhong
When implementing built-in framework, I notice I missed
vsetvl instruction type, so add it in a single patch
preparing for the following patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add vsetvl instruction type.
---
gcc/config/riscv/riscv.md | 3 ++-
1 file chang
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move
from riscv-vector-builtins.h.
* config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move
to riscv-vector-builtins.cc.
---
gcc/config/riscv/riscv-vector-builti
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move
from config/riscv/riscv-vector-builtins.h.
(DEF_RVV_TYPE): Change USER_NAME to NAME.
(register_vector_type): Change user_name to name.
* config/riscv/riscv-v
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher):
Move down like ARM SVE.
(rvv_switcher::~rvv_switcher): Move down like ARM SVE.
(mangle_builtin_type): Move down to make it together with other global
function.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (GTY): Redefine vector types.
(build_const_pointer): New function.
(register_builtin_type): Ditto.
(DEF_RVV_TYPE): Simplify macro.
(register_vector_type): Refine implementation.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (add_vector_type_attribute):
Clang-format function.
---
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.h: Remove redundant macro.
---
gcc/config/riscv/riscv-vector-builtins.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/riscv-vector-builtins.h
inde
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc: Change include files same as
ARM SVE.
* config/riscv/t-riscv: Refine makefile.
---
gcc/config/riscv/riscv-vector-builtins.cc | 9 +++--
gcc/config/riscv/t-riscv | 14 --
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.h (DEF_RVV_TYPE): Clang-format it.
---
gcc/config/riscv/riscv-vector-builtins.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/risc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-c.cc: Add new line.
* config/riscv/riscv_vector.h (vwrite_csr): Add new line.
---
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv_vector.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ju-Zhe Zhong
Hi, this patch fixed my mistake in the previous commit patch.
Since "mangle_builtin_type" is a global function will be called in riscv.cc.
It's reasonable move it down and put them together stay with other global
functions.
gcc/ChangeLog:
* config/riscv/riscv-vector-
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/t-riscv: Change Tab into 2 space.
---
gcc/config/riscv/t-riscv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 2f060437c23..15b9e7c01b1 100644
--- a/gcc/config
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config.gcc: Add gt files since function_instance is GTY ((user)).
* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV
intrinsic framework.
(riscv_builtin_decl): Ditto.
(riscv_expand_builtin): Ditto.
* config
--git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
new file mode 100644
index 000..dc41537865e
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -0,0 +1,43 @@
+/* Intrinsic define macros for RISC-V '
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Fix ALL_REGS.
---
gcc/config/riscv/riscv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index acae68ebb2d..37363e975e1 100644
--- a/gcc/
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF.
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv-vector-switch.def | 4
gcc/config/riscv/riscv.cc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv.cc | 14 ++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a390
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF
vector modes.
---
gcc/config/riscv/riscv-vector-switch.def | 4
1 file changed, 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-switch.def
b/gcc/config/riscv/riscv-ve
, HOST_WIDE_INT);
+extern bool legitimize_move (rtx, rtx, machine_mode);
+enum tail_policy
+{
+ TAIL_UNDISTURBED = 0,
+ TAIL_AGNOSTIC = 1,
+};
+
+enum mask_policy
+{
+ MASK_UNDISTURBED = 0,
+ MASK_AGNOSTIC = 1,
+};
}
/* We classify builtin types into two classes:
diff --git a/gcc/config/riscv
From: Ju-Zhe Zhong
Move away from the pre-C++11 compatibility macro CONSTEXPR.
This patch is inspired by aarch64:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603974.html.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Replace CONSTEXPR
with constexpr th
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
---
gcc/config/riscv/riscv.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo.
---
gcc/config/riscv/riscv-modes.def | 46
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/
From: Ju-Zhe Zhong
This patch fixed PR107357: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Set to minimum size.
(ADJUST_NUNITS): Adjust according to -march.
(ADJUST_BYTESIZE): Ditto.
* config
From: Ju-Zhe Zhong
I noticed that I have made a mistake in previous patch:
https://patchwork.sourceware.org/project/gcc/patch/20220817071950.271762-1-juzhe.zh...@rivai.ai/
The previous statement before this patch:
bool need_barrier_p = (get_frame_size () +
cfun->machine->frame.arg_pointer
From: Ju-Zhe Zhong
According to
https://github.com/gcc-mirror/gcc/commit/f95d3d5de72a1c43e8d529bad3ef59afc3214705.
Since GCC 4.8.6 doesn't support constexpr, we should change it back to
CONSTEXPR.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Change constexpr back to
C
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
* gcc.target/riscv/rvv/base/abi-3.c: Ditto.
* gcc.target/riscv/rvv/base/abi-4.c: Ditto.
* gcc.target/riscv/rvv/base/abi-5.c: Ditto.
* gcc.target/riscv/
From: zhongjuzhe
RISC-V 'V' Extension support scalable vector like ARM SVE.
To support RVV, we need to introduce runtime invariant.
- For zve32*, the runtime invariant uses 32-bit chunk.
- For zve64*, the runtime invariant uses 64-bit chunk.
[1]
https://github.com/riscv/riscv-v-spec/blob/maste
From: zhongjuzhe
Hello. This patch is preparing for following RVV support.
Both ARM SVE and RVV (RISC-V 'V' Extension) support length-agnostic vector.
The minimum vector length of ARM SVE is 128-bit and the runtime invariant of
ARM SVE is always 128-bit blocks.
However, the minimum vector lengt
From: zhongjuzhe
This patch fix issue of poly_uint16 (1, 1) in machine mode self test.
gcc/ChangeLog:
* simplify-rtx.cc (test_vector_subregs_fore_back): Make first value and
repeat value different.
---
gcc/simplify-rtx.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
From: zhongjuzhe
gcc/ChangeLog:
* tree-vect-loop-manip.cc (vect_gen_vector_loop_niters): Simply
initialize const_vf to 0.
---
gcc/tree-vect-loop-manip.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
From: zhongjuzhe
This patch is preparing patch for RVV support:
1. Add vector registers.
2. Add classification of RVV instructions in attribute 'type'.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
(riscv_classify_address): Disallow PLUS/LO_S
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.md: Add new type for vector instructions.
---
gcc/config/riscv/riscv.md | 100 +-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
(riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types
for RVV.
(riscv_address_insns): Add RVV modes condition.
(riscv_binary_cost): Ditto.
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Change
configuration according to TARGET_MIN_VLEN.
* config/riscv/riscv.h (UNITS_PER_FP_REG): Fix annotation.
---
gcc/config/riscv/riscv.cc | 11 ++-
gcc/config/riscv/riscv.h | 2 +-
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Change vype to vtype.
---
gcc/config/riscv/riscv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 29582f7c545..3ee5a93ce6a 100644
---
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
"vr" constraint.
(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
(vp): Add poly constraint.
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int.
(riscv_output_move): Add csrr vlenb assembly.
* config/riscv/riscv.md (move_type): Add csrr vlenb type.
(ext): New attribute.
(ext_enabled): Ditto.
(
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add RVV
registers.
---
gcc/config/riscv/riscv.cc | 9 +
1 file changed, 9 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 50de6a83cba..aebe3c0ab6
This patch fixes the following ineffective vsetvl insertion:
#include "riscv_vector.h"
void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond,
size_t cond2)
{
for (size_t i = 0; i < n; i++)
{
if (i == cond) {
vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
Update in v2: Add dump information.
This patch fixes the following ineffective vsetvl insertion:
#include "riscv_vector.h"
void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond,
size_t cond2)
{
for (size_t i = 0; i < n; i++)
{
if (i == cond) {
vint8mf8
I realize there is a RTL regression between GCC-14 and GCC-13.
https://godbolt.org/z/Ga7K6MqaT
GCC-14:
(insn 9 13 31 2 (set (reg:DI 15 a5 [138])
(unspec:DI [
(const_int 64 [0x40])
] UNSPEC_VLMAX)) "/app/example.c":5:15 2566 {vlmax_avldi}
(expr_list:REG_EQUI
Realize in recent benchmark evaluation (coremark-pro zip-test):
vid.v v2
vmv.v.i v5,0
.L9:
vle16.v v3,0(a4)
vrsub.vxv4,v2,a6 ---> LICM failed to hoist it outside the
loop.
The root cause is:
(insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0)
(re
This patch fixes the following:
vsetvli a5,a1,e32,m1,tu,ma
sllia4,a5,2
sub a1,a1,a5
vle32.v v2,0(a0)
add a0,a0,a4
vadd.vv v1,v2,v1
bne a1,zero,.L3
vsetivlizero,1,e32,m1,ta,ma
vmv.s.x v2,zero
vse
This patch fixes issue reported by Jeff.
Testing is running. Ok for trunk if I passed the testing with no regression ?
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite
compilation.
(pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
---
gcc/conf
While working on refining the cost model, I notice this test will generate
unexpected
scalar xor instructions if we don't tune cost model carefully.
Add more assembler to avoid future regression.
Committed.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: A
While working on cost model, I notice one case that dynamic lmul cost doesn't
work well.
Before this patch:
foo:
lui a4,%hi(.LANCHOR0)
li a0,1953
li a1,63
addia4,a4,%lo(.LANCHOR0)
li a3,64
vsetvli a2,zero,e32,mf2,ta,ma
v2 update: Robostify tests.
While working on cost model, I notice one case that dynamic lmul cost doesn't
work well.
Before this patch:
foo:
lui a4,%hi(.LANCHOR0)
li a0,1953
li a1,63
addia4,a4,%lo(.LANCHOR0)
li a3,64
vsetvli
This patch is inspired by LLVM patches:
https://github.com/llvm/llvm-project/pull/76550
https://github.com/llvm/llvm-project/pull/77473
Use vaaddu for AVG vectorization.
Before this patch:
vsetivlizero,8,e8,mf2,ta,ma
vle8.v v3,0(a1)
vle8.v v2,0(a2)
vwadd
This patch is preparing patch for the following cost model tweak.
Since we don't have vector cost model in default tune info (rocket),
we set the cost model default as generic cost model by default.
The reason we want to switch to generic vector cost model is the default
cost model generates infe
This patch is preparing patch for the following cost model tweak.
Since we don't have vector cost model in default tune info (rocket),
we set the cost model default as generic cost model by default.
The reason we want to switch to generic vector cost model is the default
cost model generates infe
This patch fixes the known issues on SLP cases:
ble a2,zero,.L11
addiw t1,a2,-1
li a5,15
bleut1,a5,.L9
srliw a7,t1,4
sllia7,a7,7
lui t3,%hi(.LANCHOR0)
lui a6,%hi(.LANCHOR0+128)
addit3,t3,%lo(.L
This patch fixes the following inefficient vectorized codes:
vsetvli a5,zero,e8,mf2,ta,ma
li a2,17
vid.v v1
li a4,-32768
vsetvli zero,zero,e16,m1,ta,ma
addiw a4,a4,104
vmv.v.i v3,15
lui a1,%hi(a)
li a0,1
1. This patch set scalar_to_vec cost as 2 instead 1 since scalar move
instruction is slightly more costly than normal rvv instructions (e.g.
vadd.vv).
2. Adjust scalar_to_vec cost accurately according to the splat value, for
example,
a value like 32872, needs 2 more scalar instructions:
This test should pass no matter how we adjust cost model.
Remove -fno-vect-cost-model.
Committed.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Remove
-fno-vect-cost-model
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c | 2 +-
1 file changed
1. Introduce vector regmove new tune info.
2. Adjust scalar_to_vec cost in add_stmt_cost.
We will get optimal codegen after this patch with -march=rv64gcv_zvl256b:
lui a5,%hi(a)
li a4,19
sb a4,%lo(a)(a5)
li a0,0
ret
Tested on both RV32/R
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