On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote:
> Ping ?
>
> I see that Jim has clarified the comments from Andrew.
Andrew also suggested that we add a testcase to the testsuite. I
didn't do that. I did put a testcase to reproduce in the bug report.
See
https://gcc.gnu.org
On 10/30/2017 12:13 PM, Jeff Law wrote:
On 10/13/2017 12:04 PM, David Edelsohn wrote:
This patch adds the basic LTO scanning pass to the COFF support in
collect2. I don't believe that this change should affect other COFF
targets adversely (do they even use collect2?), but I wanted to give
peopl
On 10/31/2017 12:11 PM, David Edelsohn wrote:
With your recent removal of SDB and -gcoff support, I would appreciate
your advice about my patch to incrementally add some preliminary LTO
support for AIX to collect2.c:
OK. I can take a look. I started a new job this week, so I'm a bit
disorgan
On 10/31/2017 12:11 PM, David Edelsohn wrote:
With your recent removal of SDB and -gcoff support, I would appreciate
your advice about my patch to incrementally add some preliminary LTO
support for AIX to collect2.c:
https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00893.html
There don't seem to b
The sdb/coff debug info format removal should be mentioned in the
release notes. Here is a patch to do that.
Verified as XHTML 1.0 transitional. My new employer disclaimer is on
file at the FSF as of today, and I have personal assignments, so I'm
good to contribute again.
OK?
Jim
Index: htdocs
A patch to add my new employer to the steering committee page.
Verified as XHTML 1.0 transitional and checked in.
Jim
Index: steering.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/steering.html,v
retrieving revision 1.41
diff -p -r1.41
On Mon, Nov 6, 2017 at 6:39 PM, Palmer Dabbelt wrote:
>
> +riscv port Jim Wilson
>
>
It is jimw not jim for the email address. Please fix.
Jim
Ping.
Jim
On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson wrote:
> Falkor is an ARMV8-A part, but also includes the RDMA extension from
> ARMV8.1-A.
> I'd like to enable support for the RDMA instructions when -mcpu=falkor is
> used,
> and also make the RDMA intrisics avail
queued. Since sched group insns always sort to the top
of the list of insns to schedule, all sched group insns still get
scheduled together as before.
This has been tested with an Aarch64 bootstrap and make check.
OK?
Jim
2017-07-13 Jim Wilson
PR rtl-optimization/81434
* haifa-sched.c
On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška wrote:
> May I ask Jim to test the patch?
> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.
I started an aarch64 bootstrap to test. My fast machine is busy with
work tasks, so I have to use a slower machine, and hence this
On Fri, Jul 14, 2017 at 12:59 PM, Jim Wilson wrote:
> On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška wrote:
>> May I ask Jim to test the patch?
>> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.
>
> I started an aarch64 bootstrap to test. My fast
On 07/14/2017 09:48 AM, Nathan Sidwell wrote:
This changes dbxout and dwarf2out.
Oh, the patch series survived a bootstrap on x86_64-linux.
Changes to the debug info files requires a gdb make check with and
without the patch to check for regressions. Since you are changing both
dbxout and
Ping^2
On Tue, Jul 11, 2017 at 1:49 PM, Jim Wilson wrote:
> Ping.
>
> Jim
>
> On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson wrote:
>> Falkor is an ARMV8-A part, but also includes the RDMA extension from
>> ARMV8.1-A.
>> I'd like to enable support for the
On Thu, Jul 20, 2017 at 2:00 PM, Nathan Sidwell wrote:
> With this patch the gdb stabs test results are still awful, but they are
> unchanged awfulness.
Yes, the stabs support for C++ is poor. That is one of the reasons
why almost everyone has switched to dwarf2.
I wasn't sure what to make of y
On Fri, Jul 21, 2017 at 7:15 AM, David Edelsohn wrote:
> AIX still uses DBX as the primary debugging format. AIX supports
> DWARF but the AIX toolchain does not fully interoperate with DWARF
> generated by GCC.
We could still deprecate DBX_DEBUG while leaving XCOFF_DEBUG alone for
now. This wou
On Fri, Jul 21, 2017 at 12:44 PM, Iain Sandoe wrote:
> It ought to be already, in fact anything (powerpc*/x86/x86-64) >= Darwin9 (OS
> X 10.5) ought to be defaulting to DWARF already, will check that sometime.
Yes, they do default to dwarf2. The comments say pre-darwin9 32-bit
defaults to stabs
Ping.
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00779.html
On Thu, Jul 13, 2017 at 3:00 PM, Jim Wilson wrote:
> The AArch64 port uses SCHED_GROUP to mark instructions that get fused
> at issue time, to ensure that they will be issued together. However,
> in the scheduler,
Trevor Saunders deleted the x86 openbsd 2 & 3 support here.
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01368.html
With that change, there are now 3 unused files that he missed. I noticed
the gstabs.h file while looking at debugging info related files, and then
did a consistency check and no
ed with a cross build, and checked
in under the obvious rule.
Jim
2017-07-25 Jim Wilson
gcc/
PR bootstrap/81521
* config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look
for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS.
Index: gcc/config/i
ed with a cross build, and checked
in under the obvious rule.
Jim
2017-07-25 Jim Wilson
gcc/
PR bootstrap/81521
* config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look
for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS.
Index: gcc/config/i
On 07/24/2017 01:04 PM, David Malcolm wrote:
* The LSP implementation is a just a proof-of-concept, to further
motivate capturing the extra data. Turning it into a "proper" LSP
server implementation would be a *lot* more work, and I'm unlikely to
actually do that (but maybe someone on t
On 07/22/2017 08:29 PM, David Edelsohn wrote:
This patch mirrors the earlier patch to copy debug_section_label into
dl_section_ref and append the adjustment when necessary. With this
patch, GDB is able to report correct macro information.
Bootstrapped on powerpc-ibm-aix7.2.0.0
Debug related p
This adds a pipeline description for the Qualcomm Falkor core. This was
tested with a bootstrap and make check. There were no regressions. This
gives about 0.5% performance gain on SPEC CPU2006 on our internal tree, which
has a few other patches that aren't in the FSF tree yet.
OK?
Jim
On Fri, 2017-08-11 at 12:34 +0200, Torsten Duwe wrote:
> gcc/testsuite/ChangeLog
> 2017-08-11 Torsten Duwe
>
> * c-c++-common/patchable_function_entry-default.c: Skip test on
> ia64.
> * c-c++-common/patchable_function_entry-decl.c: Likewise.
> * c-c++-common/patchable_functio
ping^2
On Fri, Jul 21, 2017 at 3:09 PM, Jim Wilson wrote:
> Ping.
>
> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00779.html
>
> On Thu, Jul 13, 2017 at 3:00 PM, Jim Wilson wrote:
>> The AArch64 port uses SCHED_GROUP to mark instructions that get fused
>> at issu
On 05/05/2017 12:23 AM, Richard Sandiford wrote:
2017-05-05 Richard Sandiford
gcc/
* lra-constraints.c (lra_copy_reg_equiv): New function.
(split_reg): Use it to copy equivalence information from the
original register to the spill register.
This patch breaks aarch64
On Sun, May 7, 2017 at 11:47 PM, Andrew Pinski wrote:
> On Sun, May 7, 2017 at 11:37 PM, Richard Sandiford
> wrote:
>> Really sorry for the breakage. I'd forgotten that this depended on:
>>
>> https://gcc.gnu.org/ml/gcc-patches/2017-03/msg01550.html
Thanks, this does fix my build failures. A
Early steppings had aarch32 support, current steppings don't, so the
aarch32 support for falkor/qdf24xx needs to be dropped. This mostly
involves removing falkor/qdf24xx references from the arm port. The
qdf24xx_extra_costs structure moves from the arm port to the aarch64
port.
This was tested w
On Thu, May 4, 2017 at 7:24 PM, Jeff Law wrote:
> On 03/01/2017 03:06 PM, Jim Wilson wrote:
> This seems fine to me. A testcase to add to the gcc.target testsuite would
> be useful, but I don't think it's strictly necessary.
Thanks for the review. It was 2 months sinc
On Fri, May 12, 2017 at 7:01 PM, Martin Sebor wrote:
> Explicitly passing the additional argument at all the call sites
> can be mitigated by giving the new alt_rtl argument a default
> value of NULL in the declarations of the extract_bit_field functions.
I keep forgetting about C++ features, as
On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
wrote:
> OK. does this need to go in the gcc-8 changes file?
Falkor hasn't shipped yet. I'm dropping features that only existed in
preproduction NDA hardware, so there isn't anything end user visible,
and hence I don't think that it need
On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists)
wrote:
> On 24/05/17 15:18, Jim Wilson wrote:
>> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
>> wrote:
>>> OK. does this need to go in the gcc-8 changes file?
>>
>> Falkor hasn't
On Wed, Apr 5, 2017 at 5:38 AM, Wilco Dijkstra wrote:
> Many supported cores use the AUTOPREFETCHER_WEAK setting which tries
> to order loads and stores to improve streaming performance. Since significant
> gains were reported in http://patchwork.ozlabs.org/patch/534469/ it seems
> like a good id
On Mon, 2017-09-18 at 22:03 +, Joseph Myers wrote:
> Thus, I'd like the architecture maintainers to advise on whether any
> such issues apply for their architecture. If they do, that will
> provide the information needed for a comment on XFAILing the test in
> glibc. If no such reasons apply
On Falkor, because of an idiosyncracy of how the pipelines are designed, a
quad-word store using a reg+reg addressing mode is almost twice as slow as an
add followed by a quad-word store with a single reg addressing mode. So we
get better performance if we disallow addressing modes using register
On Fri, Sep 22, 2017 at 8:49 AM, Jim Wilson wrote:
> On Falkor, because of an idiosyncracy of how the pipelines are designed, a
> quad-word store using a reg+reg addressing mode is almost twice as slow as an
> add followed by a quad-word store with a single reg addressing mode. So
On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski wrote:
> Two overall comments:
> * What about splitting register_offset into two different elements,
> one for non 128bit modes and one for 128bit (and more; OI, etc.) modes
> so you get better address generation right away for the simd load
> cases
.html,v
retrieving revision 1.40
diff -u -r1.40 steering.html
--- steering.html 17 Mar 2015 21:12:09 - 1.40
+++ steering.html 3 Oct 2017 21:37:21 -
@@ -38,7 +38,7 @@
Ramana Radhakrishnan (ARM)
Joel Sherrill (OAR Corporation)
Ian Lance Taylor (Google)
-Jim Wilson (Linaro)
+Jim Wilson
and
On Sun, 2017-09-10 at 19:45 +0200, Jim Wilson wrote:
> -- Forwarded message --
> From: Jim Wilson
> Date: Tue, Sep 5, 2017 at 8:04 PM
> Subject: Re: [PATCH] scheduler bug fix for AArch64 insn fusing
> SCHED_GROUP usage
> To: "gcc-patches@gcc.gnu
This is a proposed patch for the bug 79794 which I just submitted.
This isn't a regression, so this can wait for after the gcc 7 branch
if necessary.
The problem here is that a reg+offset MEM target is passed to
extract_bit_field with a vector register source. On aarch64, we have
an instruction f
On Tue, Mar 14, 2017 at 2:37 AM, James Greenhalgh
wrote:
> I'd like to hear comments from the Exynos-M1, Falkor and
> xgene-1 subtarget contributors, particularly as these targets use
> generic_branch_costs for their subtarget-sepcific tuning. It may be that
> your patch needs to preserve the 2,2
On Thu, Mar 16, 2017 at 11:01 AM, Andrew Pinski wrote:
> On Thu, Mar 16, 2017 at 10:22 AM, Wilco Dijkstra
> wrote:
>> Many supported cores implement fusion of AES instructions. When fusion
>> happens it can give a significant performance gain. If not, scheduling
>> fusion candidates next to ea
eg are now disabled in some cases. I haven't had a chance to look at
this in detail yet.
The patch was preapproved by Jeff and has been checked in.
Jim
2017-03-17 Jim Wilson
* combine.c (try_combine): Delete redundant i1 test. Call
prev_nonnote_nondebug_insn instead of prev_nonnote_in
===
--- ChangeLog (revision 234867)
+++ ChangeLog (working copy)
@@ -1,3 +1,12 @@
+2016-04-11 Jim Wilson
+
+ Partial backport from trunk r228017.
+ 2015-09-22 Jason Merrill
+
+ PR c++/70613
+ * doc/invoke.texi (-fabi-version): Document version 9.
+ (-Wabi): Document
On 04/11/2016 01:41 PM, Jim Wilson wrote:
Here is a patch to correct the -fabi-version docs on the GCC 5 branch.
Ping
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html
Jim
On 04/18/2016 01:12 PM, Jim Wilson wrote:
On 04/11/2016 01:41 PM, Jim Wilson wrote:
Here is a patch to correct the -fabi-version docs on the GCC 5 branch.
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html
ping^2
Jim
On Thu, Apr 21, 2016 at 1:15 AM, Kyrill Tkachov
wrote:
> Jim, you added support for the qdf24xx identifier to -mcpu and -mtune.
> Could you please suggest an appropriate entry to describe it?
> I think the same format as the Cortex-A35 entry in this patch would be
> appropriate.
This is tricky, a
On 10/12/2016 08:55 AM, Joseph Myers wrote:
On Wed, 12 Oct 2016, Martin Liška wrote:
Last question is whether one can aggressively fold strcasecmp in a host
compiler? Or are there any situations where results depends on locale?
There are the usual issues with Turkish locales having the upperc
On Wed, Apr 27, 2016 at 3:33 AM, Kyrill Tkachov
wrote:
> Thanks, I've incorporated your and James' feedback.
> Since James ok'd the content of the patch from an AArch64 perspective
> I'll commit this later today if I receive no further feedback.
There is no paragraph for the Qualcomm qdf24xx. Do
On Mon, Apr 25, 2016 at 11:47 AM, Bernd Schmidt wrote:
Here is a patch to correct the -fabi-version docs on the GCC 5 branch.
>>> https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html
ping^3
I put an explanation of the patch history for gcc-5 in the PR
https://gcc.gnu.org/bugzilla/sh
For this simple testcase
double
sub (void)
{
return 0.0;
}
Without the attached patch, an ARM compiler with neon support enabled, gives
vldr.64 d0, .L2
With the attached patch, an ARM compiler with neon enabled, gives
vmov.i64 d0, #0@ float
which is faster and smaller, as there is no
On Fri, May 6, 2016 at 7:29 AM, Kyrill Tkachov
wrote:
> Since you're modifying the both the ARM and Thumb2 pattern
> can you please do two bootstrap and tests, one with --with-mode=arm
> and one with --with-mode=thumb.
> Ok after adding the assert mentioned above, the arm/thumb testing and fixing
On Mon, May 2, 2016 at 12:13 PM, Jim Wilson wrote:
> Here is a patch to correct the -fabi-version docs on the GCC 5 branch.
> https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html
Maybe I didn't put enough info in the email the first 3 times?
You can see the default -fabi-versi
This is my fifth ping. I just need someone to rubber stamp it so I
can check it in.
Maybe it would be easier if I volunteered to be a doc maintainer so I
can self approve it?
Jim
On Mon, May 9, 2016 at 4:21 PM, Jim Wilson wrote:
> On Mon, May 2, 2016 at 12:13 PM, Jim Wilson wrote:
>>
Deletes text claiming that major version changes are rare, and fixes
two misspellings of signaling.
Tested with make info and make dvi.
Jim
2016-05-16 Jim Wilson
* doc/cpp.texi (__GNUC__): Major version changes are no longer rare.
* doc/invoke.texi (-mnan=2008): Change signalling to
On Mon, May 16, 2016 at 4:30 AM, James Greenhalgh
wrote:
> As this change will change code generation for all cores (except
> Exynos-M1), I'd like to hear from those with more detailed knowledge of
> ThunderX, X-Gene and qdf24xx before I take this patch.
It looks like a slight lose on qdf24xx on
On 09/08/2015 08:39 AM, Jeff Law wrote:
> Is this another instance of the PROMOTE_MODE issue that was raised by
> Jim Wilson a couple months ago?
It looks like a closely related problem. The one I am looking at has
confusion with a function arg and a local variable as they have
differen
loop distributions. There is
no measurable performance gain from the bug fix on the CPU2006 run
time though I plan to spend some more time looking at this code to see
if I can find other improvements.
OK?
Jim
2016-11-09 Jim Wilson
* tree-loop-distribution.c (pg_add_dependence_edges): Return
On Thu, Nov 10, 2016 at 2:53 AM, Richard Biener
wrote:
> The biggest "lack" of loop distribution is the ability to undo CSE so for
I hadn't noticed this problem yet. I will have to take a look.
> Then of course the cost model is purely modeled for STREAM (reduce the number
> of memory streams).
Here is a smaller simpler testcase. Only the first four args get
passed in regs, so the fifth one has address equal to the virtual
incoming args reg which triggers the failure.
typedef __simd128_float32_t float32x4_t;
float32x4_t
sub (float32x4_t a, float32x4_t b, float32x4_t c, float32x4_t d, fl
On Mon, Jan 11, 2016 at 10:22 PM, kugan
wrote:
> When promote_function_mode and promote_ssa_mode changes the sign
> differently, following is the cause for the problem in PR67714.
> This is similar to PR65932 where sign change in PROMOTE_MODE causes problem
> for parameter. But need a different
On Tue, Jan 12, 2016 at 5:10 PM, Kugan
wrote:
> Yes, making PROMOTE_MODE to work the same way as in
> promote_function_mode in arm will fix this. Can you please point me to
> the test cases that are regressing so that I can also start looking at them.
The info is in here
https://gcc.gnu.org/b
On Tue, Jan 12, 2016 at 5:40 PM, Jim Wilson wrote:
> The info is in here
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65932
> See the comments on gcc.target/arm/wmul-[123].c which no longer
> generate smulbb etc instructions, which are 16x16=32 expanding
> multiplies whic
On Tue, 2011-05-03 at 16:24 -0400, Jason Merrill wrote:
> That makes sense to me; it seems appropriate for -g1 to have information
> that makes a backtrace more informative, but not information for
> interactive debugging. Jim, do you have an opinion?
I'm not aware of any significant use of -g1
On Tue, Feb 8, 2022 at 4:35 AM Maciej W. Rozycki wrote:
> gcc/
> * config/riscv/riscv.md (UNSPEC_FMIN, UNSPEC_FMAX): New
> constants.
> (fmin3, fmax3): New insns.
> ...
I tried testing on some of the hardware I have. Both the HiFive Unleashed
(2018) and HiFive U
On Mon, Nov 29, 2021 at 5:21 PM Martin Sebor via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> There are some other "unusual" cases worth a look, such as missing
> context of any kind except for like and column:
>
> elfnn-riscv.c:3346:7: warning: statement after return is not reachable
> [-Wunre
Palmer Dabbelt
riscv port Andrew Waterman
-riscv port Jim Wilson
+riscv port Jim Wilson
rs6000/powerpc portDavid Edelsohn
rs6000/powerpc portSegher Boessenkool
rs6000 vector extns
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