promoted. This chooses
an INSN which has a high priority instruction dependent on it. This
triggers the scheduling of that consumer instruction as early as
possible to free up the registers used by that instruction.
Change log:
2014-05-21 Jaydeep Patil
Prachi Godbole
2014 PM 08:23
To: Jaydeep Patil
Cc: Rich Fuhler; Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH][MIPS] P5600 scheduling
Hi Jaydeep,
Thanks for the write-up and updated patches. I'll try to get to them this
weekend. In the meantime...
Jaydeep Patil writes:
> The -msche
. Registers of
size 16bytes and above are considered as vector registers.
Regards,
Jaydeep
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: 25 May 2014 PM 04:18
To: Jaydeep Patil
Cc: Rich Fuhler; Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH
