On Mon, Nov 23, 2015 at 10:33:01AM +, Kyrill Tkachov wrote:
>
> On 12/11/15 12:05, James Greenhalgh wrote:
> >On Tue, Nov 03, 2015 at 03:43:24PM +, Kyrill Tkachov wrote:
> >>Hi all,
> >>
> >>Bootstrapped and tested on aarch64.
> >>
> >
On Tue, Nov 24, 2015 at 02:24:30AM -0700, Michael Collison wrote:
> This is a followup patch which addresses formatting comments posted here:
>
> https://gcc.gnu.org/ml/gcc-patches/2015-11/msg02611.html
>
> 2015-11-24 Michael Collison
> * config/aarch64/aarch64-simd.md (widen_ssum, widen_us
On Tue, Nov 24, 2015 at 10:21:51AM +, Bilyan Borisov wrote:
> I've made the change you've requested. Changelog & patch description
> are below.
>
> Thanks,
> Bilyan
>
> ---
>
> This patch from the series adds tests that check for the proper error
> reporting
> of out of bounds accesses to a
On Fri, Sep 25, 2015 at 12:44:40PM +0100, Wilco Dijkstra wrote:
> This patch improves add immediate expansion by always expanding complex adds
> into a move immediate
> and an add. This enables CSE of all complex immediates. A separate split
> pattern enables combine to
> emit a 2-instruction add
On Tue, Nov 17, 2015 at 06:35:36PM +, Wilco Dijkstra wrote:
> Bernd Schmidt wrote:
> > Sent: 17 November 2015 22:16
> > To: Wilco Dijkstra; gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH 1/4][AArch64] Generalize CCMP support
> >
> > On 11/13/2015 05:02 PM, Wilco Dijkstra wrote:
> > > * gcc/
On Mon, Nov 16, 2015 at 04:31:32PM +, Matthew Wahab wrote:
> Hello,
>
> The command line options for target selection allow ARMv8.1 extensions
> to be individually enabled/disabled. They also allow the extensions to
> be enabled with -march=armv8-a. This doesn't reflect the ARMv8.1
> architect
On Tue, Nov 24, 2015 at 07:10:01AM +0100, Jan Hubicka wrote:
> > On November 23, 2015 5:50:25 PM GMT+01:00, Jan Hubicka
> > wrote:
> > >>
> > >> I think it also causes the following and one related ICE
> > >>
> > >> FAIL: gcc.dg/vect/pr62021.c -flto -ffat-lto-objects (internal
> > >compiler
>
On Tue, Nov 17, 2015 at 02:10:35PM -0800, Andrew Pinski wrote:
>
> Because the imp and parts are really integer rather than strings, this patch
> moves the comparisons to be integer. Also allows saving around integers are
> easier than doing string comparisons. This allows for the next change.
>
On Wed, Nov 25, 2015 at 10:10:49AM +, Matthew Wahab wrote:
> On 23/11/15 16:38, Matthew Wahab wrote:
> >On 23/11/15 12:24, James Greenhalgh wrote:
> >>On Tue, Oct 27, 2015 at 03:32:04PM +, Matthew Wahab wrote:
> >>>On 24/10/15 08:16, Bernhard Reutner-Fisc
On Wed, Nov 25, 2015 at 10:14:10AM +, Matthew Wahab wrote:
> On 23/11/15 13:35, James Greenhalgh wrote:
> >On Fri, Oct 23, 2015 at 01:26:11PM +0100, Matthew Wahab wrote:
> >>The ARMv8.1 architecture extension adds two Adv.SIMD instructions,
> >>sqrdmlah and sqrdmls
On Wed, Nov 25, 2015 at 10:15:45AM +, Matthew Wahab wrote:
> On 23/11/15 13:37, James Greenhalgh wrote:
> >On Fri, Oct 23, 2015 at 01:30:46PM +0100, Matthew Wahab wrote:
> >>The ARMv8.1 architecture extension adds two Adv.SIMD instructions,
> >>sqrdmlah and sqrdmls
On Tue, Oct 27, 2015 at 01:21:51PM -0700, Richard Henderson wrote:
> The problem in this PR is that a word-mode subreg is used to write to a
> multi-word pseudo, under the assumption that is the correct way to insert a
> value into the appropriate bits of the pseudo.
>
> Except that the pseudo the
On Thu, Nov 26, 2015 at 09:41:15AM +, Charles Baylis wrote:
> Hi James,
>
> Ping. This needs an ack from an AArch64 reviewer/maintainer
Fine by me, it will considerably clean up my test results for ARM!
Thanks,
James
On Thu, Nov 05, 2015 at 12:30:08PM -0700, Martin Sebor wrote:
> On 11/02/2015 09:55 PM, Jason Merrill wrote:
> >On 10/26/2015 10:06 PM, Martin Sebor wrote:
> >>+ if (TREE_CONSTANT (maybe_constant_value (outer_nelts)))
> >>+{
> >>+ if (tree_int_cst_lt (max_outer_nelts_tree, outer_nelts
On Thu, Nov 26, 2015 at 04:20:35PM -, David Sherwood wrote:
> Hi,
>
> Here is the second patch of the fmin/fmax change, which adds the optabs
> to the aarch64 backend.
>
> Tested:
>
> x86_64-linux: no regressions
> aarch64-none-elf: no regressions
>
> Good to go?
> David Sherwood.
Could yo
ut looks OK so far) if the release
managers and AArch64 maintainers agree this is something that should be
backported this late in the 5.3 release cycle.
Thanks,
James
---
2015-11-27 James Greenhalgh
* config/aarch64/aarch64-protos.h
(aarch64_cannot_change_mode_class): Br
On Tue, Dec 01, 2015 at 04:34:01PM +, David Sherwood wrote:
> Hi,
>
> Thanks for the comments James, I've moved the patterns around
> and added new comments to them. Hope this is ok.
This is fine.
Thanks,
James
}
(nil))
The patch simply constrains the pattern to use w/x registers.
Bootstrapped on aarch64-none-linux-gnu and cross-tested on aarch64-none-elf
with no issues.
OK?
Thanks,
James
---
gcc/
2015-12-04 James Greenhalgh
* config/aarch64/aarch64.md (add3_pluslong): Add register
On Mon, Dec 07, 2015 at 11:09:52AM +, Matthew Wahab wrote:
> Ping. Updated patch attached.
This is OK, thanks.
James
>
> Matthew
>
> On 27/11/15 09:23, Matthew Wahab wrote:
> >On 24/11/15 15:22, James Greenhalgh wrote:
> > > On Mon, Nov 16, 2015 at 04:31:3
On Fri, Nov 27, 2015 at 01:01:01PM +, James Greenhalgh wrote:
> This patch follow Richard Henderson's advice to tighten up
> CANNOT_CHANGE_MODE_CLASS for AArch64 to avoid a simplification bug in
> the middle-end.
>
> There is nothing AArch64-specific about the testcase
Hi,
As subject, this patch rewrites the mla intrinsics to use a + b * c rather
than inline assembler, thereby opening them to CSE, scheduling, etc.
Bootstrapped and tested on aarch64-none-linux-gnu.
OK?
Thanks,
James
---
gcc/Changelog:
2020-08-11 James Greenhalgh
config/aarch64
Hi,
As title, move some arm_neon.h functions which currently use assembly over
to intrinsics.
Bootstrapped and tested on aarch64-none-linux-gnu.
OK, if so can someone please apply on my behalf?
Thanks,
James
---
gcc/
2020-02-18 James Greenhalgh
* config/aarch64/aarch64-simd
On Wed, Aug 07, 2019 at 08:28:50PM +0100, Richard Sandiford wrote:
> It was easier to add the SVE ACLE support without enumerating every
> function at build time. This in turn meant that it was easier if the
> SVE builtins occupied a distinct numberspace from the existing AArch64
> ones, which *ar
On Tue, Sep 24, 2019 at 02:40:20PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> On 8/22/19 10:16 AM, Kyrill Tkachov wrote:
> > Hi all,
> >
> > The optimisation to optimise:
> > typedef unsigned long long u64;
> >
> > void bar(u64 *x)
> > {
> > *x = 0xabcdef10abcdef10;
> > }
> >
> >
On Mon, Sep 23, 2019 at 10:45:29AM +0100, Richard Sandiford wrote:
> The PLUS handling in aarch64_rtx_costs only checked for nonnegative
> constants, meaning that simple immediate subtractions like:
>
> (set (reg R1) (plus (reg R2) (const_int -8)))
>
> had a cost of two instructions.
>
> Teste
On Wed, Aug 01, 2018 at 07:13:53AM -0500, Vlad Lazar wrote:
> On 31/07/18 22:48, James Greenhalgh wrote:
> > On Fri, Jul 20, 2018 at 04:37:34AM -0500, Vlad Lazar wrote:
> >> Hi,
> >>
> >> The patch adds implementations for the NEON intrinsics vabsd_
On Thu, Aug 02, 2018 at 11:58:37AM -0500, Siddhesh Poyarekar wrote:
> There was a typo in the pipeline description where DUP was assigned to
> the vector pipes for quad mode ops when it really only uses the VTOG
> pipes. Fixing this does not show any noticeable difference in
> performance (there's
On Tue, Jul 31, 2018 at 04:53:19AM -0500, Matthew Malcomson wrote:
> Fixing the ilp32 issue that Christophe found.
>
> The existing testcase uses `long` to represent a 64 bit integer.
> This breaks when compiled using the `-mabi=ilp32` flag.
> We switch the use of int/long for int32_t/int64_t to a
On Fri, Aug 03, 2018 at 10:34:37AM -0500, Richard Sandiford wrote:
> The "@" handling broke -mlow-precision-div, because the scalar forms of
> the instruction were provided by a pattern that also provided FRECPX
> (and so were parameterised on an unspec code as well as a mode),
> while the SIMD ver
On Tue, Aug 07, 2018 at 05:09:34AM -0500, Tamar Christina wrote:
> Hi All,
>
> This is a re-spin to address review comments. No code change aside from a
> variable rename.
>
> Ok for trunk?
OK.
Thanks,
James
> gcc/
> 2018-08-07 Tamar Christina
>
> PR target/86486
> * config/aa
On Tue, Aug 07, 2018 at 05:09:30AM -0500, Tamar Christina wrote:
> Hi All,
>
> This is an updated patch which applies the same style changes as requested in
> patch 5/6.
No full stop on an error message IIRC.
Otherwise, OK.
Thanks,
James
> gcc/
> 2018-08-07 Tamar Christina
>
> * co
On Thu, Aug 02, 2018 at 09:02:05PM -0500, Siddhesh Poyarekar wrote:
> On 08/03/2018 12:02 AM, James Greenhalgh wrote:
> > On Thu, Aug 02, 2018 at 11:58:37AM -0500, Siddhesh Poyarekar wrote:
> >> There was a typo in the pipeline description where DUP was assigned to
> >>
On Tue, Aug 07, 2018 at 03:01:28AM -0500, Siddhesh Poyarekar wrote:
> Hello,
>
> Ping!
To help set expectations here. I'm currently only able to dedicate a couple
of hours of time to review each week. Tamar's Stack Clash has been taking
a big chunk of that time recently as we push it to a final s
On Wed, Aug 08, 2018 at 05:38:09AM -0500, Hongbo Zhang wrote:
> HXT semiconductor's CPU core Phecda, as a variant of Qualcomm qdf24xx,
> reuses the same tuning structure and pipeline with it.
Thank you. This patch is still OK.
I've applied it on your behalf as r263404.
Thanks,
James
>
> 2018-0
On Wed, Aug 08, 2018 at 07:17:07PM -0500, Martin Sebor wrote:
> On 08/08/2018 05:08 AM, Jason Merrill wrote:
> > On Wed, Aug 8, 2018 at 9:04 AM, Martin Sebor wrote:
> >> On 08/07/2018 02:57 AM, Jason Merrill wrote:
> >>>
> >>> On Wed, Aug 1, 2018 at 12:49 AM, Martin Sebor wrote:
>
> On
On Tue, Aug 14, 2018 at 09:34:08PM -0500, Martin Sebor wrote:
> On 08/14/2018 09:24 AM, Martin Sebor wrote:
> > On 08/14/2018 09:08 AM, Martin Sebor wrote:
> >> On 08/14/2018 07:27 AM, James Greenhalgh wrote:
> >>> On Wed, Aug 08, 2018 at 07:17:07PM -0500, Martin Seb
On Tue, Aug 28, 2018 at 03:59:25AM -0500, Vlad Lazar wrote:
> Gentle ping.
>
> On 08/08/18 17:38, Vlad Lazar wrote:
> > On 01/08/18 18:35, James Greenhalgh wrote:
> >> On Wed, Aug 01, 2018 at 07:13:53AM -0500, Vlad Lazar wrote:
> >>> On 31/07/18 22:48, James
On Mon, Aug 27, 2018 at 10:05:21AM -0500, Luis Machado wrote:
> Hi,
>
> On 08/08/2018 04:46 AM, Siddhesh Poyarekar wrote:
> > On 08/01/2018 04:24 AM, James Greenhalgh wrote:
> >> OK if this is what is best for your subtarget.
> >>
> >
> > I have
On Mon, Aug 27, 2018 at 10:05:17AM -0500, Luis Machado wrote:
> Hi,
>
> On 08/08/2018 04:54 AM, Siddhesh Poyarekar wrote:
> > On 08/01/2018 04:23 AM, James Greenhalgh wrote:
> >> On Wed, Jul 25, 2018 at 01:10:34PM -0500, Luis Machado wrote:
> >>> The adjusted v
On Fri, Aug 03, 2018 at 11:28:08AM -0500, Matthew Malcomson wrote:
> On 02/08/18 20:18, James Greenhalgh wrote:
> > On Tue, Jul 31, 2018 at 04:53:19AM -0500, Matthew Malcomson wrote:
> >> Fixing the ilp32 issue that Christophe found.
> >>
> >> The existing te
On Wed, Aug 01, 2018 at 10:07:23AM -0500, Sam Tebbs wrote:
> Hi all,
>
> This patch adds an optimisation that exploits the AArch64 BFXIL
> instruction when or-ing the result of two bitwise and operations
> with non-overlapping bitmasks
> (e.g. (a & 0x) | (b & 0x)).
>
> Example:
>
On Tue, Jul 31, 2018 at 04:38:43AM -0500, Sam Tebbs wrote:
> Hi all,
>
> This patch captures the case where an unnecessary uxtw instruction is
> generated
> after a bfxil instruction when in SI mode, and stops it from being
> generated.
> Note that this depends on my previous patch submission
>
On Mon, Aug 20, 2018 at 05:39:52AM -0500, Siddhesh Poyarekar wrote:
> Ping!
>
> On 07/24/2018 12:37 PM, Siddhesh Poyarekar wrote:
> > Hi,
> >
> > This is a rewrite of the tag collision avoidance patch that Kugan had
> > written as a machine reorg pass back in February.
> >
> > The falkor hardwar
On Wed, Aug 15, 2018 at 07:55:18AM -0500, Tamar Christina wrote:
> Hi All,
>
> I'm updating the patch with the suggested changes and also fixing a bug with
> a boundary condition.
>
> On AArch64 we have integer modes larger than TImode, and while we can generate
> moves for these they're not as
On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote:
> On 02/06/17 19:19 +0200, Ulrich Drepper wrote:
> >On Fri, Jun 2, 2017 at 5:46 PM, Michael Collison
> > wrote:
> >>This implementation includes "arm_neon.h" when including the optimized
> >>. This has the effect of polluting the gl
On Tue, Jun 06, 2017 at 11:47:45AM +0100, Jonathan Wakely wrote:
> On 06/06/17 11:23 +0100, Jonathan Wakely wrote:
> >On 06/06/17 11:07 +0100, James Greenhalgh wrote:
> >>On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote:
> >>>On 02/06/17 19:19 +0200,
On Tue, May 02, 2017 at 04:37:21PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch adjusts the cost model for Cortex-A53 to increase the costs of
> an integer division. The reason for this is that we want to always expand
> the division to a multiply when doing a division by constant.
>
>
On Tue, May 02, 2017 at 04:37:16PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch adjusts the cost model so that when both sdiv and udiv are possible
> it prefers udiv over sdiv. This was done by making sdiv slightly more
> expensive
> instead of making udiv cheaper to keep the baseline
On Tue, Feb 28, 2017 at 12:29:50PM +, Kyrill Tkachov wrote:
> Hi all,
>
> For the testcase in this patch we currently generate:
> foo:
> mov w1, 0
> ldaxr w2, [x0]
> cmp w2, 3
> bne .L2
> stxrw3, w1, [x0]
> cmp w3, 0
> .L2:
On Tue, Jun 06, 2017 at 09:40:44AM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> On top of the previous vec_merge simplifications [1] we can add this pattern
> to perform
> a store of a vec_concat of two 64-bit values in distinct registers as an STP.
> This avoids constructing such a vector explicit
On Fri, Mar 10, 2017 at 06:37:30AM +, Hurugalawadi, Naveen wrote:
> Hi James,
>
> >> You need to do this for all cores which might be affected by this change,
> >> i.e. all those which model neon_mul_d_long.
>
> Thanks for pointing out the missing cores in patch.
> Added the support as per yo
On Wed, Mar 15, 2017 at 04:04:35PM +, Tamar Christina wrote:
> Hi All,
>
> This fixes a bug in the scalar version of copysign where due to a subreg
> were generating less than efficient code.
>
> This patch replaces
>
> return x * __builtin_copysignf (150.0f, y);
>
> which used to genera
On Fri, Dec 30, 2016 at 10:05:26PM -0800, Andrew Pinski wrote:
> Hi,
> Currently for the following function:
> int f(int a, int b)
> {
> return a + (b <<7);
> }
>
> GCC produces:
> add w0, w0, w1, lsl 7
> But for ThunderX 1, it is better if the instruction was split allowing
> better sched
On Mon, Jan 30, 2017 at 08:35:00AM -0800, Andrew Pinski wrote:
> On Mon, Jan 30, 2017 at 3:48 AM, Maxim Kuvyrkov
> wrote:
> > This patch port prefetch configuration from aarch32 backend to aarch64.
> > There is no code-generation change from this patch.
> >
> > This patch also happens to address
On Fri, Feb 03, 2017 at 02:58:23PM +0300, Maxim Kuvyrkov wrote:
> > On Jan 30, 2017, at 5:50 PM, Maxim Kuvyrkov
> > wrote:
> >
> >> On Jan 30, 2017, at 3:23 PM, Kyrill Tkachov
> >> wrote:
> >>
> >> Hi Maxim,
> >>
> >> On 30/01/17 12:06, Maxim Kuvyrkov wrote:
> >>> This patch enables prefetch
On Mon, Jan 30, 2017 at 03:08:04PM +0300, Maxim Kuvyrkov wrote:
> This patch enables software prefetching at -O3 for Qualcomm's qdf24xx cores.
>
> Bootstrapped and regtested on x86_64-linux-gnu and aarch64-linux-gnu.
This patch is OK in whatever form it takes after rebasing for the macro
in 4/6.
On Tue, May 02, 2017 at 10:52:13AM +0100, Ramana Radhakrishnan wrote:
> We unnecessarily align data to 8 byte alignments even when -Os is
> specified. This brings the logic in the AArch64 backend more in line
> with the ARM backend and helps gain some image size in a few places.
> Caught by an inte
On Wed, Jun 07, 2017 at 12:38:27PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch allows the inlining of lrint when -fno-math-errno
> assuming that errno does not need to be set when the rounded value
> is not representable as a long.
>
> The case
>
> void f(double *a, long *b, double x)
On Wed, Jun 07, 2017 at 12:38:22PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch optimizes integer moves for cases where where the move could be
> done
> move efficiently using a smaller mode.
>
> For example:
>
> long long f1(void)
> {
> return 0x;
> }
>
> long f2(void)
>
On Fri, Jun 09, 2017 at 10:30:02AM +0300, Maxim Kuvyrkov wrote:
> > On Jun 8, 2017, at 6:13 PM, Richard Earnshaw (lists)
> > wrote:
> >
> > On 08/06/17 14:47, James Greenhalgh wrote:
> >> On Mon, Jan 30, 2017 at 08:35:00AM -0800, Andrew Pinski wrote:
> >&g
On Wed, Apr 26, 2017 at 06:34:36AM +, Hurugalawadi, Naveen wrote:
> Hi Kyrill,
>
> Thanks for the review and your comments.
>
> >> It would be useful if you expanded a bit on the approach used to
> >> generate the improved codegen
>
> The patch creates a duplicate of most common element and
On Fri, Jun 09, 2017 at 01:03:34PM -0700, Jim Wilson wrote:
> # Arch Matches
> Index: gcc/doc/invoke.texi
> ===
> --- gcc/doc/invoke.texi (revision 249025)
> +++ gcc/doc/invoke.texi (working copy)
> @@ -13983,8 +13983,8 @@
ead be transformed to:
f2:
lsr x0, x0, x1
ret
OK?
Thanks,
James
---
gcc/
2017-06-12 James Greenhalgh
* match.pd (A / (1 << B) -> A >> B): New.
gcc/testsuite/
2017-06-12 James Greenhalgh
* gcc.dg/tree-ssa/forwprop-37.c: New.
diff -
ks,
James
---
gcc/
2017-06-12 James Greenhalgh
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl_internal): Remove DImode.
(*aarch64_simd_bsl_alt): Likewise.
(aarch64_simd_bsldi_internal): New.
gcc/testsuite/
2017-06-12 James Greenhalgh
* gcc.targe
OK?
Thanks,
James
---
gcc/
2017-06-12 James Greenhalgh
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl_internal): Remove DImode.
(*aarch64_simd_bsl_alt): Likewise.
(aarch64_simd_bsldi_internal): New.
gcc/testsuite/
2017-06-12 James Greenhalgh
issue - there's no functional
change here.
OK?
Thanks,
James
---
gcc/
2017-06-12 James Greenhalgh
* config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
and store1/2/3/4 to store_4/8/12/16.
* config/aarch64/aarch64.md: Update for rename.
*
e.
OK?
Thanks,
James
---
2017-06-12 James Greenhalgh
* config/aarch64/aarch64.md (movdi_aarch64): Set load/store
types correctly.
(movti_aarch64): Likewise.
(movdf_aarch64): Likewise.
(movtf_aarch64): Likewise.
(load_pairdi): Likewise.
r
you've given it, so I don't see a right place over there.
The change is defensible, but I don't really know the ARM back end.
Bootstrapped on arm-none-linux-gnueabihf.
OK?
Thanks,
James
---
gcc/
2017-06-12 James Greenhalgh
PR target/71778
* config/arm
On Tue, Jun 13, 2017 at 10:24:59AM +, Hurugalawadi, Naveen wrote:
> Hi James,
>
> Thanks for your review and useful comments.
>
> >> If you could try to keep one reply chain for each patch series
> Will keep that in mind for sure :-)
>
> >> Very minor, but what is wrong with:
> >> int matche
This patch is pretty huge, are there any opportunities to further split
it to aid review?
I have some comments in line.
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index
> a069427f576f6bd7336bbe4497249773bd33d138..2ab2d96e40e80a79b5648046ca2d6e202d3939a2
> 10064
On Wed, Jun 07, 2017 at 12:38:37PM +0100, Tamar Christina wrote:
> Hi All,
>
>
> This patch adds support for creating floating point constants
> using mov immediate instructions. The movi SIMD instruction can
> be used for HFmode and SFmode constants, eg. for -0.0f we generate:
>
> mov
On Wed, Jun 14, 2017 at 08:53:27AM +, Hurugalawadi, Naveen wrote:
> Hi James,
>
> >> Could you make the testcase a bit more comprehensive?
>
> Modified the testcase considering all the possible cases.
> Split up the test based on different scenarios.
>
> Please review the patch and let us k
On Wed, Jun 07, 2017 at 12:38:41PM +0100, Tamar Christina wrote:
> Hi All,
>
>
> This patch adds new tests to cover the newly generated code from this patch
> series.
>
>
> Regression tested on aarch64-none-linux-gnu and no regressions.
>
> OK for trunk?
OK.
Thanks,
James
>
> gcc/testsui
On Thu, Apr 27, 2017 at 05:07:26AM +, Hurugalawadi, Naveen wrote:
> Hi Wilco,
>
> >> You should only return true if there is a match, not if there is
> >> not a match.
>
> Done.
>
> Bootstrapped and Regression tested on AArch64 and X86_64.
> Please review the patch and let us know if its oka
On Fri, May 05, 2017 at 05:02:46PM +0100, Wilco Dijkstra wrote:
> Richard Earnshaw (lists) wrote:
>
> > --- a/gcc/config/arm/aarch-common.c
> > +++ b/gcc/config/arm/aarch-common.c
> > @@ -254,12 +254,7 @@ arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
> > return 0;
> >
> > if ((
On Tue, Jun 13, 2017 at 03:00:28PM +0100, Wilco Dijkstra wrote:
>
> ping
I've been avoiding reviewing this patch as Richard was the last to comment
on it, and I wasn't sure that his comments had been resolved to his
satisfaction. The conversation was back in August 2016 on v1 of the patch:
> Ric
On Mon, Jun 12, 2017 at 02:16:44PM +0100, Wilco Dijkstra wrote:
> The Cortex-A53 scheduler model of FMAC bypass is not quite right
> for FMAC to FMAC forwarding. Experiments also show the latencies of
> FP operations are too high as well. Rather than adding more bypasses,
> adjust the latencies o
On Tue, Jun 13, 2017 at 10:43:05AM +0100, Wilco Dijkstra wrote:
> Richard Earnshaw (lists) wrote:
> >
> > Why 1 and not 2? Many processors have 2 fp pipes and forcing this down
> > to a sequential stream is not obviously the right thing.
>
> 1 was faster than 2. Like I said, the reassociation is
On Mon, Mar 06, 2017 at 05:08:57AM +, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that adds "addr_type" attribute
> for AArch64.
>
> The patch doesn't change spec but improve other benchmarks.
What am I missing - you add a new function which is never called? This pa
On Mon, Oct 31, 2016 at 06:29:21PM +, Wilco Dijkstra wrote:
> This patch cleans up all code related to the frame pointer. On AArch64 we
> emit a frame chain even in cases where the frame pointer is not required.
> So make this explicit by introducing a boolean emit_frame_chain in
> aarch64_fra
just use
mode[argc] as that will get you the scalar mode), we can just return target
directly. That will ensure we've given something valid back in the correct
mode, even if it is not all that useful.
Bootstrapped on arm-none-linux-gnueabihf. OK?
Thanks,
James
---
gcc/
2017-06-15 James Gr
On Mon, Jun 12, 2017 at 03:56:25PM +0200, Richard Biener wrote:
> On Mon, 12 Jun 2017, James Greenhalgh wrote:
>
> >
> > Hi,
> >
> > As subject, for the testcase in the patch:
> >
> > unsigned long
> > f2 (unsigned long a, int b)
> >
On Fri, Jun 16, 2017 at 11:07:41AM +0100, Kyrill Tkachov wrote:
>
> On 16/06/17 10:07, James Greenhalgh wrote:
> >On Wed, Jun 14, 2017 at 11:21:30AM +0100, Kyrill Tkachov wrote:
> >
> > <...>
> >
> >>That movv2di expander is the one in vec-common.m
On Tue, Jun 20, 2017 at 11:57:59AM +0100, Wilco Dijkstra wrote:
> Improve the dup pattern to prefer vector registers. When doing a dup
> after a load, the register allocator thinks the costs are identical
> and chooses an integer load. However a dup from an integer register
> includes an int->fp
On Tue, Jun 20, 2017 at 12:06:29PM +0100, Wilco Dijkstra wrote:
> SIMD moves are currently emitted as ORR. Change this to use the MOV
> pseudo instruction just like integer moves (the ARM-ARM states MOV is the
> preferred disassembly), improving readability of -S output.
>
> Passes bootstrap, OK
Hi,
This patch rearranges the cores in aarch64-cores.def first by architecture
revision, then by alphabetical order of implementer ID.
This just neatens up the file a bit, as it is growing to be unwieldy.
Committed as revision 249410.
Thanks,
James
---
2017-06-20 James Greenhalgh
e committed this as obvious to trunk (as revision 249411) and gcc-7-branch
(as revision 249413).
Thanks,
James
[1] Patchwork arm64: Add support for Half precision floating point
https://patchwork.kernel.org/patch/8124451/
---
2017-06-20 James Greenhalgh
* config/aarch64/aarch64-opt
ed, and checked that we
correctly pass +rcpc on to the assembler if we give something like
-mcpu=generic+rcpc .
OK?
Thanks,
James
---
2017-06-20 James Greenhalgh
* config/aarch64/aarch64-option-extensions.def (rcpc): New.
* config/aarch64/aarch64.h (AARCH64_FL_RCPC): New.
d
On Fri, Jun 16, 2017 at 10:06:51AM -0700, Steve Ellcey wrote:
>
> https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00021.html
>
> Ping.
Hi Steve,
These changes all look like they are to the tree pass rather than to the
AArch64 back end. Maybe reposting it without the AArch64 tag will get it
more v
0, 32, 32
fmovs2, w3
fmovs3, w0
ret
I've benchamrked this with Spec2000 and found no performance differences.
And bootstrapped on aarch64-none-linux-gnu with no issues.
Does this look like a sensible approach and if so, is it OK for trunk?
Thanks,
James
---
gc
n the patch,
-mcpu=cortex-a75 is treated as equivalent to passing -mtune=cortex-a75
-march=armv8.2-a+rcpc .
Tested on aarch64-none-elf with no issues.
OK for trunk?
Thanks,
James
---
2017-06-20 James Greenhalgh
* config/aarch64/aarch64-cores.def (cortex-a55): New.
(corte
On Fri, Jun 16, 2017 at 11:41:57AM +0200, Richard Biener wrote:
> On Fri, 16 Jun 2017, James Greenhalgh wrote:
> > On Mon, Jun 12, 2017 at 03:56:25PM +0200, Richard Biener wrote:
> > > + We can't do the same for signed A, as it might be negative, which
> > > wou
*ping*
Thanks,
James
On Mon, Jun 12, 2017 at 02:44:40PM +0100, James Greenhalgh wrote:
> [Sorry for the re-send. I spotted that the attributes were not right for the
> new pattern I was adding. The change between this and the first version was:
>
> + [(set_attr "type&qu
On Mon, Jun 12, 2017 at 03:28:52PM +0100, Kyrill Tkachov wrote:
>
> On 12/06/17 14:53, James Greenhalgh wrote:
> >Hi,
> >
> >In the AArch64 backend and scheduling models there is some confusion as to
> >what the load1/load2 etc. scheduling types refer to. This leads
*ping*
Thanks,
James
On Mon, Jun 12, 2017 at 02:54:00PM +0100, James Greenhalgh wrote:
>
> Hi,
>
> There seems to be a partial misconception in the AArch64 backend that
> load1/load2 referred to the number of registers to load, rather than the
> number of words to load. Thi
On Tue, Jun 20, 2017 at 11:13:24AM -0700, Andrew Pinski wrote:
> Here is the updated patch based on the new infrastructure which is now
> included.
>
> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions
> and tested again on SPEC CPU 2006 on THunderX T88 with the speed up
> men
On Tue, Jun 20, 2017 at 02:07:22PM -0700, Andrew Pinski wrote:
> On Mon, Jun 19, 2017 at 2:00 PM, Andrew Pinski wrote:
> > On Wed, Jun 7, 2017 at 10:16 AM, James Greenhalgh
> > wrote:
> >> On Fri, Dec 30, 2016 at 10:05:26PM -0800, Andrew Pinski wrote:
> >&g
On Wed, Jun 21, 2017 at 02:48:20PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> As Andrew pointed out, the patch at r248921
> (https://gcc.gnu.org/ml/gcc-patches/2017-02/msg01648.html) that allowed
> const0_rtx as an argument to the compare-exchange patterns was incomplete. It
> didn't extend the TA
t;
> Ok with that change.
Oh, I see what you mean. Sorry for not getting that correct last time round.
This is what I committed to trunk as revision 249502 after bootstrapping and
testing on aarch64-none-linux-gnu without any issues.
Thanks,
James
gcc/
2017-06-22 James Greenhalg
Resending for the list, as the last copy got bounced.
Thanks,
James
- Forwarded message from James Greenhalgh -
Date: Thu, 22 Jun 2017 11:16:38 +0100
From: James Greenhalgh
To: Michael Collison , Wilco Dijkstra
, Christophe Lyon , GCC
Patches , nd ,
richard.sandif...@linaro.org
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