On Thu, Mar 10, 2016 at 01:37:50PM +0100, Christophe Lyon wrote:
> On 10 March 2016 at 12:43, James Greenhalgh wrote:
> > On Tue, Jan 26, 2016 at 03:43:36PM +0100, Christophe Lyon wrote:
> >> With the attachment
> >>
> >>
> >> On 26 Januar
On Thu, Mar 03, 2016 at 11:38:11AM +, Kyrill Tkachov wrote:
> Hi all,
>
> This patch fixes the ICE that was introduced by my earlier patch to
> aarch64_set_current_function:
> FAIL: gcc.dg/torture/pr52429.c -O2 -flto -fno-use-linker-plugin
> -flto-partition=none (internal compiler error)
>
On Mon, Mar 07, 2016 at 01:12:16PM +, Nick Clifton wrote:
> Hi Kyrill,
>
> > This is missing a second hunk from the patch you attached in the PR that I
> > think is necessary
> > for this to work (setting to x_flag_omit_frame_pointer)...
>
> Doh! Silly me - there was a snafu restoring the p
On Thu, Mar 10, 2016 at 03:42:38PM +, Kyrill Tkachov wrote:
> Hi all,
>
> When extending the aarch64_handle_option function for GCC 6 I introduced a
> thinko
> when handling the -momit-leaf-frame-pointer option and had it set the variable
> for -fomit-frame-pointer instead. This hasn't been p
On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote:
> >I agree to postpone until GCC 7.
> >
> >[AArch64] Replace insn to zero up SIMD registers
> >
> >gcc/
> >* config/aarch64/aarch64.md
> >(*movhf_aarch64): Add "movi %0, #0" to zero up register.
On Fri, Mar 11, 2016 at 03:19:54PM +, Kyrill Tkachov wrote:
> Hi all,
>
> I've been seeing this test FAIL for a toolchain configured with
> --with-cpu=cortex-a57 in the scan vectoriser dump check because the cost
> model for -mtune=cortex-a57 decides not to vectorise.
>
> This patch disables
On Mon, Mar 07, 2016 at 10:54:25PM -0800, Andrew Pinski wrote:
> On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) wrote:
> >> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix)
> >> wrote:
> >> > Hi,
> >> >
> >> > As discussed in LKML:
> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2
On Tue, Mar 15, 2016 at 03:18:43PM +0100, Andreas Schwab wrote:
> Like x32, aarch64 ILP32 needs to define FFI_SIZEOF_JAVA_RAW. This fixes
> the java interpreter.
Should this go through upstream libffi first? I can't remember the right
order for these.
Anyway, this is OK in whatever order is need
On Tue, Mar 15, 2016 at 03:46:00PM +0100, Andreas Schwab wrote:
> * include/private/gcconfig.h [AARCH64] (ALIGNMENT, CPP_WORDSZ):
> Define for __ILP32__.
OK.
Thanks,
James
> ---
> boehm-gc/include/private/gcconfig.h | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
On Wed, Mar 16, 2016 at 02:25:27PM -0700, Richard Henderson wrote:
> PR target/70048
> * config/aarch64/aarch64.c (virt_or_elim_regno_p): New.
> (aarch64_classify_address): Use it.
> (aarch64_legitimize_address): Force all subexpressions of PLUS
> into regist
On Wed, Mar 16, 2016 at 02:45:37PM -0500, Evandro Menezes wrote:
> On 03/08/16 16:08, Evandro Menezes wrote:
> >On 02/16/16 14:56, Evandro Menezes wrote:
> >>On 12/08/15 15:35, Evandro Menezes wrote:
> >>>Emit square root using the Newton series
> >>>
> >>> 2015-12-03 Evandro Menezes
> >>>
> >
On Wed, Mar 30, 2016 at 11:18:27AM -0500, Evandro Menezes wrote:
>Add scalar 0.0 to the aarch64_simd_reg_or_zero predicate.
>
>2016-03-30 Evandro Menezes
>
> * gcc/config/aarch64/predicates.md
> (aarch64_simd_reg_or_zero predicate): Add the "const_double"
>constrain
change.
Built and tested on an arm-none-linux-gnueabihf box with no issues.
OK?
Thanks,
James
---
2016-03-31 James Greenhalgh
* config/arm/linux-elf.h (ASM_OUTPUT_DEF): Delete.
---
[1]: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00018.html
diff --git a/gcc/config/arm/linux-elf
On Thu, Mar 31, 2016 at 02:11:49PM +0100, Ramana Radhakrishnan wrote:
> Hi,
>
> In this PR we have a situation where we aren't really detecting
> weak references vs weak definitions. If one has a weak definition
> that binds locally there's no reason not to put out PC relative
> relocations.
On Mon, Jan 25, 2016 at 12:15:48PM +, James Greenhalgh wrote:
> On Wed, Jan 20, 2016 at 09:27:41PM +0100, Roger Ferrer Ibáñez wrote:
> > Hi James,
> >
> > > This patch looks technically correct to me, though there is a small
> > > style issue to correct (in
On Fri, Apr 01, 2016 at 02:47:05PM +0100, Wilco Dijkstra wrote:
> Evandro Menezes wrote:
> >
> > Ping^1
>
> I haven't seen a newer version that incorporates my feedback. To recap what
> I'd like to see is a more general way to select approximations based on mode.
> I don't believe that looking at
Hi,
This change reflects binutils support for CRC, where it is always enabled
for armv8.1-a.
OK?
Thanks,
James
---
2016-04-06 James Greenhalgh
* config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_1): Also add
AARCH64_FL_CRC.
diff --git a/gcc/config/aarch64/aarch64.h b/gcc
Patch AArch64 1/3] Enable CRC by default for armv8.1-a
2016-04-06 James Greenhalgh
* config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_1): Also add
AARCH64_FL_CRC.
[Patch AArch64 2/3] Rework the code to print extension strings (pr70133)
gcc/
2016-04-06 James Greenhalgh
rch64-none-linux-gnu and tested for the defaults, and
with an explicit -march=native passed to dejagnu.
OK?
Thanks,
James
---
gcc/
2016-04-06 James Greenhalgh
PR target/70133
* config/aarch64/aarch64-common.c (aarch64_option_extension): Keep
track of a canonical flag
check the input data in pr70133.
OK?
Thanks,
James
---
2016-04-06 James Greenhalgh
PR target/70133
* config/aarch64/driver-aarch64.c
(aarch64_get_extension_string_for_isa_flags): New.
(arch_extension): Rename to...
(aarch64_arch_extension
On Thu, Apr 07, 2016 at 05:23:59PM +0200, Christophe Lyon wrote:
> On 6 April 2016 at 12:10, James Greenhalgh wrote:
> >
> > Hi,
> >
> > This change reflects binutils support for CRC, where it is always enabled
> > for armv8.1-a.
> >
>
> Does v8.1 alw
s the diff regenerated with '-w' to skip the whitespace changes.
OK?
Thanks,
James
> ---
> 2016-04-06 James Greenhalgh
>
> PR target/70133
>
> * config/aarch64/driver-aarch64.c
> (aarch64_get_extension_string_for_isa_flags): New.
>
On Thu, Apr 14, 2016 at 02:24:48PM +0100, Kyrill Tkachov wrote:
> Ping.
> https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00142.html
>
> Thanks,
> Kyrill
> On 04/04/16 10:10, Kyrill Tkachov wrote:
> >Hi all,
> >
> >I'd like to backport Nicks' patch for PR 70044 to the GCC 5 branch.
> >The patch does
On Fri, Apr 15, 2016 at 03:12:58PM +0100, Kyrill Tkachov wrote:
>
> On 15/04/16 15:10, Kyrill Tkachov wrote:
> >Hi all,
> >
> >This is a repost of Andrew's fix for PR target/64971 that was originally
> >posted at:
> >https://gcc.gnu.org/ml/gcc-patches/2015-02/msg00502.html
> >
> >The only change
On Fri, Apr 22, 2016 at 07:59:41AM +0200, Wladimir J. van der Laan wrote:
> The lane parameter is not unused, so should not be marked as such.
>
> The others were removed in https://patchwork.ozlabs.org/patch/272912/,
> but this one appears to have been missed.
The patch looks good to me, and is
On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
> If there's anything I've missed it's purely my oversight, feel free to add
> entries or suggest improvements.
For me, I'm mostly happy with th
On Fri, Apr 22, 2016 at 11:02:48AM +0100, Szabolcs Nagy wrote:
> Some gcc source files include standard headers after
> "system.h" but those headers may declare and use poisoned
> symbols, they also cannot be included before "system.h"
> because they might depend on macro definitions from there,
>
On Mon, Apr 25, 2016 at 05:39:45PM +0200, Wladimir J. van der Laan wrote:
>
> Thanks for the info with regard to contributing,
>
> On Fri, Apr 22, 2016 at 09:40:11AM +0100, James Greenhalgh wrote:
> > This patch will need a ChangeLog entry [1], please draft one that I can
&g
On Mon, Sep 05, 2016 at 03:59:18PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch allows the FP register to be used as a call-saved
> register when -fomit-frame-pointer is used.
>
> The change is done in such a way that the defaults do not change.
> To use the FP register both -fomit-fram
On Tue, Sep 06, 2016 at 10:19:50AM +0100, James Greenhalgh wrote:
> This patch adds patterns for conversion from 64-bit integer to 16-bit
> floating-point values under AArch64 targets which don't have support for
> the ARMv8.2-A 16-bit floating point extensions.
>
> We impl
On Tue, Sep 13, 2016 at 01:39:39PM +0100, Tamar Christina wrote:
> Hi all,
>
> This fixes a bug in the name mangling which prevented mangling
> of functions with return type void and arguments that require
> any qualifiers. e.g. void(unsigned int, unsigned int).
>
> Ran regression tests on aar
On Tue, Sep 13, 2016 at 01:54:15PM +0100, Tamar Christina wrote:
> Hi all,
>
> This patch adds the following NEON intrinsics to the ARM Aarch64 GCC
> (and fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72758):
>
> Added new tests for these and ran regression tests on aarch64-none-linux-gnu
On Mon, Sep 19, 2016 at 03:22:39PM +0200, Christophe Lyon wrote:
> Hi,
>
>
> On 19 September 2016 at 10:39, Tamar Christina
> wrote:
> >
> >
> > On 17/09/16 07:20, James Greenhalgh wrote:
> >
> >
> > Hi James,
> >
> >> The conv
On Tue, Sep 13, 2016 at 01:15:39PM +0100, Tamar Christina wrote:
>
>
> On 05/09/16 22:37, Andrew Pinski wrote:
> >On Mon, Sep 5, 2016 at 4:53 AM, Tamar Christina
> >wrote:
> >>Hi all,
> >>
> >>This patch adds __artificial__ attribute to the intrinsics
> >>in arm_neon.h so that costs are associa
On Tue, Sep 20, 2016 at 10:09:14AM +0100, James Greenhalgh wrote:
> On Tue, Sep 13, 2016 at 01:15:39PM +0100, Tamar Christina wrote:
>>
> Thanks, I applied this following your script above, and committed it as
> revision 240256, after tweaking one part of the script to replace a
On Tue, Sep 20, 2016 at 04:37:42PM +0100, Tamar Christina wrote:
> Hi All,
>
> This patch fixes the regression failures introduced by r240256.
> It adds some missing attributes to the functions:
>
> * vst2_s64
> * vst2_u64
> * vst2_f64
> * vst2_s8
> * vst3_s64
> * vst3_u64
> * vst3_f64
>
On Tue, Sep 13, 2016 at 10:31:28AM +0100, James Greenhalgh wrote:
> On Tue, Sep 06, 2016 at 10:19:50AM +0100, James Greenhalgh wrote:
> > This patch adds patterns for conversion from 64-bit integer to 16-bit
> > floating-point values under AArch64 targets which don't have
ested on x86_64 with --enable-languages=all,ada,go,obj-c++
with no issues.
OK?
Thanks,
James
---
gcc/
2016-09-22 James Greenhalgh
* defaults.h (TARGET_FLT_EVAL_METHOD_NON_DEFAULT): Remove.
* system.h (TARGET_FLT_EVAL_METHOD_NON_DEFAULT): Poison.
gcc/c-family/
2016-09-
On Tue, Sep 27, 2016 at 04:40:22PM +0530, Senthil Kumar Selvaraj wrote:
> Hi,
>
> This patch requires int32plus for
> gcc.dg/tree-ssa/builtin-sprintf-warn-1.c, as it reports a bunch of
> failures for a 16 bit int target like the avr. The "%u" format
> specifier tests, for example, use int
On Wed, Sep 21, 2016 at 10:42:03AM +0100, James Greenhalgh wrote:
> On Tue, Sep 13, 2016 at 10:31:28AM +0100, James Greenhalgh wrote:
> > On Tue, Sep 06, 2016 at 10:19:50AM +0100, James Greenhalgh wrote:
> > > This patch adds patterns for conversion from 64-bit integer to 16-
On Thu, Sep 22, 2016 at 05:55:21PM +, Joseph Myers wrote:
> On Thu, 22 Sep 2016, James Greenhalgh wrote:
>
> > The relaxation isn't portable, and keeping it in place is tricky, so this
> > patch removes it, and poisons TARGET_FLT_EVAL_METHOD_NON_DEFAULT in
> > s
excess precision intentions
gcc/
2016-09-30 James Greenhalgh
* target.def (excess_precision): New hook.
* target.h (flt_eval_method): New.
(excess_precision_type): Likewise.
* targhooks.c (default_excess_precision): New.
* targhooks.h (default_ex
he range of values to {-1, 0, 1, 2}, those are
the only values we see. At this stage in the patch series this trivially
holds for all targets.
Bootstrapped on x86_64 with no issues and tested in series on AArch64.
OK?
Thanks,
James
---
gcc/c-family/
2016-09-30 James Greenha
Hi,
Now that we've worked on -fexcess-precision, the comment in targhooks.c
no longer holds. We can now permit _Float16 on any target which provides
HFmode and supports HFmode in libgcc.
Bootstrapped and tested on x86-64, and in series on AArch64.
OK?
Thanks,
James
---
2016-09-30
James Greenhalgh
* target.def (excess_precision): New hook.
* target.h (flt_eval_method): New.
(excess_precision_type): Likewise.
* targhooks.c (default_excess_precision): New.
* targhooks.h (default_excess_precision): New.
* doc/tm.texi.in
x86_64 and aarch64 with no issues.
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* toplev.c (init_excess_precision): Delete most logic.
* tree.c (excess_precision_type): Rewrite to use
TARGET_EXCESS_PRECISION.
* doc/invoke.texi (-fexcess-precision): Document be
Hi,
We've removed all uses of TARGET_FLT_EVAL_METHOD, so we can remove it
and poison it.
Bootstrapped and tested on x86-64 and AArch64. Tested on s390 and m68k
to the best of my ability (no execute tests).
OK?
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* config/s390
Hi,
This patch ports the logic from i386's TARGET_FLT_EVAL_METHOD to the new
target hook TARGET_C_EXCESS_PRECISION.
Bootstrapped and tested with no issues.
OK?
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* config/i386/i386.c (ix86_excess_precision)
code when compiling
testsuite/gcc.target/i386/excess-precision* to show no difference in
code-generation.
OK?
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* config/s390/s390.c (s390_excess_precision): New.
(TARGET_C_EXCESS_PRECISION): Define.
diff --git a/gcc/config
code when compiling
testsuite/gcc.target/i386/excess-precision* to show no difference in
code-generation.
OK?
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* config/m68k/m68k.c (m68k_excess_precision): New.
(TARGET_C_EXCESS_PRECISION): Define.
diff --git a/gcc/config
Hi,
This patch merges in the support added to glibc for HFmode conversions in
this patch:
commit 87ab10d6524fe4faabd7eb3eac5868165ecfb323
Author: James Greenhalgh
Date: Wed Sep 21 21:02:54 2016 +
[soft-fp] Add support for various half-precision conversion routines
Hi,
This patch merges in the support added to glibc for HFmode conversions in
this patch:
commit 87ab10d6524fe4faabd7eb3eac5868165ecfb323
Author: James Greenhalgh
Date: Wed Sep 21 21:02:54 2016 +
[soft-fp] Add support for various half-precision conversion routines
Hi,
Finally, this patch adds the back-end wiring to get AArch64 support for
the _Float16 type working.
Bootstrapped on AArch64 with no issues.
OK?
Thanks,
James
---
2016-09-30 James Greenhalgh
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Update
Hi,
This patch enables the conversion functions we need for AArch64's _Float16
support. To do that we need to implement TARGET_SCALAR_MODE_SUPPORTED_P,
so do that now.
OK?
Thanks,
James
---
gcc/
2016-09-30 James Greenhalgh
* config/aarch64/aarch6
On Fri, Sep 30, 2016 at 05:57:45PM +, Joseph Myers wrote:
> On Fri, 30 Sep 2016, Jeff Law wrote:
>
> > On 09/30/2016 11:34 AM, Joseph Myers wrote:
> > > On Fri, 30 Sep 2016, James Greenhalgh wrote:
> > >
> > > > + case EXCESS_PR
On Thu, Jul 07, 2016 at 05:18:41PM +0100, Jiong Wang wrote:
> ARMv8.2-A adds support for scalar and vector FP16 instructions to ARM and
> AArch64. This patch adds support for testing code for AArch64 targets
> using the new instructions. It is based on the target-support code for
> ARMv8.2-A added
On Thu, Jul 07, 2016 at 05:19:09PM +0100, Jiong Wang wrote:
> This patch contains testcases for those new scalar intrinsics which are only
> available for AArch64.
OK.
Thanks,
James
>
> gcc/testsuite/
> 2016-07-07 Jiong Wang
>
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
On Thu, Jul 07, 2016 at 05:19:25PM +0100, Jiong Wang wrote:
> This patch contains testcases for those new vector intrinsics which are only
> available for AArch64.
OK.
Thanks,
James
> gcc/testsuite/
> 2016-07-07 Jiong Wang
>
> * gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c: New
On Thu, Jul 07, 2016 at 05:19:37PM +0100, Jiong Wang wrote:
> This patch contains testcases for those new scalar intrinsics which are only
> available for AArch64.
OK.
Thanks,
James
> gcc/testsuite/
> 2016-07-07 Jiong Wang
>
> * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.in
On Wed, Oct 05, 2016 at 05:44:08PM +0100, Jiong Wang wrote:
> On 27/09/16 17:03, Jiong Wang wrote:
> >
> > Now as ARM patches have gone in around r240427, I have done a
> quick confirmation
> > on the status of these four pending testsuite patches:
> >
> > https://gcc.gnu.org/ml/gcc-patches/2016-
On Fri, Oct 07, 2016 at 01:34:37PM -0700, Andrew Pinski wrote:
> On Fri, Oct 7, 2016 at 7:52 AM, Kyrill Tkachov
> wrote:
> > Hi all,
> >
> > This patch uses the spellcheck API from David and Jakub [1] to implement
> > hints for the
> > march, mcpu and mtune options to suggest appropriate architect
On Wed, Sep 28, 2016 at 05:17:14PM +0100, James Greenhalgh wrote:
> On Wed, Sep 21, 2016 at 10:42:03AM +0100, James Greenhalgh wrote:
> > On Tue, Sep 13, 2016 at 10:31:28AM +0100, James Greenhalgh wrote:
> > > On Tue, Sep 06, 2016 at 10:19:50AM +0100, James Greenhalgh wrote:
On Fri, Sep 30, 2016 at 05:56:53PM +0100, James Greenhalgh wrote:
>
> This patch introduces TARGET_C_EXCESS_PRECISION. This hook takes a tri-state
> argument, one of EXCESS_PRECISION_TYPE_IMPLICIT,
> EXCESS_PRECISION_TYPE_STANDARD, EXCESS_PRECISION_TYPE_FAST. Which relate to
> the
mfortable with changing it.
>
> An interesting case is imagemagick. They define their ABI-relevant
> MagickRealType based on the size
> of float_t in recent versions but excplicitly without depending on
> FLT_EVAL_METHOD
> (http://www.imagemagick.org/discourse-server/vi
On Fri, Sep 30, 2016 at 11:28:28AM -0600, Jeff Law wrote:
> On 09/30/2016 11:01 AM, James Greenhalgh wrote:
> >
> >Hi,
> >
> >This patch ports the logic from m68k's TARGET_FLT_EVAL_METHOD to the new
> >target hook TARGET_C_EXCESS_PRECISION.
> >
On Fri, Sep 30, 2016 at 05:32:01PM +, Joseph Myers wrote:
> On Fri, 30 Sep 2016, James Greenhalgh wrote:
>
> >/* float.h needs to know this. */
> > + /* We already have the option -fno-fp-int-builtin-inexact to ensure
> > + certain built-in functions follow T
On Fri, Sep 30, 2016 at 06:03:57PM +0100, James Greenhalgh wrote:
> Hi,
>
> Finally, this patch adds the back-end wiring to get AArch64 support for
> the _Float16 type working.
>
> Bootstrapped on AArch64 with no issues.
>
> OK?
I spotted a bug in the way I'd writ
On Thu, Oct 13, 2016 at 06:14:16PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch moves the aarch64-specific FMA steering pass registration into the
> new framework
> that Jakub introduced. With this patch the RTL dump for the steering pass is
> now numbered properly
> so that it appears
On Sat, Oct 15, 2016 at 01:07:12PM +1100, kugan wrote:
> Hi Bin,
>
> On 15/10/16 00:15, Bin Cheng wrote:
> >+/* Test for likely overcommitment of vector hardware resources. If a
> >+ loop iteration is relatively large, and too large a percentage of
> >+ instructions in the loop are vectorized
On Mon, Sep 19, 2016 at 11:22:27AM +0200, Jan Hubicka wrote:
> > On Mon, Sep 19, 2016 at 2:48 AM, Jan Hubicka wrote:
> > > Hi,
> > > this is the patch compensating testsuite I commited after re-testing
> > > on x86_64-linux.
> > >
> > > Other placements of early_thread_jumps does not work veyr wel
On Mon, Oct 17, 2016 at 12:40:18PM +, Wilco Dijkstra wrote:
>
> ping
>
> If the number of integer callee-saves is odd, the FP callee-saves use 8-byte
> aligned LDP/STP. Since 16-byte alignment may be faster on some CPUs, align
> the FP callee-saves to 16 bytes and use the alignment gap for th
On Mon, Oct 17, 2016 at 12:38:36PM +, Wilco Dijkstra wrote:
>
> ping
>
>
> From: Wilco Dijkstra
> Sent: 10 August 2016 17:20
> To: Richard Earnshaw; GCC Patches
> Cc: nd
> Subject: Re: [PATCH][AArch64] Improve stack adjustment
>
> Richard Earnshaw wrote:
> > I see you've added a default
On Tue, Oct 18, 2016 at 07:10:07PM +0100, Wilco Dijkstra wrote:
> James Greenhalgh wrote:
> On Mon, Oct 17, 2016 at 12:38:36PM +, Wilco Dijkstra wrote:
>
> >> + /* We need two add/sub instructions, each one perform part of the
> >> + addition/subtraction, but d
On Sat, Oct 15, 2016 at 07:38:40PM -0700, Andrew Pinski wrote:
> On Wed, Nov 25, 2015 at 11:59 AM, Andrew Pinski wrote:
> Here is finally an updated (fixed) patch (I did not implement the two
> implementer big.LITTLE support yet, that will be for a different patch
> since I also fixed the part no
On Fri, Oct 21, 2016 at 04:57:22PM +0100, Richard Earnshaw (lists) wrote:
> On 21/10/16 14:59, James Greenhalgh wrote:
> > On Sat, Oct 15, 2016 at 07:38:40PM -0700, Andrew Pinski wrote:
> >> On Wed, Nov 25, 2015 at 11:59 AM, Andrew Pinski wrote:
> >> Here is finally
On Wed, Oct 12, 2016 at 04:56:52PM +0100, James Greenhalgh wrote:
> On Wed, Sep 28, 2016 at 05:17:14PM +0100, James Greenhalgh wrote:
> > On Wed, Sep 21, 2016 at 10:42:03AM +0100, James Greenhalgh wrote:
> > > On Tue, Sep 13, 2016 at 10:31:28AM +0100, James Greenhalgh wrote:
>
Hi,
This patch set builds on the AArch64 support for _Float16 that will be added
once the patch set starting at
https://gcc.gnu.org/ml/gcc-patches/2016-09/msg02383.html is accepted.
Unlike the AArch64 support, we've not got too much to do, outside of setting
up a single step conversions between H
Mv8-A machine with no issues, and cross-tested with
a reasonable multi-lib range.
OK?
Thanks,
James
---
libgcc/
2016-10-24 James Greenhalgh
Matthew Wahab
* config/arm/fp16.c (struct format): New.
(binary32): New.
(__gnu_float2h_internal): New. Body moved
conversion function which rounds once only.
Bootstrapped on an ARMv8-A machine with no issues, and cross-tested with
a range of multilibs.
OK?
Thanks,
James
---
libgcc/
2016-10-24 James Greenhalgh
Matthew Wahab
* config/arm/fp16.c (binary64): New
HFmode as supported in libgcc.
Bootstrapped on an ARMv8-A machine, and crosstested with no issues.
OK?
Thanks,
James
---
2016-10-24 James Greenhalgh
* config/arm/arm-builtins.c (arm_simd_floatHF_type_node): Rename to...
(arm_fp16_type_node): ...This, make visibile
can.
This also lets us remove the implementation of TARGET_CONVERT_TO_TYPE.
Bootstrapped on an ARMv8-A machine,and crosstested with no issues.
OK?
Thanks,
James
---
2016-10-24 James Greenhalgh
* config/arm/arm.c (arm_convert_to_type): Delete.
(TARGET_CONVERT_TO_TYPE): Delete
On Wed, Oct 26, 2016 at 12:11:44PM +, Wilco Dijkstra wrote:
> Add a SHA1H pattern with a V2SI input. This avoids unnecessary
> DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).
I think this is incorrect for big endian - element 0 of a vec_select in
big-endian for V4SImode is
On Fri, Oct 28, 2016 at 04:54:05PM +0100, Wilco Dijkstra wrote:
> James Greenhalgh wrote:
> > On Wed, Oct 26, 2016 at 12:11:44PM +, Wilco Dijkstra wrote:
> > > Add a SHA1H pattern with a V2SI input. This avoids unnecessary
> > > DUPs when using intrinsics like vsha1
On Sun, Oct 23, 2016 at 03:37:22PM -0700, Andrew Pinski wrote:
> On Tue, Nov 17, 2015 at 2:10 PM, Andrew Pinski wrote:
> >
> > The way the current code was written assumes all cores have an unique part
> > num which is not true. What they have is an unique pair of implementer and
> > part num. T
ter the rebuild - else we likely would see it here too).
This change adds a dependency on target.h to aarch64-c.o in t-aarch64,
which looks correct.
Thanks,
James
---
2016-11-01 James Greenhalgh
* config/aarch64/t-aarch64 (aarch64-c.o): Depend on TARGET_H.
diff --git a/gcc/config/aarch64/
On Mon, Oct 24, 2016 at 04:19:47PM +, Wilco Dijkstra wrote:
> The add expander still contains some expansion code that was required for the
> previous prolog/epilog code, but which is no longer needed. I also noticed
> that
> the current version splits off immediates from frame addressing ins
On Tue, Nov 01, 2016 at 10:49:10AM +, Jiong Wang wrote:
> >>>Is this ok for trunk?
> >>>
> >>>Thanks,
> >>>Kyrill
> >>>
> >>>2016-10-12 Kyrylo Tkachov
> >>>
> >>>* config/aarch64/aarch64.c (aarch64_register_saved_on_entry): Add
> >>>function comment.
> >>>(aarch64_next_callee_sav
On Tue, Nov 01, 2016 at 11:08:53AM -0700, Andrew Pinski wrote:
> On Tue, Nov 17, 2015 at 2:10 PM, Andrew Pinski wrote:
> > Since ThunderX T88 pass 1 (variant 0) is a ARMv8 part while pass 2 (variant
> > 1)
> > is an ARMv8.1 part, I needed to add detecting of the variant also for this
> > differen
On Fri, Oct 28, 2016 at 09:12:11PM +, Joseph Myers wrote:
> On Fri, 14 Oct 2016, James Greenhalgh wrote:
>
> > + value set for @code{-fexcess-precision=[standard|fast]}.",
>
> I think the correct markup for the option here is:
>
> @option{-fexcess-preci
On Fri, Oct 28, 2016 at 09:09:55PM +, Joseph Myers wrote:
> On Fri, 14 Oct 2016, James Greenhalgh wrote:
>
> > +/* If the join of the implicit precision in which the target will compute
> > + floating-point values and the standard precision in which the target
> &
On Mon, Oct 24, 2016 at 10:24:27PM +, Joseph Myers wrote:
> On Mon, 24 Oct 2016, James Greenhalgh wrote:
>
> > Conversions from double precision floats to the ARM __fp16 are required
> > to round only once.
>
> I'd expect that when fixing this you need to update
&
On Mon, Oct 24, 2016 at 10:28:42PM +, Joseph Myers wrote:
> On Mon, 24 Oct 2016, James Greenhalgh wrote:
>
> > Hi,
> >
> > Finally, having added support for single-step DFmode to HFmode conversions,
> > this patch adds support for _Float16 to the ARM back-end.
On Mon, Jul 04, 2016 at 05:00:18PM +0100, Jiong Wang wrote:
> As the request from
>
> https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01936.html
>
> This patch replace all use of ARMv8.1 to ARMv8.1-A.
>
> OK for trunk?
Thanks for the follow-up.
OK.
Thanks,
James
>
> 2016-07-04 Jiong Wang
On Wed, Jul 06, 2016 at 02:11:51PM +0100, Jiong Wang wrote:
> The current vmaxnm/vminnm float intrinsics are implemented using
> __builtin_aarch64_smax/min which are mapping to backend patterns
> using smin/smax rtl operators. However as documented in rtl.def
>
> "Further, if both operands are
On Thu, Jul 07, 2016 at 10:16:31AM +0100, Jiong Wang wrote:
> I was using dg-xfail-if, (the description is still using "marked as
> XFAIL"...),
> but later found it's actually broken under advsimd-intrinsics,
> UNRESOLVEDs are
> given at the same time instead of clean XFAIL, I suspect those dg-do-w
On Thu, Jul 07, 2016 at 05:13:56PM +0100, Jiong Wang wrote:
> Several data-processing instructions are agnostic to the type of their
> operands. This patch add the mapping between them and those bit- and
> lane-manipulation instructions.
>
> No ARMv8.2-A FP16 extension hardware support is required
On Fri, Jul 08, 2016 at 04:01:33PM +0530, Virendra Pathak wrote:
> Hi James,
>
> Please find the patch after taking care of your comments.
>
>
> > Did you see those patches, and did you consider whether there would be a
> > benefit to doing the same for Vulcan?
> In our simulation environment, w
On Fri, Jul 15, 2016 at 10:08:11AM +0530, Virendra Pathak wrote:
> Hi James/Julian,
>
> Kindly merge this patch to the trunk.
Done as r238372.
Thanks,
James
> >>> gcc/ChangeLog:
> >>>
> >>> Virendra Pathak
> >>> Julian Brown
> >>>
> >>> * config/aarch64/aarch64-cores.def: Update vul
On Thu, Jun 23, 2016 at 02:19:52PM +, Joseph Myers wrote:
> No GCC port supports a floating-point format suitable for _Float128x.
> Although there is HFmode support for ARM and AArch64, use of that for
> _Float16 is not enabled. Supporting _Float16 would require additional
> work on the exc
that in our
cost model, and in many ways we just got lucky previously.
> s/precitable/predictable/ ?
This, and all your other comments regarding spelling and grammar have been
fixed. Thanks.
On Thu, Jun 30, 2016 at 01:58:52PM +0200, Bernd Schmidt wrote:
> On 06/21/2016 05:50 PM, James Greenhal
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