On Thu, Feb 11, 2016 at 01:10:33PM +, Kyrill Tkachov wrote:
> >>>Why not just keep the last string you printed, and use a string compare
> >>>to decide whether to print or not? Sure we'll end up doing a bit more
> >>>work, but the logic becomes simpler to follow and we don't need to pass
> >>>a
On Fri, Feb 12, 2016 at 05:34:21PM +0100, Jakub Jelinek wrote:
> On Fri, Feb 12, 2016 at 03:20:07PM +0100, Bernd Schmidt wrote:
> > >>- mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode;
> > >>+ mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode1;
> > >>if (xmode1 != VOID
On Mon, Feb 08, 2016 at 10:57:44AM +, James Greenhalgh wrote:
> On Mon, Feb 01, 2016 at 01:59:34PM +0000, James Greenhalgh wrote:
> > On Mon, Jan 25, 2016 at 11:21:25AM +0000, James Greenhalgh wrote:
> > > On Mon, Jan 11, 2016 at 11:53:39AM +, James Greenhalgh wrote:
&
On Mon, Feb 08, 2016 at 10:56:29AM +, James Greenhalgh wrote:
> On Tue, Feb 02, 2016 at 10:29:29AM +0000, James Greenhalgh wrote:
> > On Wed, Jan 20, 2016 at 03:22:11PM +0000, James Greenhalgh wrote:
> > >
> > > Hi,
> > >
> > > In a number of c
On Mon, Feb 08, 2016 at 12:52:00PM +, James Greenhalgh wrote:
> On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote:
> >
> > Hi,
> >
> > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> > available when compiling with
On Mon, Feb 08, 2016 at 10:57:10AM +, James Greenhalgh wrote:
> On Mon, Feb 01, 2016 at 02:00:01PM +0000, James Greenhalgh wrote:
> > On Mon, Jan 25, 2016 at 11:20:46AM +0000, James Greenhalgh wrote:
> > > On Mon, Jan 11, 2016 at 12:04:43PM +, James Greenhalgh wrote:
&
On Thu, Jan 21, 2016 at 04:55:40PM -0600, Evandro Menezes wrote:
>
> Got it.
>
> Let me try this again:
>
>Add support for the FCCMP insn types
>
>2016-01-21 Evandro Menezes
>
>gcc/
> * config/aarch64/aarch64.md (fccmp): Change insn type.
> (fccmpe): Like
On Thu, Feb 11, 2016 at 11:03:23PM +0530, Prathamesh Kulkarni wrote:
> Hi,
> aarch64 supports section anchors but it appears
> check_effective_target_section_anchors() doesn't contain entry for it.
> This patch adds for entry for aarch64.
> OK for trunk ?
OK. I presume you tested this, and the tes
On Tue, Feb 16, 2016 at 09:27:00AM +, Kyrill Tkachov wrote:
> Hi all,
>
> As Christophe reported at:
> https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00784.html
>
> The test gcc.target/aarch64/assembler_arch_1.c fails to assemble on older
> assemblers that don't support the LSE architecture ex
On Mon, Feb 15, 2016 at 11:24:53AM -0600, Evandro Menezes wrote:
> On 02/15/16 04:50, James Greenhalgh wrote:
> >On Mon, Feb 08, 2016 at 10:57:10AM +0000, James Greenhalgh wrote:
> >>On Mon, Feb 01, 2016 at 02:00:01PM +, James Greenhalgh wrote:
> >>>On Mon, Ja
On Thu, Feb 18, 2016 at 11:31:02AM +0100, Christophe Lyon wrote:
> On 17 February 2016 at 17:06, Kyrill Tkachov
> wrote:
> > Hi all,
> >
> > I've thought about this check a bit more and I think we can compactly
> > auto-generate checks
> > for any aarch64 architecture extension support in the asse
On Mon, Feb 22, 2016 at 03:07:09PM +, Alan Lawrence wrote:
> On 22/01/16 17:16, Alan Lawrence wrote:
> >
> >On 21/01/16 17:23, Alan Lawrence wrote:
> >>On 18/01/16 17:10, Eric Botcazou wrote:
> >>>
> >>>Could you post the list of files that differ? How do they differ exactly?
> >>
> >>Hmmm. We
On Mon, Feb 22, 2016 at 06:50:44PM -0600, Evandro Menezes wrote:
> In preparation for the patch adding the Newton series also for
> square root, I'd like to propose this patch changing the name of the
> existing tuning flag for the reciprocal square root.
This is fine, other names like sw_rsqrt, e
On Thu, Feb 25, 2016 at 12:00:58PM +0100, Yvan Roux wrote:
> Hi,
>
> On 26 January 2015 at 18:01, Matthew Wahab wrote:
> > Hello,
> >
> > The LEGITIMIZE_RELOAD_ADDRESS macro is only needed for reload. Since the
> > Aarch64 backend no longer supports reload, this macro is not needed and this
> > p
On Thu, Feb 25, 2016 at 09:25:45AM +, Kyrill Tkachov wrote:
> Hi all,
>
> In this wrong-code PR we get bad code when synthesising a TImode right shift
> by variable amount using DImode shifts during expand.
>
> The expand_double_word_shift function expands two paths: one where the
> variable
On Thu, Feb 25, 2016 at 11:04:21AM +, Kyrill Tkachov wrote:
> Hi all,
>
> Seems like aarch64 is suffering from something similar to PR 69245 as well.
> If a target pragma sets the target state to the same as the
> target_option_default_node the node is just a pointer to
> target_option_default
On Thu, Feb 25, 2016 at 02:49:08PM -0600, Joel Sherrill wrote:
> * gcc/config.gcc, libgcc/config.host: Add aarch64-*-rtems*.
> * gcc/config/aarch64/rtems.h: New file.
OK.
Thanks,
James
> ---
> gcc/config.gcc | 11 +--
> gcc/config/aarch64/rtems.h | 28 +++
On Thu, Feb 25, 2016 at 02:49:10PM -0600, Joel Sherrill wrote:
> * contrib/config-list.mk: Add aarch64-rtems and x86_64-rtems
The AArch64 part of this is OK.
Thanks,
James
> ---
> contrib/config-list.mk | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote:
>
> The following fixes PR69951, hopefully the last case of decl alias
> issues with alias analysis. This time it's points-to and the DECL_UIDs
> used in points-to sets not being canonicalized.
>
> The simplest (and cheapest) fix is
On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote:
> On Mon, 29 Feb 2016, James Greenhalgh wrote:
>
> > On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote:
> > >
> > > The following fixes PR69951, hopefully the last case of decl alias
&g
On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
> > On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
> >> Ok for mainline?
> >>
> >>* gensupport.c (process_substs_on_one_elem): Split loop to
> >>complete mark_operands_used_in_mat
On Tue, Mar 01, 2016 at 01:35:18PM +0100, Andreas Krebbel wrote:
> On 03/01/2016 01:15 PM, James Greenhalgh wrote:
> > On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
> >> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
> >>> On 02/29/2016 09:46 AM, An
On Tue, Mar 01, 2016 at 05:56:30PM +0100, Christophe Lyon wrote:
> On 1 March 2016 at 10:51, James Greenhalgh wrote:
> > On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote:
> >> On Mon, 29 Feb 2016, James Greenhalgh wrote:
> >>
> >> > On Fri, Fe
rch64-none-elf with
no issues.
OK?
Thanks,
James
---
2016-03-03 James Greenhalgh
* gcc.dg/vect/bb-slp-34.c: Don't XFAIL for ARM/AArch64.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-34.c b/gcc/testsuite/gcc.dg/vect/bb-slp-34.c
index 418f2b5..7b9511a 100644
--- a/gcc/testsuite
On Fri, Mar 04, 2016 at 12:02:59PM +0100, Jakub Jelinek wrote:
> On Fri, Mar 04, 2016 at 10:41:04AM +, Kyrill Tkachov wrote:
> > Can do. I've moved the dodgy functions into their own separate compile test.
> > The test passes.
> > Ok?
>
> LGTM.
OK from me too.
James
On Thu, Nov 28, 2013 at 10:11:26PM +, Vladimir Makarov wrote:
> Committed as rev. 205498.
>
> 2013-11-28 Vladimir Makarov
>
> PR target/57293
> * ira.h (ira_setup_eliminable_regset): Remove parameter.
> * ira.c (ira_setup_eliminable_regset): Ditto. Add
> SUPPORTS_S
On Mon, Dec 09, 2013 at 11:43:24AM +, Kyrill Tkachov wrote:
> 2013-12-09 Kyrylo Tkachov
>
> * config/arm/arm.md (generic_sched): Add cortexa12.
> (generic_vfp): Likewise.
> * config/arm/arm.c (cortexa12_extra_costs): New cost table.
> (arm_cortex_a12_tune): New tuning st
ption.
Bootstrapped in series and checked on arm-none-linux-gnueabi and
arm-none-eabi.
OK?
Thanks,
James
---
gcc/
2013-12-17 James Greenhalgh
* config/arm/arm-cores.def: Add new column for TUNE_IDENT.
* config/arm/genopt.sh: Improve layout.
* config/arm/arm-tune.md: Regen
Hi,
This patch wires up -mcpu=cortex-a57.cortex-a53 as an option to
-mcpu.
Bootstrapped in series, and sanity checked.
OK?
Thanks,
James
---
2013-12-17 James Greenhalgh
* config/arm/arm-cores.def (cortex-a57.cortex-a53): New.
* doc/invoke.texi: Document -mcpu=cortex-a57
Hi,
This patch wires up -mcpu=cortex-a15.cortex-a7 as an option to
-mcpu.
Bootstrapped in series, with --with-cpu=cortex-a15.cortex-a7.
OK?
Thanks,
James
---
2013-12-17 James Greenhalgh
* config/arm/arm-cores.def (cortex-a15.cortex-a7): New.
* doc/invoke.texi: Document
---
2013-12-17 James Greenhalgh
* config/arm/arm-cores.def (cortex-a57): New.
* doc/invoke.texi: Document -mcpu=cortex-a57.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* config/arm/bpabi.h (BE8_LINK_SPEC): Handle -mcpu=c
Hi,
This patch series adds machinery and functionality to enable
tuning for big.LITTLE systems when compiling for the ARM target.
We take the convention for names to -mcpu that for some big.LITTLE
system where the big core is 'x' and the little core is 'y', the -mcpu
name will be x.y
In order to
character we see.
Thus -mcpu=cortex-a15.cortex-a7 would be truncated to -mcpu=cortex-a15.
Bootstrapped on a ChromeBook and checked for an arm-none-eabi and
an arm-none-linux-gnueabi build.
Thanks,
James
---
gcc/
2013-12-17 James Greenhalgh
* common/config/arm/ar
these specs.
Tested on aarch64-none-elf with no regressions, built on
aarch64-none-linux-gnu with no problems.
OK?
Thanks,
James
---
2013-12-18 James Greenhalgh
* common/config/aarch64/aarch64-common.c
(aarch64_rewrite_selected_cpu): New.
(aarch64_rewrite_mcpu)
Hi,
This patch series adds support for tuning for big.LITTLE systems
when compiling for the AArch64 target.
The patch series progresses as the one for the ARM backend did yesterday.
(http://gcc.gnu.org/ml/gcc-patches/2013-12/msg01475.html)
As with the ARM backend, we take the convention that for
Hi,
This patch wires up support for -mcpu=cortex-a57.cortex-a53.
Tested on aarch64-none-elf with no regressions.
OK?
---
2013-12-18 James Greenhalgh
* config/aarch64/aarch64-cores.def: Add support for
-mcpu=cortex-a57.cortex-a53.
* config/aarch64/aarch64-tune.md
x-gnu
with no issues.
OK?
Thanks,
James
---
2013-12-18 James Greenhalgh
* config/aarch64/aarch64-cores.def: Add new column for
SCHEDULER_IDENT.
* config/aarch64/aarch64-opts.h (AARCH64_CORE): Handle
SCHEDULER_IDENT.
* config/aarch64/aarch64.c (AA
anyone desires, but they make more sense
as this coherent blob.
Tested on aarch64-none-elf.
OK for 4.8-branch?
Thanks,
James
---
gcc/
2013-12-18 James Greenhalgh
Backport from Mainline.
2013-05-01 James Greenhalgh
* config/aarch64/aarch64-simd-builtins.def (cmhs
Ugh.
Now we have two ASM_SPECs which try to handle -mcpu as input.
One of them just returns the input, the other does the cpu rewriting
we actually want, so we can end up with:
gcc -mcpu=cortex-a57.cortex-a53
Getting passed through to the assembler as:
as -mcpu=cortex-a57 -mcpu=cortex-a57
On Wed, Jan 08, 2014 at 12:10:13AM +, Andrew Pinski wrote:
> On Tue, Jan 7, 2014 at 4:05 PM, Marcus Shawcroft
> wrote:
> >
> > Andrew, We know that there are numerous issues with aarch64 BE advsimd
> > support in GCC. The aarch64_be support is very much a work in progress.
> > Tejas sorted
On Fri, Jul 10, 2015 at 01:21:05PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> Some of the testcases in aarch64.exp can fail their scan-assembler patterns
> if if-conversion becomes more aggressive.
>
> This patch adjusts the testcases in case the branches are eliminated and
> further optimisations
On Wed, Jul 15, 2015 at 09:22:01AM +0100, Bin.Cheng wrote:
> Ping^2
> +/* ADD -(immediate). */
I'd like to see a more detailed comment in this case. Probably something
along the lines of:
/* The canonical form of subtract of immediate is
(add op0 minus_imm). Catch that here, m
On Wed, Jul 15, 2015 at 02:44:40PM +0100, Kyrill Tkachov wrote:
> Hi all,
> This pattern performs a csinc of the same register in both operands.
> This form can be written using the shorter alias CINC.
> The ARMv8-A ARM says:
>
> "CINC , ,
> is equivalent to
> CSINC , , , invert()"
>
> So the pa
On Fri, Jun 26, 2015 at 08:14:55PM +0100, Charles Baylis wrote:
> Since the last ping, I've tweaked the test cases a bit...
>
> Since I've been working on doing the same changes for the ARM backend,
> I've moved the tests into the advsimd-intrinsics directory, marked as
> XFAIL for ARM targets for
On Thu, Jul 16, 2015 at 04:20:30PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This first patch adds a field to the processor structure that uniquely
> identifies that processor. Note that the current 'core' field is actually
> just the core for which to schedule the instructions. With this patch
On Thu, Jul 16, 2015 at 04:20:33PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> In this second patch I want to get to the point where I can get an enum that
> I can use to index all_architectures to get the current architecture being
> used, similar to what we
> do in patch 1/N.
>
> The closest thi
On Wed, May 20, 2015 at 05:36:25PM +0100, Jeff Law wrote:
>
> These fix the remaining leaks in the threader that I'm aware of. We
> failed to properly clean-up when we had to cancel certain jump threading
> opportunities. So thankfully this wasn't a big leak.
Hi Jeff,
I don't have a reduced
On Thu, Jul 16, 2015 at 04:20:37PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This one is more meaty than the previous ones. It buffs up the parsing
> functions for
> the mcpu, march, mtune options, decouples them and makes them return an enum
> describing
> the errors that may occur. This will
On Thu, Jul 16, 2015 at 04:48:43PM +0100, Kyrill Tkachov wrote:
> Sorry, had sent out the wrong version.
> This is the right patch.
>
> Thanks,
> Kyrill
>
> On 16/07/15 16:20, Kyrill Tkachov wrote:
> > Hi all,
> >
> > This patch transforms the Cortex-A53 erratum 835769 workaround checks into
> >
On Thu, Jul 16, 2015 at 04:20:45PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch wraps aarch64_frame_pointer_required into a
> TARGET_OMIT_LEAF_FRAME_POINTER macro
> and initializes aarch64_frame_pointer_required to 2 instead of 1, allowing us
> to detect from
> aarch64_frame_pointer_req
On Fri, Jul 17, 2015 at 03:19:20PM +0100, Kyrill Tkachov wrote:
>
>
> This is a slight respin of this patch, handling the -moverride string more
> gracefully.
> We need to explicitly save and restore it in TARGET_OPTION_SAVE otherwise the
> option gen machinery
> gets confused about its type an
On Thu, Jul 16, 2015 at 04:20:56PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements TARGET_SET_CURRENT_FUNCTION and defines
> SWITCHABLE_TARGET.
> With this patch in the series, we should be far enough to get LTO option
> switching to work properly.
>
> The implementation if TAR
On Thu, Jul 16, 2015 at 04:20:59PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements target attribute support via the
> TARGET_OPTION_VALID_ATTRIBUTE_P hook.
> The aarch64_handle_option function in common/config/aarch64/aarch64-common.c
> is exported to the
> backend and beefed up
On Thu, Jul 16, 2015 at 04:21:02PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements the target-specific inlining rules.
> The basic philosophy is that we want to definitely reject inlining if the
> callee's architecture
> is not a subset, feature-wise, of the caller's.
>
> Beyond
On Thu, Jul 16, 2015 at 04:21:05PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements target pragmas for aarch64.
> The pragmas accepted are the same as for target attributes (as required).
> In addition pragmas will need to redefine the target-specific preprocessor
> macros if appro
On Thu, Jul 16, 2015 at 04:21:15PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> These are the tests for target attributes and pragmas.
> I've tried to test for the inlining rules, some of the possible errors and
> the preprocessor macros changed from target pragmas.
>
> Ok for trunk?
Mechanical ch
On Thu, Jul 16, 2015 at 04:21:22PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch improves compilation times for code using the arm_neon.h
> intrinsics.
> The problem there is that since we now wrap all the intrinsics in arm_neon.h
> inside a pragma,
> the midend will apply the pragma str
On Tue, Jul 21, 2015 at 05:59:39PM +0100, Kyrill Tkachov wrote:
> Sorry, here's the correct version, which uses initialized instead of inited
> in one of the variable names.
Some nits below.
>
> Kyrill
>
> 2015-07-21 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c (aarch64_option_valid_
On Wed, May 20, 2015 at 01:35:41PM +0100, Jiong Wang wrote:
> Current IRA still use both target macros in a few places.
>
> Tell IRA to use the order we defined rather than with it's own cost
> calculation. Allocate caller saved first, then callee saved.
>
> This is especially useful for LR/x30,
Hi,
As subject. This makes the naming scheme for insn_reservations consistent in
config/arm/cortex-a53.md.
Checked that we still build a compiler after this cosmetic change, and
committed as obvious as revision 226069.
Thanks,
James
2015-07-22 James Greenhalgh
* config/arm/cortex
On Fri, Jun 26, 2015 at 02:45:39PM +0100, Jiong Wang wrote:
>
> Marcus Shawcroft writes:
>
> 2015-06-26 Jiong Wang
>
> wwwdocs/
> * htdocs/gcc-6/changes.html (AArch64): Document -fpic for small model.
>
> Index: gcc-6/changes.html
>
On Thu, Jul 23, 2015 at 09:38:26AM +0100, Jiong Wang wrote:
>
> James Greenhalgh writes:
>
> > On Fri, Jun 26, 2015 at 02:45:39PM +0100, Jiong Wang wrote:
> >>
> >> Marcus Shawcroft writes:
> >>
> >> 2015-06-26 Jiong Wang
> >>
On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
> >
> > Andrew Pinski writes:
> >
> >>> On Fri, Jul 24, 2015 at 2:07 AM, Jiong Wang wrote:
> >>>
> >>> James Gre
On Mon, Jul 27, 2015 at 03:38:40PM +0100, Wilco Dijkstra wrote:
> ping
> > Various instructions are supported as integer operations as well as SIMD on
> > AArch64. When
> > register pressure is high, lra-constraints inserts spill code without
> > taking the allocation
> > class into account, and
On Mon, Jul 27, 2015 at 03:38:55PM +0100, Wilco Dijkstra wrote:
> This is basically the same as the shl version but for the shr patterns.
>
> Various instructions are supported as integer operations as well as SIMD on
> AArch64. When
> register pressure is high, lra-constraints inserts spill code
On Tue, Jul 28, 2015 at 12:26:09PM +0100, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf):
> Reparameterize to...
> (aarch64_float_truncate_lo_): ...this, for both V2SF and V4HF.
> (aarch64_float_truncate_hi_v4sf):
On Tue, Jul 28, 2015 at 12:25:55PM +0100, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.c (aarch64_split_simd_combine): Add V4HFmode.
> * config/aarch64/aarch64-builtins.c (VAR13, VAR14): New.
> (aarch64_scalar_builtin_types, aarch64_init_simd_builtin_scalar_
On Tue, Jul 28, 2015 at 12:25:06PM +0100, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New.
> (aarch64_init_builtins): Make aarch64_fp16_type_node, use for __fp16.
>
> * config/aarch64/aarch64-modes.def: Add HFmode.
>
>
On Tue, Jul 28, 2015 at 12:25:26PM +0100, Alan Lawrence wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/fp16/fp16.exp: New.
> * gcc.target/aarch64/fp16/f16_convs_1.c: New.
> * gcc.target/aarch64/fp16/f16_convs_2.c: New.
OK.
Thanks,
James
On Tue, Jul 28, 2015 at 12:25:40PM +0100, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.c (aarch64_vector_mode_supported_p): Support
> V4HFmode and V8HFmode.
> (aarch64_split_simd_move): Add case for V8HFmode.
> * config/aarch64/aarch64-builtins.c (v4hf
On Wed, Jul 29, 2015 at 10:10:09AM +0100, Alan Lawrence wrote:
> James Greenhalgh wrote:
> > On Tue, Jul 28, 2015 at 12:26:09PM +0100, Alan Lawrence wrote:
> >> gcc/ChangeLog:
> >>
> >>* config/aarch64/aarch64-simd.md (aarch64_float_truncate
On Tue, Jul 28, 2015 at 12:26:22PM +0100, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/arm_neon.h (vreinterpret_p8_f16, vreinterpret_p16_f16,
> vreinterpret_f16_f64, vreinterpret_f16_s8, vreinterpret_f16_s16,
> vreinterpret_f16_s32, vreinterpret_f16_s64, vreinterpre
On Tue, Jul 28, 2015 at 12:26:35PM +0100, Alan Lawrence wrote:
> commit 214fcc00475a543a79ed444f9a64061215397cc8
> Author: Alan Lawrence
> Date: Wed Jan 28 13:01:31 2015 +
>
> AArch64 6/N: vcvt{,_high}_f32_f16 (using vect_par_cnst_hi_half, fixing
> bigendian indices)
>
> diff --git a/
On Thu, Jul 30, 2015 at 12:47:20PM +0100, Alan Lawrence wrote:
> James Greenhalgh wrote:
> > On Tue, Jul 28, 2015 at 12:25:40PM +0100, Alan Lawrence wrote:
> >
> > I'd have preferred the unrelated changes here as separate patches. If you
> > pull them out, they
On Thu, Jul 30, 2015 at 04:06:22PM +0100, Alan Lawrence wrote:
> James Greenhalgh wrote:
> >>
> >> (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
> >>(V2SI "V8SI") (V2SF "V8SF")
> >> -
On Fri, Jul 24, 2015 at 09:21:46AM +0100, Kyrill Tkachov wrote:
>
> Thanks for the review, here's an updated version.
> In the end, I chose to retain the use alloca (other patches in the series
> are reworked to use it too).
>
> How's this?
A nit or two from code you were moving or that got caug
On Fri, Jul 24, 2015 at 11:43:32AM +0100, Kyrill Tkachov wrote:
>
> On 21/07/15 16:37, James Greenhalgh wrote:
> > On Thu, Jul 16, 2015 at 04:20:59PM +0100, Kyrill Tkachov wrote:
> >> Hi all,
> >>
> >> This patch implements target attribute support via th
On Thu, Jul 23, 2015 at 11:17:20AM +0100, Kyrill Tkachov wrote:
> Thanks, I've implemented the suggestions.
> Re-bootstrapped and tested on aarch64.
> How's this?
This is good. OK for trunk.
Thanks,
James
On Mon, Aug 03, 2015 at 10:36:17AM +0100, Kyrill Tkachov wrote:
> And here is a rebased version to resolve a conflict after Alan's patches went
> in.
>
OK with the nits below fixed.
> 2015-08-03 Kyrylo Tkachov
>
> * config.gcc (aarch64*-*-*): Specify c_target_objs and cxx_target_objs.
On Fri, Jul 24, 2015 at 09:38:34AM +0100, Kyrill Tkachov wrote:
> Thanks, here's an updated version.
>
> 2015-07-24 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c (aarch64_option_valid_attribute_p):
> Initialize simd builtins if TARGET_SIMD.
> * config/aarch64/aarch64-builtins.c
On Fri, Jul 24, 2015 at 09:40:28AM +0100, Kyrill Tkachov wrote:
>
> On 21/07/15 18:14, James Greenhalgh wrote:
> > On Thu, Jul 16, 2015 at 04:21:15PM +0100, Kyrill Tkachov wrote:
> >> Hi all,
> >>
> >> These are the tests for target attributes and pragmas.
&
On Fri, Jul 24, 2015 at 11:55:33AM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements an aarch64-specific expansion of the signed modulo by a
> power of 2.
> The proposed sequence makes use of the conditional negate instruction CSNEG.
> For a power of N, x % N can be calculated with
On Mon, Jul 27, 2015 at 02:22:41PM +0100, Pawel Kupidura wrote:
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 10df325..ffafc3f 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,7 @@
> +2015-07-27 Pawel Kupidura
Two spaces between your name and your email address, like so:
2
On Mon, Aug 03, 2015 at 04:20:13PM +0100, Kyrill Tkachov wrote:
> Ok, I've removed usages of 'ret' in favor of returning when appropriate.
> In this last one I left the ret (but cleaned up the control flow a bit)
> because if the processing fails we need to clean up a bit of state before
> returnin
On Tue, Aug 04, 2015 at 09:58:37AM +0100, Kyrill Tkachov wrote:
>
> On 04/08/15 09:53, James Greenhalgh wrote:
> > On Mon, Aug 03, 2015 at 04:20:13PM +0100, Kyrill Tkachov wrote:
> >> Ok, I've removed usages of 'ret' in favor of returning when appropriate.
On Tue, Jul 28, 2015 at 02:12:36PM +0100, Jiong Wang wrote:
>
> The instruction sequences for preparing argument for TLS descriptor
> runtime resolver and the later function call to resolver can actually be
> hoisted out of the loop.
>
> Currently we can't because we have exposed the hard registe
On Thu, Jul 16, 2015 at 11:21:25AM +0100, Jiong Wang wrote:
>
> Jeff Law writes:
>
> > On 06/23/2015 02:29 AM, Ramana Radhakrishnan wrote:
> >
> >>> If you try disabling the REG_EQUAL note generation [*], you'll probably
> >>> find a
> >>> performance regression on arm32 (and probably on aarch64
On Tue, Jul 21, 2015 at 01:42:35PM +0100, Jiong Wang wrote:
>
> Jiong Wang writes:
>
> > Alexander Monakov writes:
> >
> >>> Attachment is the patch which repair -fno-plt support for AArch64.
> >>>
> >>> aarch64_is_noplt_call_p will only be true if:
> >>>
> >>> * gcc is generating position in
On Thu, Jul 16, 2015 at 10:24:20AM +0100, Szabolcs Nagy wrote:
> On 06/07/15 11:24, James Greenhalgh wrote:
> >
> > Please make sure in a follow-up patch that the costing logic in
> > aarch64_rtx_costs also gets updated.
> >
>
> Tested with aarch64-none-linux
On Tue, Aug 04, 2015 at 11:06:11AM +0100, Pawel Kupidura wrote:
> Hi,
>
> I'm sorry about the issues with formatting, it should be fixed now.
> Here's corrected version with diff to current trunk.
Hi Pawel,
I'm still having trouble getting this patch to apply, I'm not sure whether
it is the for
On Wed, Aug 05, 2015 at 12:09:35PM +0100, Richard Biener wrote:
> On Wed, 5 Aug 2015, Andrew Pinski wrote:
>
> > On Wed, Aug 5, 2015 at 3:16 AM, Richard Biener wrote:
> > > On Wed, 5 Aug 2015, Andreas Schwab wrote:
> > >
> > >> Richard Biener writes:
> > >>
> > >> > * gimple-fold.c (gimple_f
On Wed, Aug 05, 2015 at 02:38:01PM +0100, Richard Biener wrote:
> On Wed, 5 Aug 2015, James Greenhalgh wrote:
>
> > On Wed, Aug 05, 2015 at 12:09:35PM +0100, Richard Biener wrote:
> > > On Wed, 5 Aug 2015, Andrew Pinski wrote:
> > >
> > > > On W
On Wed, Aug 05, 2015 at 02:56:08PM +0100, Richard Biener wrote:
> For reference see below (testing on aarch64 appreciated).
Looks good to me on aarch64-none-elf.
Thanks,
James
> Bootstrap & regtest running on x86_64-unknown-linux-gnu.
>
> Richard.
>
> 2015-08-05 Richard Biener
>
> *
On Mon, Aug 03, 2015 at 12:32:15PM +0100, James Greenhalgh wrote:
> On Fri, Jul 24, 2015 at 09:40:28AM +0100, Kyrill Tkachov wrote:
> >
> > On 21/07/15 18:14, James Greenhalgh wrote:
> > > On Thu, Jul 16, 2015 at 04:21:15PM +0100, Kyrill Tkachov wrote:
> > >>
using
copysign or SIGN from fortran.
OK?
Thanks,
James
---
gcc/
2015-09-16 James Greenhalgh
* config/aarch64/aarch64.md (copysigndf3): New.
(copysignsf3): Likewise.
gcc/testsuite/
2015-09-16 James Greenhalgh
* gcc.target/aarch64/copysign_1.c: New
On Mon, Sep 07, 2015 at 06:54:30AM +0100, Michael Collison wrote:
> This patch is designed to address code that was not being vectorized due
> to missing widening patterns in the aarch64 backend. Code such as:
>
> int t6(int len, void * dummy, short * __restrict x)
> {
>len = len & ~31;
>i
On Thu, Sep 17, 2015 at 05:37:55PM +0100, Matthew Wahab wrote:
> Hello,
>
> ARMv8.1 adds atomic swap and atomic load-operate instructions with
> optional memory ordering specifiers. This patch series adds the
> instructions to GCC, making them available with -march=armv8.1-a or
> -march=armv8+lse,
On Thu, Sep 17, 2015 at 05:40:48PM +0100, Matthew Wahab wrote:
> Hello,
>
> ARMv8.1 adds atomic swap and atomic load-operate instructions with
> optional memory ordering specifiers. This patch adds an expander to
> generate a BIC instruction that can be explicitly called when
> implementing the at
On Thu, Sep 17, 2015 at 05:42:35PM +0100, Matthew Wahab wrote:
> Hello,
>
> ARMv8.1 adds atomic swap and atomic load-operate instructions with
> optional memory ordering specifiers. This patch adds the ARMv8.1 atomic
> load-operate instructions.
>
> Tested the series for aarch64-none-linux-gnu wi
On Thu, Sep 17, 2015 at 05:47:43PM +0100, Matthew Wahab wrote:
> Hello,
>
> ARMv8.1 adds atomic swap and atomic load-operate instructions with
> optional memory ordering specifiers. This patch uses the ARMv8.1 atomic
> load-operate instructions to implement the atomic_fetch_
> patterns. This patch
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