This patch adds support for arguments to the signal and interrupt
function attributes. It allows to specify the ISR by means of the
associated IRQ number, in extension to the current attributes that
require to specify the ISR name like "__vector_1" as (assembly) name
for the function. The new fe
Applied with the addendum below.
Am 23.07.24 um 22:19 schrieb Georg-Johann Lay:
This patch adds support for arguments to the signal and interrupt
function attributes. It allows to specify the ISR by means of the
associated IRQ number, in extension to the current attributes that
require to
Applied the patch below
Johann
--
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 3b3a6c0b..aa8d7609 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -99,7 +99,27 @@ a work-in-progress.
-
+AVR
+
+
+ Support has been added for the signal
Am 10.07.24 um 01:17 schrieb Jeff Law:
On 7/9/24 4:03 AM, Georg-Johann Lay wrote:
Hi Jeff,
This patch adds peephole2s and insns to make better use of
instructions that set condition code (SREG) as a byproduct.
Of course with cc0 all this was *much* simpler... so here we go;
adding CCNmode and
Applied the following patchlet to the documentation.
Johann
--
AVR: Propose to use attribute signal(n) via AVR-LibC's ISR_N.
gcc/
* doc/extend.texi (AVR Function Attributes): Propose to use
attribute signal(n) via AVR-LibC's ISR_N from avr/interrupt.h
diff --git a/gcc/doc/exten
Applied this tweak to the 16-bit and 32-bit comparisons.
Johann
--
gcc/
* config/avr/constraints.md (YMM): New constraint.
* config/avr/avr.md (cmp3, *cmp3)
(cbranch4_insn): Allow YMM where M is allowed.
(cbranch4_insn): Split to a test of the
high part a
Building glibc on the m68k has exposed a long standing latent bug in reload.
Basically ext-dce replaced an extension with a subreg expression (good)
resulting in this pair of insns:
(insn 7 4 8 2 (set (reg:DI 31 [ _1 ])
(subreg:DI (reg/v:SI 37 [ __major ]) 0)) "j.c":7:32 75 {*m68k.md
Am 05.08.24 um 12:28 schrieb Stefan Schulze Frielinghaus:
This is a follow-up of
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/654013.html
What has changed?
- Rebased and fixed an issue in constrain_operands which manifested
after late-combine.
- Introduced new test cases for Arm, Intel,
This is a second take on improving SREG (condition code) usage
for avr.
The difference to the 1st patch is that I added a paragraph to
avr.md that explains why we don't use cmpelim:
- The achievable compare mode may depend on the availability of
a scratch register. SELECT_CC_MODE doesn't prov
Am 05.08.24 um 15:59 schrieb Stefan Schulze Frielinghaus:
On Mon, Aug 05, 2024 at 02:19:50PM +0200, Georg-Johann Lay wrote:
Am 05.08.24 um 12:28 schrieb Stefan Schulze Frielinghaus:
This is rather unfortunate but I couldn't find a way how to validate
register names during genoutput. If n
Applied the following patch..
Johann
--
AVR: Add 8 more avrxmega3 MCUs.
gcc/
* config/avr/avr-mcus.def: Add: avr16du14, avr16du20,
avr16du28,
avr16du32, avr32du14, avr32du20, avr32du28, avr32du32.
* doc/avr-mmcu.texi: Rebuild.
diff --git a/gcc/co
Applied as obvious
Johann
--
AVR: target/114752 - Fix ICE on inline asm const 64-bit float operand
gcc/
PR target/114752
* config/avr/avr.cc (avr_print_operand) [CONST_DOUBLE_P]:
Handle DFmode.
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 4a5a921107b..510
Instead of jumping to a place that ROLs r_arg1 (with C=0),
LSL r_arg1 can be performed prior to the loop. This
reduces the number of loopings from 9 to 8.
Applied as obvious.
Johann
AVR: target/114794 - Tweak __udivmodqi4
libgcc/
PR target/114794
* config/avr/lib1funcs.S (__ud
Am 22.04.24 um 12:04 schrieb Jonathan Wakely:
OK for wwwdocs?
For me it's ok (I am not a native speaker though,
which is the reason the typos are there to begin with).
Johann
htdocs/gcc-14/changes.html | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/ht
Applied to fix this long standing wrong-code bug.
Johann
--
AVR: ipa/92606 - Don't optimize PROGMEM data against non-PROGMEM.
ipa/92606: Inter-procedural analysis optimizes data across
address-spaces and PROGMEM. As of v14, the PROGMEM part is
still not fixed (and there is still no target hoo
Applied this tweak as proposed in the PR.
Johann
--
commit 6b73a9879a4503ebee2cb1a3ad243f60c922ca31
Author: Wolfgang Hospital
Date: Tue May 7 16:24:39 2024 +0200
AVR: target/114835 - Tweak popcountqi2
libgcc/
PR target/114835
* config/avr/lib1funcs.S (__popc
Add a combine pattern for parity detection.
Ok for master?
Johann
AVR: target/114975 - Add combine-pattern for __parityqi2.
PR target/114975
gcc/
* config/avr/avr.md: Add combine pattern for
8-bit parity detection.
gcc/testsuite/
* gcc.target/avr/pr114975-parit
Add a pattern for better popcount detection.
Ok for master?
Johann
--
AVR: target/114975 - Add combine-pattern for __popcountqi2.
PR target/114975
gcc/
* config/avr/avr.md: Add combine pattern for
8-bit popcount detection.
gcc/testsuite/
* gcc.target/avr/pr114
__builtin_powif is currently implemented in C,
and this patch implements it (__powisf2) in assembly.
Ok for master?
Johann
--
AVR: target/114981 - Tweak __powisf2
Implement __powisf2 in assembly.
PR target/114981
libgcc/
* config/avr/t-avr (LIB2FUNCS_EXCLUDE): Add _powisf2.
This adds __powidf2 as a wrapper in LibF7.
Johann
--
avr: target/114981 - Support __builtin_powi[l] / __powidf2.
This supports __powidf2 by means of a double wrapper for already
existing f7_powi (renamed to __f7_powi by f7-renames.h).
It tweaks the implementation so that it does not perform tr
There are cases, where opportunities to use POST_INC addressing
only occur very late in the compilation process. Take for example
the following function from AVR-LibC's qsort:
void swapfunc (char *a, char *b, int n)
{
do
{
char t = *a;
*a++ = *b;
*b++ = t;
} w
Am 30.08.24 um 14:46 schrieb Richard Biener:
On Fri, Aug 30, 2024 at 2:10 PM Georg-Johann Lay wrote:
There are cases, where opportunities to use POST_INC addressing
only occur very late in the compilation process. Take for example
the following function from AVR-LibC's qsort:
void swa
Am 30.08.24 um 15:31 schrieb Richard Biener:
On Fri, Aug 30, 2024 at 3:28 PM Georg-Johann Lay wrote:
Am 30.08.24 um 14:46 schrieb Richard Biener:
On Fri, Aug 30, 2024 at 2:10 PM Georg-Johann Lay wrote:
There are cases, where opportunities to use POST_INC addressing
only occur very late in
The avr backend is using the convention to not
print a space after the comma that separates asm
operands. Applied as obvious.
Johann
AVR: Don't print a space after , when printing instructions.
gcc/
* config/avr/avr.cc: Follow the convention to not add a space
The reason for PR116326 is that LRA and reload require different
ELIMINABLE_REGS for a multi-register frame pointer. As ELIMINABLE_REGS
is used to initialize static const objects, it is not possible to make
ELIMINABLE_REGS to depend on options or patch it in some target hook.
It was also conclud
Am 07.09.24 um 18:35 schrieb Jeff Law:
On 9/6/24 3:40 AM, Georg-Johann Lay wrote:
The reason for PR116326 is that LRA and reload require different
ELIMINABLE_REGS for a multi-register frame pointer. As ELIMINABLE_REGS
is used to initialize static const objects, it is not possible to make
Am 07.09.24 um 19:51 schrieb H.J. Lu:
On Sat, Sep 7, 2024 at 10:49 AM Georg-Johann Lay wrote:
Am 07.09.24 um 18:35 schrieb Jeff Law:
On 9/6/24 3:40 AM, Georg-Johann Lay wrote:
The reason for PR116326 is that LRA and reload require different
ELIMINABLE_REGS for a multi-register frame pointer
The reason for PR116326 is that LRA and reload require different
ELIMINABLE_REGS for a multi-register frame pointer. As ELIMINABLE_REGS
is used to initialize static const objects, it is not possible to make
ELIMINABLE_REGS dependent on -mlra.
It was also concluded that it is not desirable to adj
Am 09.09.24 um 09:08 schrieb Richard Biener:
On Sun, Sep 8, 2024 at 12:22 PM Georg-Johann Lay wrote:
The reason for PR116326 is that LRA and reload require different
ELIMINABLE_REGS for a multi-register frame pointer. As ELIMINABLE_REGS
is used to initialize static const objects, it is not
The order in which multi-byte EQ and NE comparisons are performing
the byte comparisons does not matter, and there are situations where
using SBIW on the high word can save an instruction.
This is for trunk.
Johann
--
AVR: Tweak 32-bit EQ and NE comparisons.
The order in which multi-byte EQ a
This patch reorders functions in avr.cc so that less
forward declarations are needed.
Johann
--
AVR: avr.cc - Reorder functions to require less forward decls.
gcc/
* config/avr/avr.cc (avr_init_machine_status): Move code to...
(avr_option_override) : ...lambda.
(avr_ins
This patch reworks avr_out_compare:
Use new convenient helper functions that may be useful in
other output functions, too.
Generalized some special cases that only work for EQ and NE
comparisons. For example, with the patch
;; R24:SI == -1 (unused after)
adiw r26,1
sbci r25,hi8
Am 10.09.24 um 16:20 schrieb Stefan Schulze Frielinghaus:
This series introduces hard register constraints. The first patch
enables hard register constraints for asm statements and for
machine descriptions. The subsequent patch adds some basic error
handling for asm statements. The third pa
.
(avr_uint16): New function.
commit 3a7ef412ab18cafc96ba664d531295e9f3865f4c
Author: Georg-Johann Lay
Date: Fri Sep 13 12:50:31 2024 +0200
AVR: Use avr_byte instead of simplify_gen_subreg (QImode, ...
There are many places where asm output functions have to look at
the
The transparent call insns like "*parityhi2.libgcc" output a single
[R]CALL instruction that can be skipped by the skip instructions.
Such insns have attribute "type" of "xcall" and can therefore
be easily recognized.
Ok for trunk?
Johann
--
AVR: Detect more skip opportunities.
The tra
This uses new rtx code copysign instead of an unspec.
It also allows const_double as 2nd operand because gcc
does not optimize code like
__builtin_copysignf (x, -1.0f);
Ok for trunk?
Johann
--
AVR: Use rtx code copysign.
gcc/
* config/avr/avr.md (UNSPEC_COPYSIGN): Remove
This patch tidies up enum and struct tags that are
not required in C++. It also uses rtx_code for
RTX codes instead of RTX_CODE. RTX_CODE is now only
used in #ifdef's in avr-protos.h.
Ok for trunk?
Johann
--
AVR: Tidy up enum and struct tags.
Use "rtx_code" for RTX codes, not "enum rtx_code
Unsigned comparisons may skip comparing the lower bytes when
the according bytes of the constant are all zeros. For example,
uint16 >= 0x1200
is true iff
hi8 (uint16) >= hi8 (0x1200)
and similar for uint16 < 0x1200. Some comparisons against constants
that are an integral power of 256
This reverts the part of 2024-09-12 r15-3623 that mixed
ADIW with CPC or SBIC.
https://gcc.gnu.org/r15-3623
Johann
--
AVR: Partially revert r15-3623.
ADIW doesn't mix with CPC / SBIC because it's not only about
propagating the Z flag but also about carry.
gcc/
* config/avr/avr.cc (av
Am 16.09.24 um 13:04 schrieb Denis Chertykov:
вс, 15 сент. 2024 г. в 19:32, Georg-Johann Lay :
Unsigned comparisons may skip comparing the lower bytes when
the according bytes of the constant are all zeros. For example,
uint16 >= 0x1200
is true iff
hi8 (uint16) >= hi8 (
AVR-LibC has been moved to GitHub a while ago. This patch
adjusts web links to the documentation and to the project
page.
Ok for trunk?
Johann
--
AVR: Update weblinks to AVR-LibC.
AVR-LibC has moved to GitHub, adjust web links:
https://github.com/avrdudes/avr-libc (project)
https://avrdudes.
This patch updates more web links from nongnu to Github.
The http://www.nongnu.org/avr links still worked, but the
"super project" seems to be deserted. Instead, it now links:
*
https://avrdudes.github.io/avr-libc/avr-libc-user-manual/install_tools.html
*
https://github.com/sprintersb/atest?ta
Joern Rennecke wrote:
This patch fixes the gcc.dg/c99-stdint-5.c and gcc.dg/c99-stdint-6.c
excess error failures.
FYI, some of the problems with the c99-stdint tests are related to the
stdint.h implementation in use. For example, some types in AVR-Libc's
stdint.h are not defined in the way t
Denis Chertykov schrieb:
Georg-Johann Lay:
PR52543 required to represent a load from non-generic address spaces as UNSPEC
instead of as MEM to avoid a gross code bloat.
http://gcc.gnu.org/PR52543
lower-subreg's cost model is still broken: It assumes that any loads from MEM
are fro
Denis Chertykov wrote:
Georg-Johann wrote:
Denis Chertykov wrote:
Georg-Johann Lay wrote:
PR52543 required to represent a load from non-generic address spaces as
UNSPEC
instead of as MEM to avoid a gross code bloat.
http://gcc.gnu.org/PR52543
lower-subreg's cost model is still broke
avr-gcc compiles code like
void f (int, int);
void f_or (int x)
{
f (x, x | 42);
}
to
f_or:
ldi r22,lo8(42) ; 15*movhi/5[length = 2]
ldi r23,0
or r22,r24 ; 6iorhi3/1[length = 2]
or r23,r25
rjmp f
but this is more efficient:
f_or:
movw
As already discussed, this patch removes the -mshort-calls command option from
avr-gcc.
Ok to apply?
If the change is on order, changes to wwwdocs will follow, i.e. deprecate the
option in 4.7 and tell it is removed in the 4.8 caveats.
Johann
* doc/invoke.texi (AVR Options): Remove -ms
Oleg Endo wrote:
Weddington, Eric wrote:
Georg-Johann Lay wrote:
As already discussed, this patch removes the -mshort-calls command option
from avr-gcc.
Ok to apply?
Ok to apply, but...
If the change is on order, changes to wwwdocs will follow, i.e. deprecate
the option in 4.7 and tell it
Joerg Wunsch wrote:
As Oleg Endo wrote:
I think it's more user friendly to
first warn and then do.
The problem is that this option would better not have existed straight
from the beginning. When using it, the compiler is at the risk of
generating code that fails to link later, because the re
Applied the following changes to 4.7/4.8 release notes caveats.
Index: htdocs/gcc-4.7/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.127
retrieving revision 1.128
diff -u -p -r1.127 -
avr_extra_arch_macro is not really needed, it just holds
avr_current_device->macro.
Thus, this tiny tidy up.
Ok for trunk?
Johann
* config/avr/avr-arch.h (avr_extra_arch_macro): Remove prototype.
* config/avr/avr.c (avr_extra_arch_macro): Remove variable.
(avr_option_o
This documents __AVR_ARCH__ built-in macro that was missing up to now.
Pointer to --help=target is removed because the documentation of -mmcu= is
complete.
Ok to apply?
Johann
* doc/invoke.texi (AVR Options): Document __AVR_ARCH__.
Note __AVR___ is not defined for cores.
Ralf Corsepius schrieb:
I've applied the patch below to trunk and gcc-4.7-branch.
It contains 2 RTEMS specific cleanups which have been in use for
avr-rtems for quite a while.
Ralf
2012-10-26 Ralf Corsépius
* config/avr/rtems.h (TARGET_OS_CPP_BUILTINS): Remove
__USE_INIT_
http://gcc.gnu.org/viewcvs?view=revision&revision=192878
Applied as obvios.
Johann
PR target/55034
* config/avr/avr.c (avr_out_lpm): Remove unused regno_dest.
This is a fix of a wrong warning for a bas ISR name. The assumption was that
if DECL_ASSEMBLER_NAME is set, it would always starts with a *.
This is not the case for LTO compiler where the assembler name is the plain
name of the function (except an assembler name is set).
Thus, do a more res
Am 12/05/2013 04:09 PM, schrieb Richard Biener:
On Thu, Dec 5, 2013 at 3:53 PM, Georg-Johann Lay wrote:
This is a fix of a wrong warning for a bas ISR name. The assumption was
that if DECL_ASSEMBLER_NAME is set, it would always starts with a *.
This is not the case for LTO compiler where the
Am 12/06/2013 10:32 AM, schrieb Richard Biener:
On Thu, Dec 5, 2013 at 4:38 PM, Georg-Johann Lay wrote:
Am 12/05/2013 04:09 PM, schrieb Richard Biener:
On Thu, Dec 5, 2013 at 3:53 PM, Georg-Johann Lay wrote:
This is a fix of a wrong warning for a bas ISR name. The assumption was
that if
Am 12/05/2013 04:09 PM, schrieb Richard Biener:
On Thu, Dec 5, 2013 at 3:53 PM, Georg-Johann Lay wrote:
This is a fix of a wrong warning for a bas ISR name. The assumption was
that if DECL_ASSEMBLER_NAME is set, it would always starts with a *.
This is not the case for LTO compiler where the
This works around an assumption in optabs, namely that if a widening-mul insn
is available but no mul3 insn, then the widening multiplication insn is
preferred over expanding the multiply as a libcall.
The problem occurs only if !AVR_HAVE_MUL, so I added that condition to
respective mulsidi3
Hi, committed this patchlet that fixes a test case.
Johann
* gcc.target/avr/progmem-error-1.cpp: Fix location of the
expected diagnostic.
Index: gcc.target/avr/progmem-error-1.cpp
===
--- gcc.target/avr/progmem-erro
Hi,
r276985 broke avr because it removed PARAM_ALLOW_STORE_DATA_RACES from
--params. The patch fixes that by using flag_store_data_races = 1 instead.
Ok to apply?
Johann
* config/avr/avr.c (avr_option_override): Fix broken build
introduced by r276985.
Index: config/avr/avr.c
Hi, for families avrxmega5/7 after ELPM the reset of RAMPZ to
zero was missing in some situations due to shortcut-return in
avr_out_lpm which which bypassed that reset.
Ok to apply and backport?
Johann
PR target/86040
* config/avr/avr.c (avr_out_lpm): Do not shortcut-return.
In
Am 10/17/19 um 1:22 PM schrieb Eric Botcazou:
r276985 broke avr because it removed PARAM_ALLOW_STORE_DATA_RACES from
--params. The patch fixes that by using flag_store_data_races = 1 instead.
Note that you'll unconditionally override the user, unlike the original code.
You're right. What ab
Hi, this fixes some FAILs for small targets, fixed or skipped by
size32plus, double64[plus] etc.
Ok to apply?
Johann
Fix some fallout for small targets.
* gcc.c-torture/execute/20190820-1.c:
Add dg-require-effective-target int32plus.
* gcc.c-torture/execute/pr8
Here is some more cases fixed for small targets for noise reduction.
Ok to apply?
Johann
gcc/testsuite/
Fix some fallout for small targets.
PR testsuite/52641
* gcc.dg/torture/pr86034.c: Use 32-bit base type for a bitfield of
width > 16 bits.
* gcc.dg/to
On Fri, 11 Dec 2020 at 20:32, Jeff Law wrote:
I'm definitely curious about the testing setup and whether or not it can
be replicated into our Jenkins setup.
Hi, Jeff.
The gcc testsuite setup is described in the readme of avrtest:
https://sourceforge.net/p/winavr/code/HEAD/tree/trunk/avrtest/
ce that he can step in on this stuff, but I'm also hesitant to let
patches linger for too long.
I don't think I have seen mails from Denis since then (more than
eleven months).
Do we need to get a new maintainer for AVR in place? Any nominations?
I nominate Georg-Johann Lay as the obviou
Am 10.11.22 um 15:08 schrieb Paul Iannetta:
On Thu, Nov 03, 2022 at 02:38:39PM +0100, Georg-Johann Lay wrote:
[PATCH v3] c++: parser - Support for target address spaces in C++
2. Will it work with compound literals?
===
Currently, the following C code
Am 14.11.22 um 18:55 schrieb Jason Merrill:
On 11/10/22 06:40, Georg-Johann Lay wrote:
Am 10.11.22 um 15:08 schrieb Paul Iannetta:
On Thu, Nov 03, 2022 at 02:38:39PM +0100, Georg-Johann Lay wrote:
[PATCH v3] c++: parser - Support for target address spaces in C++
2. Will it work with
Am 16.11.19 um 18:36 schrieb Jeff Law:
On 11/8/19 9:19 AM, Georg-Johann Lay wrote:
Hi,
this patch adds support for a few more AVR devices. Because the offset
where flash is seen in RAM deviates from the settings for the family
(and hence also from the linker script defaults), a new field in
Am 06.11.19 um 23:32 schrieb Jeff Law:
On 10/31/19 3:55 PM, Georg-Johann Lay wrote:
Hi, this adds the possibility to enable IEEE compatible double
and long double support in avr-gcc.
It supports 2 configure options
--with-double={32|64|32,64|64,32}
--with-long-double={32|64|32,64|64,32|double
Hi,
This patch adds support for devices that can access flash memory
by LD* instructions, hence there is no need to put .rodata in RAM.
The default linker script for the new multilib versions already
supports this feature, it's similar to avrtiny, cf.
https://sourceware.org/PR21472
This patch
Ping #1
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00096.html
On 02.06.2017 09:53, Georg-Johann Lay wrote:
Hi,
this small addition improves costs of PARALLELs in
rtlanal.c:seq_cost(). Up to now, these costs are
assumed to be 1 which gives gross inexact costs for,
e.g. divmod which is
On 12.06.2017 08:30, Pitchumani Sivanupandi wrote:
On Friday 09 June 2017 03:59 PM, Georg-Johann Lay wrote:
Hi,
This patch adds support for devices that can access flash memory
by LD* instructions, hence there is no need to put .rodata in RAM.
The default linker script for the new multilib
Hi,
Since PR71151 we have jump-tables in .text so that branches
crossing the tables have longer offsets that needed.
This moves jump-tables out of test again, but not into
.progmem.gcc_sw_tables like before PR71151, but into
the currently unused but existing .jumptables.
Since PR63223 there is
Ping #2
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00096.html
On 02.06.2017 09:53, Georg-Johann Lay wrote:
> Hi,
>
> this small addition improves costs of PARALLELs in
> rtlanal.c:seq_cost(). Up to now, these costs are
> assumed to be 1 which gives gross inexact costs for
Ping #1
http://gcc.gnu.org/ml/gcc-patches/2017-06/msg01029.html
Georg-Johann Lay schrieb:
Hi,
Since PR71151 we have jump-tables in .text so that branches
crossing the tables have longer offsets that needed.
This moves jump-tables out of test again, but not into
.progmem.gcc_sw_tables like
Ping #2
http://gcc.gnu.org/ml/gcc-patches/2017-06/msg01029.html
On 14.06.2017 14:03, Georg-Johann Lay wrote:
Hi,
Since PR71151 we have jump-tables in .text so that branches
crossing the tables have longer offsets that needed.
This moves jump-tables out of test again, but not into
Ping #3
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00096.html
On 02.06.2017 09:53, Georg-Johann Lay wrote:
> Hi,
>
> this small addition improves costs of PARALLELs in
> rtlanal.c:seq_cost(). Up to now, these costs are
> assumed to be 1 which gives gross inexact costs for
On 28.06.2017 22:18, Wilco Dijkstra wrote:
Georg-Johann Lay wrote:
@@ -5300,6 +5300,9 @@ seq_cost (const rtx_insn *seq, bool spee
set = single_set (seq);
if (set)
cost += set_rtx_cost (set, speed);
+ else if (INSN_P (seq)
+ && PARALLEL ==
This adds AVR improvements to v8 Release Notes.
Ok?
Johann
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,v
retrieving revision 1.22
diff -r1.22 changes.html
179c179,240
<
---
> AVR
>
>
> The
On 14.12.2017 21:44, Gerald Pfeifer wrote:
Hi Johann,
On Wed, 13 Dec 2017, Georg-Johann Lay wrote:
This adds AVR improvements to v8 Release Notes.
that's quite impressive a set of improvements!
Index: changes.html
===
This PR skips saving of any registers in main.
Attribute OS_main can do this as well, however we can just drop
any saves / restores in all optimized compilation -- not even
the test suite needs these saves.
The feature can still be switched off by new -mno-OS_main
Ok for trunk?
gcc/
D
On 08.01.2018 18:39, Denis Chertykov wrote:
2018-01-08 20:19 GMT+04:00 Georg-Johann Lay :
This PR skips saving of any registers in main.
Attribute OS_main can do this as well, however we can just drop
any saves / restores in all optimized compilation -- not even
the test suite needs these
This patch adds a bit more the the avr section of the v8 release notes.
Ok?
Johann
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,v
retrieving revision 1.25
diff -r1.25 changes.html
240a241,246
>
>
Added the following avr specific test cases for the already fixed PR83801.
Johann
PR c/83801
PR c/83729
* gcc.target/avr/torture/pr83729.c: New test.
* gcc.target/avr/torture/pr83801.c: New test.
Index: gcc.target/avr/torture/pr83729.c
==
This obvious patch adds more handling of AVR_TINY, mostly by
applying "!avr_tiny" target filter of by defaulting to
generic address-space if __flash is not available.
Committed as https://gcc.gnu.org/r256690
Johann
* gcc.target/avr/progmem.h (pgm_read_char): Handle AVR_TINY.
* g
On 18.01.2018 16:08, Sebastian Perta wrote:
Hello,
I am interested in implementing a new pass in gcc to merge identical
sequences of code in GCC to be used mainly for RL78.
The commercial RL78 compilers have such algorithms implemented and they make
quite good use of it.
Opportunities arise from
Applied the following patch that moves disabling of
-fno-disable-null-pointer-checks to a different place so that it can be
overwritten on the command-line (as opposed to TARGET_OVERRIDE_OPTIONS).
This allows some more test cases to pass that set
-fdisable-null-pointer-checks.
gcc/
*
Again. This change adjusts more tests to work with int16. For tests
that cannot be easily adjusted, added int32plus or size32plus filters.
https://gcc.gnu.org/r257327
Johann
gcc/testsuite/
PR testsuite/52641
* gcc.c-torture/execute/pr81913.c: Use types that also work for int1
This patch reduces avr testsuite fallout for some cases that cannot be
easily adjusted or where int32plus et al. is not the right filter.
Moreover, target-supports.exp reads:
# Return 1 if according to target_info struct and explicit target list
# target disables -fdelete-null-pointer-checks.
Again. This change adjusts more tests to work with int16. For tests
that cannot be easily adjusted, added int32plus or size32plus filters.
Committed as 257333.
Johann
gcc/testsuite/
PR testsuite/52641
* gcc.c-torture/execute/pr83362.c: Make work for int16.
* gcc.dg/Wsi
This patch fixed the wrong pre-increment of .dtors addresses to a
post-increment. The first .dtor was bypassed and the last access read beyond
__dtors_end.
Installed as obvious: http://gcc.gnu.org/r216550
Johann
* config/avr/lib1funcs.S (__do_global_dtors): Fix wrong code
in
This addendum to PR63223 reverses the order in which __do_global_dtors
traverses .dtors: The order is from first to last so that it matches trunk
implementation and is inverse direction as __do_global_ctors (which is from
last .ctors entry to first).
Applied as http://gcc.gnu.org/r216551
Joh
This no-op change fixed typos and restored coding rules as obvious like:
spaces around operators, space before opening parentheses, wrapping long lines,
indentation rules, trailing blanks, etc...
http://gcc.gnu.org/r216592
Johann
gcc/
* config/avr/avr.c: Fix GNU coding rules and typo
This optimization makes most sign-extensions one instruction shorter in the
case when the source register may be clobbered and the register numbers are
different. Source and destination may overlap.
Ok for trunk?
Johann
gcc/
* config/avr/avr.md (extendqihi2, extendqipsi2, extendqisi
Am 10/23/2014 08:16 PM schrieb Denis Chertykov:
This optimization makes most sign-extensions one instruction shorter in the
case when the source register may be clobbered and the register numbers are
different. Source and destination may overlap.
Ok for trunk?
Johann
gcc/
* config/av
This is a fix for unrecognizable insn ICE where the push expander generated
(subreg(mem)) for non-generic address-space locations.
Instead of loading byte-wise and legitimizing such expressions, it's easier and
results in better code when we load such MEMs in one chunk.
Ok to apply?
Johann
Am 04/16/2015 um 11:28 AM schrieb Senthil Kumar Selvaraj:
On Thu, Apr 16, 2015 at 11:02:05AM +0200, Georg-Johann Lay wrote:
Am 04/16/2015 um 08:43 AM schrieb Senthil Kumar Selvaraj:
This patch fixes PR 65657.
The following artifact appears to be PR63633.
I did see that one - unfortunately
...and the sketch against 4.9
Index: config/avr/avr.c
===
--- config/avr/avr.c (revision 221321)
+++ config/avr/avr.c (working copy)
@@ -287,6 +287,94 @@ avr_to_int_mode (rtx x)
}
+static void
+avr_rest_of_handle_expand_xload (vo
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