[PATCH] RISC-V: Support the ins "rol" with immediate operand

2022-11-27 Thread Feng Wang
From: wangfeng There is no Immediate operand of ins "rol" accroding to the B-ext, so the immediate operand should be loaded into register at first. But we can convert it to the ins "rori" or "roriw", and then one immediate load ins can be reduced. Please refer to the following use cases: unsigne

Re: Re: [PATCH] RISC-V: Support the ins "rol" with immediate operand

2022-11-28 Thread Feng Wang
on 2022-11-28 23:39  Jeff Law wrote: > > >On 11/27/22 19:14, Feng Wang wrote: >> From: wangfeng >> >> There is no Immediate operand of ins "rol" accroding to the B-ext, >> so the immediate operand should be loaded into register at first. >> But we

[PATCH v2 0/1] RISC-V: Optimze the reverse conditions of rotate shift

2022-12-06 Thread Feng Wang
The first patch is https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607332.html. Accroding to Jeff's suggestion I added some conditions when reverse the rotate shift during RTL expansion and RTL optimization. wangfeng (1): RISC-V: Optimze the reverse conditions of rotate shift gcc/conf

[PATCH v2 1/1] RISC-V: Optimze the reverse conditions of rotate shift

2022-12-06 Thread Feng Wang
From: wangfeng There is no Immediate operand of ins "rol" according to the B-ext, so the immediate operand should be loaded into register at first. But we can convert it to the ins "rori" or "roriw", and then one immediate load ins can be reduced. So I added some conditions when reverse the rotat

[PATCH] RISC-V: Optimize load memory data in rv64

2023-03-23 Thread Feng Wang
This patch optimize load one byte or halfword from memory in rv64. Please refer to the following test case for loading one byte. int sextb32_memory(int* x) { return (*x << 24) >> 24; } The build flags are "-march=rv64g -mabi=lp64d -O2" The current compilation results are as follows, slliw a0,a0,0

[PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64

2023-03-23 Thread Feng Wang
This patch optimize the combine processing for sext.b/h in rv64. Please refer to the following test case, int sextb32(int x) { return (x << 24) >> 24; } The rtl expression is as follows, (insn 6 3 7 2 (set (reg:SI 138) (ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0) (co

Re: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64

2023-03-23 Thread Feng Wang
Hi Juzhe, Thank you for your reply, I'm really doing some optimization work right now. I am very interested in the question you have raised, and I will take the time to try to optimize it. I hope I can communicate with you and learn from you more in the future. Thanks.

Re: Re: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64

2023-03-26 Thread Feng Wang
HO) is to walk >through the optimizer pipeline to see where it can potentially be >eliminated.  In general, the earlier in the optimizer pipeline the >extension can be eliminated, the better. > >Jeff Hi Jeff,Do you think my patch modification is suitable?What else needs to be improved? Thanks. Feng Wang

[PATCH] RISC-V:Auto vect for vector bf16

2024-10-16 Thread Feng Wang
-vect.c: New test. Signed-off-by: Feng Wang --- gcc/config/riscv/vector-bfloat16.md | 144 -- .../riscv/rvv/autovec/vfncvt-auto-vect.c | 19 +++ .../riscv/rvv/autovec/vfwcvt-auto-vect.c | 19 +++ .../riscv/rvv/autovec/vfwmacc-auto-vect.c | 14 ++ 4 files

[PATCH v2] RISC-V:Auto vect for vector-bfloat16

2024-10-18 Thread Feng Wang
/ChangeLog: * gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c: New test. * gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c: New test. * gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c: New test. Signed-off-by: Feng Wang --- gcc/config/riscv/autovec-opt.md

[PATCH] PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error

2024-11-19 Thread Feng Wang
This patch fix the wrong condition for RVVMF2BF. It should be TARGET_VECTOR_ELEN_BF_16. gcc/ChangeLog: PR target/117669 * config/riscv/vector-iterators.md: Signed-off-by: Feng Wang --- gcc/config/riscv/vector-iterators.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH] RISC-V:Fix wrong condition for vector-bfloat16

2024-11-19 Thread Feng Wang
This patch fix the wrong condition for RVVMF2BF. It should be TARGET_VECTOR_ELEN_BF_16. gcc/ChangeLog: * config/riscv/vector-iterators.md: Modify condition. Signed-off-by: Feng Wang --- gcc/config/riscv/vector-iterators.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

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