Building the ASAN for the n32 MIPS ABI currently fails, due to a few reasons:
- defined(__mips64), which is set solely based on the architecture type
(32-bit/64-bit), was still used in some places.
Therefore, defined(__mips64) is swapped with SANITIZER_MIPS64, which takes the
ABI into account as
When we use cross toolchains, in which the GCC libraries are not installed
within a designated system root, the shared sanitizer libraries link against
libstdc++.so* within the same libraries. This directory, however, is not in
RPATH, so attempting to build a dynamically linked application with
Fix kernel_stat structure size for non-Android 32-bit Mips.
LLVM currently has this value for the kernel_stat structure size,
as per compiler-rt/lib/sanitizer-common/sanitizer_platform_limits_posix.h.
This also resolves one of the build issues for non-Android 32-bit Mips.
libsanitizer/ChangeLo
Building the ASAN for the n32 MIPS ABI currently fails, due to a few reasons:
- defined(__mips64), which is set solely based on the architecture type
(32-bit/64-bit),
was still used in some places. Therefore, defined(__mips64) is swapped with
SANITIZER_MIPS64,
which takes the ABI into account a
When we use cross toolchains, in which the GCC libraries are not installed
within a designated system root, the shared sanitizer libraries link against
libstdc++.so* within the same libraries. This directory, however, is not in
RPATH,
so attempting to build a dynamically linked application with
Thanks Xi. Forgive me as I'm not that familiar with the coding standards
when submitting patches for a review.
Here is the updated version of the patch.
Fix kernel_stat structure size for non-Android 32-bit Mips.
LLVM currently has this value for the kernel_stat structure size,
as per compiler-rt
Thanks Xi. Forgive me as I'm not that familiar with the coding standards
when submitting patches for a review.
Here is the updated version of the patch.
Building the ASAN for the n32 MIPS ABI currently fails, due to a few reasons:
- defined(__mips64), which is set solely based on the architecture
On Saturday, June 11, 2022 2:03 PM, Xi wrote:
> Just tried TSAN_SUPPORTED=yes with asynchronous unwind tables enabled,
> but I got some strange test failures for tls_race.c:
>
> FAIL: c-c++-common/tsan/tls_race.c -O0 output pattern test
> Output was:
> ThreadSanitizer: CHECK failed: tsan_platfo
flag_asynchronous_unwind_tables = 1;
From: Xi Ruoyao
Sent: Tuesday, July 5, 2022 3:54 AM
To: Dimitrije Milosevic ;
gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic
Subject: Re: [PATCH] Mips: Enable asynchronous unwind tables with both ASAN and
TSAN
On Mon, 2022-07-04 at 14:28 +, Di
Ping. :)
I think this is good to go. Unfortunately, I do not have commit access, so if
anyone
can commit it, that would be great!
From: Dimitrije Milosevic
Sent: Friday, July 1, 2022 4:25 PM
To: Xi Ruoyao ; gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic ; Richard Sandiford
Subject: Re: Mips
1
-# if defined(__mips64)
+# if defined(__mips64) && _MIPS_SIM == _ABI64
#define SANITIZER_MIPS32 0
#define SANITIZER_MIPS64 1
# else
--
2.25.1
From: Richard Sandiford
Sent: Monday, July 4, 2022 1:23 PM
To: Xi Ruoyao via Gcc-patches
Cc: Dimitrije Milosevic ; Xi Ruoyao
; Djordje
s
will be working properly. As for this change, I'm not sure what should be done?
Should this be committed now, while the LLVM change is cherry-picked once it's
committed.
Best regards,
Dimitrije Milosevic
From: Hans-Peter Nilsson
Sent: Saturday, July 9, 2022 4:44 PM
To: Xi Ruoyao
Cc:
an Glibc (it's PR
> 106136 in GCC bugzilla).
I might be able to, but no promises. :)
From: Xi Ruoyao
Sent: Wednesday, July 13, 2022 4:38 AM
To: Dimitrije Milosevic ; Hans-Peter Nilsson
Cc: Djordje Todorovic ; gcc-patches@gcc.gnu.org
Subject: Re: Mips: Fix kernel_stat structure size
2bfb0fcb51510f22723c8cdfefe [Sanitizer][MIPS] Fix stat struct size for the O32
ABI.
Signed-off-by: Dimitrije Milosevic .
---
.../sanitizer_common/sanitizer_platform_limits_posix.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/libsanitizer/sanitizer_common
Gentle ping, requiring someone to push this change, as I do not have commit
access. :)
From: Dimitrije Milosevic
Sent: Monday, July 25, 2022 8:55 AM
To: gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic ; xry...@xry111.site
Subject: [PATCH] libsanitizer: Cherry-pick 2bfb0fcb51510f22723c8cdfefe
> Do you know someone very familiar with MIPS and GCC and capable as a
> port maintainer? An active MIPS port maintainer will make the situation
> better.
Sadly, no. I agree it would make things easier.
From: Xi Ruoyao
Sent: Wednesday, July 27, 2022 8:43 AM
To: Dimitrije Milosev
Gentle ping, requiring someone to push the change. :)
From: Dimitrije Milosevic
Sent: Monday, July 25, 2022 8:55 AM
To: gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic ; xry...@xry111.site
Subject: [PATCH] libsanitizer: Cherry-pick 2bfb0fcb51510f22723c8cdfefe from
upstream
Thanks Martin! I'm sending out the output from git format-patch as an
attachment to this email.
From: Martin Liška
Sent: Thursday, July 28, 2022 3:48 PM
To: Dimitrije Milosevic ;
gcc-patches@gcc.gnu.org
Cc: ma...@embecosm.com ; Djordje Todorovic
; jos...@codesourcery.com
Subjec
The following patch enables TSAN for mips64, on which it is supported.
Signed-off-by: Dimitrije Milosevic .
libsanitizer/ChangeLog:
* configure.tgt: Enable
TSAN for 64-bit ABIs.
---
libsanitizer/configure.tgt | 4
1 file changed, 4 insertions(+)
diff --git a/libsanitizer
Gentle ping. :)
From: Dimitrije Milosevic
Sent: Friday, July 29, 2022 12:38 PM
To: gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic ; xry...@xry111.site
; mask...@google.com
Subject: [PATCH] Mips: Enable TSAN for 64-bit ABIs
The following patch enables TSAN for mips64, on which it is supported
nested
loops.
Additionally, when bumping up the register pressure cost, the number of
invariants should also be
considered, in addition to the number of candidates.
Dimitrije Milosevic (2):
ivopts: Revert computation of address cost complexity.
ivopts: Consider number of invariants when calcu
-ivopts.cc (compute_symbol_and_var_present): Reintroduce.
(compute_min_and_max_offset): Likewise.
(get_address_cost): Revert
complexity calculation.
Signed-off-by: Dimitrije Milosevic
---
gcc/tree-ssa-address.cc | 2 +-
gcc/tree-ssa-address.h | 2 +
gcc/tree-ssa-loop
(ivopts_estimate_reg_pressure): Adjust.
Signed-off-by: Dimitrije Milosevic
---
gcc/tree-ssa-loop-ivopts.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/tree-ssa-loop-ivopts.cc b/gcc/tree-ssa-loop-ivopts.cc
index d53ba05a4f6..9d0b669d671 100644
--- a/gcc/tree-ssa
c1$f20,-8($2)
lwc1$f12,0($25)
maddf.s $f11,$f1,$f12
bne $2,$20,.L93
swc1$f11,-4($2)
...
= After f9f69dd =
Notice the additional instructions used for index calculation, due to
unoptimal candidate selection.
Regards,
Dimitrije
rd Biener
Sent: Tuesday, October 25, 2022 1:07 PM
To: Dimitrije Milosevic
Cc: gcc-patches@gcc.gnu.org ; Djordje Todorovic
Subject: Re: [PATCH 2/2] ivopts: Consider number of invariants when calculating
register pressure.
On Fri, Oct 21, 2022 at 3:57 PM Dimitrije Milosevic
wrote:
>
>
s to compensate
the lack of other addressing modes somehow. If complexities for both of
those are equal to 0, in cases where complexities decide which candidate is
to be chosen, a more complex candidate may be picked.
Regards,
Dimitrije
From: Jeff Law
Sent: Friday, October 28, 2022 1:02 AM
To: D
n.
Would love to hear your thoughts.
[0] https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604304.html
Regards,
Dimitrije
From: Richard Biener
Sent: Friday, October 28, 2022 9:00 AM
To: Dimitrije Milosevic
Cc: Jeff Law ; gcc-patches@gcc.gnu.org
; Djordje Todorovic
Subject: Re: [PATCH
l
Regards,
Dimitrije
From: Richard Biener
Sent: Friday, October 28, 2022 9:38 AM
To: Dimitrije Milosevic
Cc: gcc-patches@gcc.gnu.org ; Djordje Todorovic
Subject: Re: [PATCH 2/2] ivopts: Consider number of invariants when calculating
register pressure.
On Tue, Oct 25, 2022 at 3:00 PM
'll take a deeper look into the candidate selection algorithm then. Will
get back to you.
Regards,
Dimitrije
From: Jeff Law
Sent: Tuesday, November 1, 2022 7:46 PM
To: Richard Biener; Dimitrije Milosevic
Cc: gcc-patches@gcc.gnu.org; Djordje Todorovic
ds,
Dimitrije
From: Richard Biener
Sent: Monday, November 7, 2022 2:35 PM
To: Dimitrije Milosevic
Cc: Jeff Law ; gcc-patches@gcc.gnu.org
; Djordje Todorovic
Subject: Re: [PATCH 1/2] ivopts: Revert computation of address cost complexity.
On Wed, Nov 2, 2022 at 9:40 AM Dimitrije Milosevic
wro
m not sure how to feel about merging complexity into the cost part
of an address cost, though.
> If it's really only about the "complexity" value then each
> compensation step should
> add to the complexity?
That could be the way to go. Also worth verifying is that we compensate f
Enable asynchronous unwind tables with both ASAN and TSAN for correct
back-trace.
LLVM currently enables asynchronous unwind tables for: ASAN, HWSAN, TSAN, MSAN,
and DFSAN.
HWSAN is currently available only on AArch64, while MSAN and DFSAN are not
available at all.
Also, LLVM checks is '-ffreest
&& (flag_sanitize & SANITIZE_THREAD)))
&& !global_options_set.x_flag_asynchronous_unwind_tables)
flag_asynchronous_unwind_tables = 1;
---
From: Xi Ruoyao
Sent: Saturday, May 28, 2022 12:30 PM
To: Dimitrije Milosevic ;
gcc-patches@gcc.gnu.o
Fix the ASAN shadow offset hook for the n32 ABI.
gcc/ChangeLog:
* config/mips/mips.cc (mips_asan_shadow_offset): Reformat
to handle the N32 ABI.
* config/mips/mips.h (SUBTARGET_SHADOW_OFFSET): Remove
the macro, as it is not needed anymore.
---
gcc/config/mips/mi
Correct, it should be committed very soon.
From: Xi Ruoyao
Sent: Tuesday, June 7, 2022 10:17 AM
To: Dimitrije Milosevic ;
gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic
Subject: Re: [PATCH] Mips: Fix the ASAN shadow offset hook for the n32 ABI
On Mon, 2022-06
Definitely, a patch is on the way.
From: Xi Ruoyao
Sent: Tuesday, June 7, 2022 10:20 AM
To: Dimitrije Milosevic ;
gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic
Subject: Re: [PATCH] Mips: Enable asynchronous unwind tables with both ASAN and
TSAN
On Mon, 2022
36 matches
Mail list logo
