Re: [PATCH] Support bitfields in Wodr machinery (PR lto/85405).

FIELD (f2)) >> { >> warn_odr (t1, t2, f1, f2, warn, warned, >> - G_ ("one field is bitfield while other is not >> ")); >> + G_("one field is bitfield while other is not&quo

Re: [PATCH] Support bitfields in Wodr machinery (PR lto/85405).

On 19 April 2018 at 10:37, Martin Liška wrote: > On 04/18/2018 10:51 PM, Christophe Lyon wrote: >> Hi, >> >> >> On 17 April 2018 at 10:19, Jan Hubicka wrote: >>>> On 04/17/2018 08:58 AM, Jakub Jelinek wrote: >>>>> On Tue, Apr 17, 2018 at 07:3

Re: [PATCH] Fix aarch64 ILP32 ICE with vaarg gimplified code

On 26 April 2018 at 14:09, Richard Biener wrote: > > Seen by Christophe Lyon, verified with a cross that this fixes the > issue. > > aarch64 people, can you please test & commit this? > As I have just written in bugzilla, this patch avoids an ICE when compiling newlib&#x

Re: [PATCH] Fix aarch64 ILP32 ICE with vaarg gimplified code

On 26 April 2018 at 15:41, Richard Biener wrote: > On Thu, 26 Apr 2018, Christophe Lyon wrote: > >> On 26 April 2018 at 14:09, Richard Biener wrote: >> > >> > Seen by Christophe Lyon, verified with a cross that this fixes the >> > issue. >> > &

[RFC] Configure and testsuite updates for ARM FDPIC target

Hello, I am preparing the submission of a patch series to support the FDPIC ABI for Linux on ARM. During development, we internally used arm-linux-uclibceabi as target name, but I had to change it to handle feedback when I submitted the binutils patches. These have been merged to binutils ma

Re: [PATCH] Add constant folding support for next{after,toward}{,f,l} (PR libstdc++/85466)

and I thought it was a matter of adding the c99_runtime effective target, as done in the attached patch. Even if newlib gets a fix for this, the effective target will still claim c99_runtime is not supported on such targets Thanks, Christophe > Thanks, > - Tom gcc/testsuite/ChangeLo

Re: Gimple FE support for internal functions

On 17 May 2018 at 10:25, Richard Sandiford wrote: > This patch gets the gimple FE to parse calls to internal functions. > The only non-obvious thing was how the functions should be written > to avoid clashes with real function names. One option would be to > go the magic number of underscores rou

[ARM/FDPIC 04/21] [ARM] FDPIC: Add support for FDPIC for arm architecture

into account whether it is a pointer to data or to a function, because different relocations are needed. 2018-XX-XX Christophe Lyon Mickaël Guêné * config/arm/arm-c.c (__FDPIC__): Define new pre-processor macro in FDPIC mode. * config/arm/arm-pro

[ARM/FDPIC 02/21] [ARM] FDPIC: Handle arm*-*-uclinuxfdpiceabi in configure scripts

. 2018-XX-XX Christophe Lyon * config/futex.m4: Handle *-uclinux*. * config/tls.m4 (GCC_CHECK_TLS): Likewise. * gcc/config.gcc: Handle *-*-uclinuxfdpiceabi. * libatomic/configure.tgt: Handle arm*-*-uclinux*. * libgcc/config.host: Handle

[ARM/FDPIC 07/21] [ARM] FDPIC: Avoid saving/restoring r9 on stack since it is RO

2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_compute_save_reg0_reg12_mask): Handle FDPIC. (thumb1_compute_save_core_reg_mask): Likewise. Change-Id: Ib534cf91704cdc740867b46a8fe45fda27894562 diff --git a/gcc/config/arm/arm.c b

[ARM/FDPIC 12/21] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp

2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. * config/arm/arm.md (load_tp_soft_fdpic): New pattern. (load_tp_soft): Disable in FDPIC mode. Change-Id: I0a2e3466c9afb869ad8e844083ad178de014658e diff

[ARM/FDPIC 11/21] [ARM] FDPIC: Add support to unwind FDPIC signal frame

2018-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * unwind-arm-common.inc (ARM_SET_R7_RT_SIGRETURN) (THUMB2_SET_R7_RT_SIGRETURN, FDPIC_LDR_R12_WITH_FUNCDESC) (FDPIC_LDR_R9_WITH_GOT, FDPIC_LDR_PC_WITH_RESTORER) (FDPIC_FUNCDESC_OFFSET

[ARM/FDPIC 00/21] FDPIC ARM for ARM

3f247b81fa7de789edc4d9 [5] https://git.qemu.org/?p=qemu.git;a=commit;h=e8fa72957419c11984608062c7dcb204a6003a06 [6] https://git.linaro.org/people/christophe.lyon/uclibc.git/log/?h=uClibc-0.9.33.2-fdpic-upstream Christophe Lyon (21): [ARM] FDPIC: Add -mfdpic option support [ARM] FDPIC: Handl

[ARM/FDPIC 06/21] [ARM] FDPIC: Add support for c++ exceptions

When restoring a function address, we also have to restore the FDPIC register value (r9). 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * ginclude/unwind-arm-common.h (unwinder_cache): Add reserved5 field. libgcc/ * config/arm/linux-atomic.c

[ARM/FDPIC 01/21] [ARM] FDPIC: Add -mfdpic option support

2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.opt: Add -mfdpic option. Change-Id: Ie5c4ed7434488933de6133186da09cd3ea1291a7 diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index a1286a4..231c1cb 100644 --- a/gcc/config/arm/arm.opt +++ b

[ARM/FDPIC 08/21] [ARM] FDPIC: Fix corner case of weak symbol

When checking the address of a weak symbol in an executable, it is mandatory to use the GOTFUNCDESC scheme so that the address==NULL semantic is valid if the symbol is not present in the final link. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c

[ARM/FDPIC 09/21] [ARM] FDPIC: Add support for taking address of nested function

2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_asm_trampoline_template): Add FDPIC support. (arm_trampoline_init): Likewise. (arm_trampoline_init): Likewise. * config/arm/arm.h (TRAMPOLINE_SIZE): Likewise. Change

[ARM/FDPIC 03/21] [ARM] FDPIC: Force FDPIC related options unless -mno-fdpic is provided

ing is not supported. We should also apply the same behavior for -Wl,-Ur as for -r, but I couldn't find how to describe that in the specs fragment. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config.gcc: Handle arm*-*-uclinuxfdpiceabi. * con

[ARM/FDPIC 10/21] [ARM] FDPIC: Implement legitimize_tls_address_fdpic

Support additional relocations: TLS_GD32_FDPIC, TLS_LDM32_FDPIC, and TLS_IE32_FDPIC. We do not support the GNU2 TLS dialect. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (tls_reloc): Add TLS_GD32_FDPIC, TLS_LDM32_FDPIC and TLS_IE32_FDPIC

[ARM/FDPIC 05/21] [ARM] FDPIC: Fix __do_global_dtors_aux and frame_dummy generation

In FDPIC, we need to make sure __do_global_dtors_aux and frame_dummy are referenced by their address, not by pointers to the function descriptors. 2018-XX-XX Christophe Lyon Mickaël Guêné * libgcc/crtstuff.c: Add support for FDPIC. Change-Id

[ARM/FDPIC 15/21] [ARM][testsuite] FDPIC: Skip unsupported tests

43597.c pr43920-2.c * Disable assembler scanning invalid for FDPIC: pr45701-1.c pr45701-2.c stack-red-zone.c * gnu2 TLS dialect is not supported by FDPIC: tlscall.c * Test relies on symbols not generated in FDPIC: data-rel-2.c data-rel-3.c 2018-XX-XX Christophe Lyon Mi

[ARM/FDPIC 16/21] [ARM][testsuite] FDPIC: Adjust scan-assembler patterns.

In FDPIC mode, r9 is saved in addition to other registers, so update the expected patterns accordingly. 2018-XX-XX Christophe Lyon Mickaël Guêné * gcc/testsuite/ * gcc.target/arm/interrupt-1.c: Add scan-assembler pattern for arm*-*-uclinuxfdpiceabi

[ARM/FDPIC 19/21] [ARM][testsuite] FDPIC: Handle *-*-uclinux*

Add *-*-uclinux* to tests that work on this target. 2018-XX-XX Christophe Lyon gcc/testsuite/ * g++.dg/abi/forced.C: Add *-*-uclinux*. * g++.dg/abi/guard2.C: Likewise. * g++.dg/ext/cleanup-10.C: Likewise. * g++.dg/ext/cleanup-11.C: Likewise. * g

[ARM/FDPIC 14/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture

Christophe Lyon Mickaël Guêné libgcc/ * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m architecture. Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 564e4f13..6da6e3d 100644

[ARM/FDPIC 17/21] [ARM][testsuite] FDPIC: Skip v8-m and v6-m tests that currently produce an ICE

v6-M and v8-M are not supported currently in FDPIC mode, it's better to skip the tests. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/testsuite/ * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: Skip on arm*-*-uclinuxfdpiceabi. * gcc.targe

[ARM/FDPIC 13/21] [ARM] FDPIC: Support unwinding across thumb2 signal trampoline

2018-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * unwind-arm-common.inc (FDPIC_T2_LDR_R12_WITH_FUNCDESC) (FDPIC_T2_LDR_R9_WITH_GOT, FDPIC_T2_LDR_PC_WITH_RESTORER): New. (__gnu_personality_sigframe_fdpic): Support Thumb address. (get_eit_entry

[ARM/FDPIC 18/21] [ARM][testsuite] FDPIC: Skip tests that don't work in PIC mode

Some tests fail on arm*-*-uclinuxfdpiceabi because it generates PIC code and they don't support it: skip them. They also fail on arm*-linux* when forcing -fPIC. 2018-XX-XX Christophe Lyon gcc/testsuite/ * gcc.target/arm/eliminate.c: Accept only nonpic targets. * g

[ARM/FDPIC 20/21] [ARM][testsuite] FDPIC: Enable tests on pie_enabled targets

Some tests have the "nonpic" guard, but pass on arm*-*-uclinuxfdpiceabi because it is in PIE mode by default. Rather than adding this target to all these tests, add the "pie_enabled" effective target. 2018-XX-XX Christophe Lyon gcc/testsuite/ * g++.dg/cpp

[ARM/FDPIC 21/21] [ARM][testsuite] FDPIC: Adjust pr43698.c to avoid clash with uclibc.

uclibc defines bswap_32, so use a different name in this test. 2018-XX-XX Christophe Lyon gcc/testsuite/ * gcc.target/arm/pr43698.c (bswap_32): Rename as my_bswap_32. Change-Id: I2591bd911030814331cabf97ee5cf6cf8124b4f3 diff --git a/gcc/testsuite/gcc.target/arm/pr43698.c b

Re: [testsuite patch] add code to arm_thumbX_ok to exercise ABI

On 8 August 2014 02:30, Janis Johnson wrote: > Running an arm-none-eabi test that adds "-mthumb" for a multilib that > uses "-march=armv5te -mfloat-abi=hard" works fine if the test doesn't > have any calls, but if it does then the effective-target checks for > arm_thumb1_ok and arm_thumb2_ok pass

Re: [PATCH][ARM][2/2] Vectorise lroundf, lfloorf, lceilf using the new ARMv8-A vcvt* instructions

Hi Kyrill, I've noticed that the tests you added with this patch fail (scan-tree-dump-times) for the armeb-none-linux-gnueabihf target. Not sure if you want to fix your patch or the tests? Christophe. On 2 September 2014 17:48, Ramana Radhakrishnan wrote: > > > On 02/09/14 16:34, Kyrill Tkacho

Re: [debug-early] reuse variable DIEs and fix their context

Hi, FWIW I saw the same problem on arm* and aarch64 targets. On 4 September 2014 20:34, Aldy Hernandez wrote: > On 09/04/14 11:23, Richard Biener wrote: >> >> On September 4, 2014 7:54:14 PM CEST, Aldy Hernandez >> wrote: >>> >>> I think this merge caused bootstrap failure on Linux/i686 >

[Patch, AArch64] Enable Address sanitizer and UB sanitizer

separately, and should not prevent from adding the functionality since most of them pass. Note that an update of libsanitizer is required, to include at least revision 209641 (which fixes internal_fork for AArch64). OK for trunk? Christophe. 2014-09-05 Christophe Lyon gcc/ * config

Re: [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction

Hi Alan, In my cross-testing I've noticed that your new test: gcc.target/aarch64/simd/int_comparisons_1.c scan-assembler-not not is PASS for targets aarch64-none-elf and aarch64_be-none-elf, but FAIL for aarch64-none-linux-gnu. It seems this is not what you saw in your own validations? Christoph

Re: [Patch,Aarch64] Make frame grow downwards

Ping? The original post is here: http://gcc.gnu.org/ml/gcc-patches/2013-06/msg01588.html Thanks, Christophe. On 28 June 2013 13:41, Christophe Lyon wrote: > Hi, > Following the discussion on > http://gcc.gnu.org/ml/gcc/2013-05/msg00208.html > here is a patch to change the fra

Re: [PATCH] Time profiler - phase 1

On 11 November 2013 18:52, Martin Liška wrote: >>> +2013-10-28 Martin Liska >>> + >>> + * gcc.dg/time-profiler-1.c: New test. >>> + * gcc.dg/time-profiler-2.c: Ditto. >>> + > > Yes, I do have commit right. I will bootstrap the patch, test Inkscape > instrumentation and commit it. >

Re: [Patch ARM-AArch64/testsuite v2 01/21] Neon intrinsics execution tests initial framework.

On 1 October 2014 17:11, Marcus Shawcroft wrote: > On 30 September 2014 15:27, Christophe Lyon > wrote: >> On 10 July 2014 12:12, Marcus Shawcroft wrote: >>> On 1 July 2014 11:05, Christophe Lyon wrote: >>>> * documentation (README) >>>> * dejan

[Patch, testsuite] check if -shared is supported

Is it OK for trunk, and 4.9 (since Jason's patch was also committed to 4.9) ? 2014-10-08 Christophe Lyon * lib/target-supports.exp (check_effective_target_shared): New function. * g++.dg/ipa/devirt-28a.C: Check if -shared is supported. Thanks, Christophe. d

Re: [AArch64] Fix predicate and constraint mismatch in logical atomic operations

On 25 September 2014 21:30, Segher Boessenkool wrote: > On Thu, Sep 25, 2014 at 10:33:17AM -0700, Michael Collison wrote: >> The problem is the "CONST_INT 0", not a large constant. This constant is >> not accepted by the predicate, but is accepted by the constraint. > > Yes, bad choice of words, s

Re: [PATCH] gcc parallel make check

Hi Jakub, On 15 September 2014 18:05, Jakub Jelinek wrote: [...] > # For parallelized check-% targets, this decides whether parallelization > # is desirable (if -jN is used and RUNTESTFLAGS doesn't contain anything > # but optional --target_board or --extra_opts arguments). If desirable, >

Re: [PATCH] gcc parallel make check

On 10 October 2014 16:19, Jakub Jelinek wrote: > On Fri, Oct 10, 2014 at 04:09:39PM +0200, Christophe Lyon wrote: >> my.exp contains the following construct which is often used in the testsuite: >> == >> foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] { &

[committed] Fix comment about RUNTESTFLAGS and parallelization

Hi, After Jakub's pre-approval https://gcc.gnu.org/ml/gcc/2014-10/msg00084.html I have committed the small attached patch as r216147. 2014-10-13 Christophe Lyon * Makefile.in: (check-%): Update comment, as RUNTESTFLAGS no longer impact parallelization. Christophe.

[Patch, testsuite] clear wrap_compile_flags before setting it

stophe 2014-10-17 Christophe Lyon * lib/wrapper.exp ({tool}_maybe_build_wrapper): Clear wrap_compile_flags before setting it. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 29ed3e6..faadd79 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeL

Re: [AARCH64, NEON] Any regression testcase for AARCH64 NEON intrinsics in GCC testsuite?

On 20 October 2014 14:01, Yangfei (Felix) wrote: > Hi, > > I am trying to improve the AARCH64 NEON intrinsics. It seems that we don't > enough testcases for this part in GCC testsuite. > How do you guys test your patch on this part? Any suggestions? Thanks. > Hello, I have written a testsuit

[Patch ARM-AArch64/testsuite v3 00/21] Neon intrinsics executable tests

7;Advanced SIMD (Neon)' instead of 'Neon' Christophe Lyon (21): Advanced SIMD (Neon) intrinsics execution tests initial framework. vaba, vld1 and vshl tests. Add unary operators: vabs and vneg. Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub. Add compari

[Patch ARM-AArch64/testsuite v3 02/21] Add unary operators: vabs and vneg.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/unary_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vneg.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd

[Patch ARM-AArch64/testsuite v3 01/21] Advanced SIMD (Neon) intrinsics execution tests initial framework. vaba, vld1 and vshl tests.

* documentation (README) * dejanu driver (advsimd-intrinsics.exp) * support macros (arm-neon-ref.h, compute-ref-data.h) * Tests for 3 intrinsics: vaba, vld1, vshl 2014-10-21 Christophe Lyon * gcc.target/arm/README.advsimd-intrinsics: New file. * gcc.target/aarch64/advsimd

[Patch ARM-AArch64/testsuite v3 03/21] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/binary_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vand.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vbic.c

[Patch ARM-AArch64/testsuite v3 05/21] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcale.c

[Patch ARM-AArch64/testsuite v3 06/21] Add unary saturating operators: vqabs and vqneg.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqabs.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vqneg.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64

[Patch ARM-AArch64/testsuite v3 08/21] Add vabal tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vabal.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c new file mode 100644 index 000..cd31062 --- /dev/null

[Patch ARM-AArch64/testsuite v3 04/21] Add comparison operators: vceq, vcge, vcgt, vcle and vclt.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcge.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcgt.c

[Patch ARM-AArch64/testsuite v3 07/21] Add binary saturating operators: vqadd, vqsub.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqadd.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vqsub.c: Likewise. diff --git a/gcc/testsuite/gcc.target

[Patch ARM-AArch64/testsuite v3 10/21] Add vabdl tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vabdl.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c new file mode 100644 index 000..28018ab --- /dev/null

[Patch ARM-AArch64/testsuite v3 16/21] Add vdup and vmov tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c new file mode 100644 index 000..b5132f4

[Patch ARM-AArch64/testsuite v3 12/21] Add vaddl tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vaddl.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c new file mode 100644 index 000..861abec --- /dev/null

[Patch ARM-AArch64/testsuite v3 13/21] Add vaddw tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c new file mode 100644 index 000..5804cd7 --- /dev/null

[Patch ARM-AArch64/testsuite v3 19/21] Add vld2_lane, vld3_lane and vld4_lane tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c new file mode 100644 index 000..1991033

[Patch ARM-AArch64/testsuite v3 14/21] Add vbsl tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vbsl.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c new file mode 100644 index 000..bb17f0a --- /dev/null +++ b

[Patch ARM-AArch64/testsuite v3 17/21] Add vld1_dup tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c new file mode 100644 index 000..0e05274 --- /dev

[Patch ARM-AArch64/testsuite v3 20/21] Add vmul tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vmul.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c new file mode 100644 index 000..7527861 --- /dev/null +++ b

[Patch ARM-AArch64/testsuite v3 15/21] Add vclz tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vclz.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c new file mode 100644 index 000..ad28d2d --- /dev/null +++ b

[Patch ARM-AArch64/testsuite v3 18/21] Add vld2/vld3/vld4 tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vldX.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c new file mode 100644 index 000..fe00640 --- /dev/null +++ b

[Patch ARM-AArch64/testsuite v3 21/21] Add vuzp and vzip tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics

[Patch ARM-AArch64/testsuite v3 11/21] Add vaddhn tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c new file mode 100644 index 000..74b4b4d --- /dev/null

[Patch ARM-AArch64/testsuite v3 09/21] Add vabd tests.

2014-10-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vabd.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c new file mode 100644 index 000..e95404f --- /dev/null +++ b

Re: [PATCH] Fix PR63266: Keep track of impact of sign extension in bswap

Hi Thomas, Some minor comments: On 21 October 2014 11:28, Thomas Preud'homme wrote: > Hi Richard, > > I realized thanks to Christophe Lyon that a shift was not right: the shift > count > is a number of bytes instead of a number of bits. > > This extra patch fixes the

Re: [Patch, AArch64] Enable Address sanitizer and UB sanitizer

On 29 September 2014 15:01, Christophe Lyon wrote: > On 26 September 2014 23:05, Andreas Schwab wrote: >> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=34c65c4 >> >> * sanitizer_common/sanitizer_pl

Re: [PATCH] Fix PR63266: Keep track of impact of sign extension in bswap

On 22 October 2014 10:56, Thomas Preud'homme wrote: >> From: Christophe Lyon [mailto:christophe.l...@linaro.org] >> Sent: Tuesday, October 21, 2014 10:03 PM >> > +typedef int SItype __attribute__ ((mode (SI))); >> What's the purpose of this? It seems unused. &

Re: [Patch ARM-AArch64/testsuite v3 00/21] Neon intrinsics executable tests

On 24 October 2014 10:07, Marcus Shawcroft wrote: > On 21 October 2014 14:02, Christophe Lyon wrote: >> This patch series is an updated version of the series I sent here: >> https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00022.html >> >> I addressed comments from Marc

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

On 29 May 2014 11:58, Thomas Preud'homme wrote: >> From: Andreas Schwab [mailto:sch...@linux-m68k.org] >> "Thomas Preud'homme" writes: >> >> > By the way, I couldn't understand how you reached the value >> > 0x44434241. Can you explain me? >> >> Each byte is composed of the first 7 bits of the or

Re: patch to fix PR61325

On 4 June 2014 00:02, James Greenhalgh wrote: > On Thu, May 29, 2014 at 06:38:22PM +0100, Vladimir Makarov wrote: >> The following patch PR61325. The details can be found on >> >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61325 >> >> The patch was bootstrapped and tested on x86/x86-64. >>

Re: patch to fix PR61325

On 5 June 2014 14:37, James Greenhalgh wrote: > On Wed, Jun 04, 2014 at 08:00:51PM +0100, Vladimir Makarov wrote: >> On 2014-06-03, 6:02 PM, James Greenhalgh wrote: >> > On Thu, May 29, 2014 at 06:38:22PM +0100, Vladimir Makarov wrote: >> >>The following patch PR61325. The details can be foun

[Patch ARM/testsuite 01/22] Neon intrinsics execution tests initial framework.

* documentation (README) * dejanu driver (neon-intrinsics.exp) * support macros (arm-neon-ref.h, compute-ref-data.h) * Tests for 2 intrinsics: vaba, vld1 diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/README b/gcc/testsuite/gcc.target/arm/neon-intrinsics/README new file mode 100644 ind

[Patch ARM/testsuite 00/22] Neon intrinsics executable tests

w too). OK for trunk? Thanks, Christophe. Christophe Lyon (22): Neon intrinsics execution tests initial framework. Add unary operators: vabs and vneg. Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub. Add comparison operators: vceq, vcge, vcgt, vcle and vclt. Add compa

[Patch ARM/testsuite 05/22] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_fp_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_fp_op.inc new file mode 100644 index 000..33451d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_fp_op.inc @@ -0,0 +1,75 @@ +/* Template file for th

[Patch ARM/testsuite 02/22] Add unary operators: vabs and vneg.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc new file mode 100644 index 000..33f9b5f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc @@ -0,0 +1,72 @@ +/* Template file for unary

[Patch ARM/testsuite 03/22] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub.

vadd tests also show how to add directives to scan the assembly output. diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_op.inc new file mode 100644 index 000..3483e0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm

[Patch ARM/testsuite 06/22] Add unary saturating operators: vqabs and vqneg.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_sat_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_sat_op.inc new file mode 100644 index 000..3f6d984 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_sat_op.inc @@ -0,0 +1,80 @@ +/* Template fi

[Patch ARM/testsuite 08/22] Add vabal tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabal.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabal.c new file mode 100644 index 000..cd31062 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabal.c @@ -0,0 +1,161 @@ +#include +#include "arm-neon-ref.h" +#i

[Patch ARM/testsuite 04/22] Add comparison operators: vceq, vcge, vcgt, vcle and vclt.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_op.inc new file mode 100644 index 000..a09c5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/cmp_op.inc @@ -0,0 +1,224 @@ +#include +#include "arm-neon-r

[Patch ARM/testsuite 10/22] Add vabdl tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabdl.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabdl.c new file mode 100644 index 000..28018ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabdl.c @@ -0,0 +1,109 @@ +#include +#include "arm-neon-ref.h" +#i

[Patch ARM/testsuite 09/22] Add vabd tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabd.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabd.c new file mode 100644 index 000..e95404f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vabd.c @@ -0,0 +1,153 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 07/22] Add binary saturating operators: vqadd, vqsub.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_sat_op.inc b/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_sat_op.inc new file mode 100644 index 000..35d7701 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_sat_op.inc @@ -0,0 +1,91 @@ +/* Template

[Patch ARM/testsuite 13/22] Add vaddw tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddw.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddw.c new file mode 100644 index 000..5804cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddw.c @@ -0,0 +1,122 @@ +#include +#include "arm-neon-ref.h" +#i

[Patch ARM/testsuite 11/22] Add vaddhn tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddhn.c new file mode 100644 index 000..74b4b4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddhn.c @@ -0,0 +1,109 @@ +#include +#include "arm-neon-ref.h"

[Patch ARM/testsuite 12/22] Add vaddl tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddl.c new file mode 100644 index 000..861abec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vaddl.c @@ -0,0 +1,122 @@ +#include +#include "arm-neon-ref.h" +#i

[Patch ARM/testsuite 14/22] Add vbsl tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbsl.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbsl.c new file mode 100644 index 000..bb17f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbsl.c @@ -0,0 +1,124 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 16/22] Add vdup and vmov tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vdup-vmov.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vdup-vmov.c new file mode 100644 index 000..b5132f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vdup-vmov.c @@ -0,0 +1,253 @@ +#include +#include "arm-neo

[Patch ARM/testsuite 15/22] Add vclz tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vclz.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vclz.c new file mode 100644 index 000..ad28d2d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vclz.c @@ -0,0 +1,194 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 18/22] Add vld2/vld3/vld4 tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX.c new file mode 100644 index 000..f0156c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX.c @@ -0,0 +1,812 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 17/22] Add vld1_dup tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vld1_dup.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vld1_dup.c new file mode 100644 index 000..6aa16cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vld1_dup.c @@ -0,0 +1,189 @@ +#include +#include "arm-neon-r

[Patch ARM/testsuite 19/22] Add vld2_lane, vld3_lane and vld4_lane tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX_lane.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX_lane.c new file mode 100644 index 000..8887c3e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vldX_lane.c @@ -0,0 +1,679 @@ +#include +#include "arm-neo

[Patch ARM/testsuite 20/22] Add vmul tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vmul.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vmul.c new file mode 100644 index 000..7527861 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vmul.c @@ -0,0 +1,156 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 21/22] Add vshl tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vshl.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vshl.c new file mode 100644 index 000..e64d6e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vshl.c @@ -0,0 +1,230 @@ +#include +#include "arm-neon-ref.h" +#incl

[Patch ARM/testsuite 22/22] Add vuzp and vzip tests.

diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vuzp.c new file mode 100644 index 000..53f875e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vuzp.c @@ -0,0 +1,245 @@ +#include +#include "arm-neon-ref.h" +#incl

Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 6 June 2014 01:32, Joseph S. Myers wrote: > Have these been tested for both big and little endian (especially for > tests where memory layout matters - load / store / lane number tests - > remembering that GNU C vector initializers always use array ordering, > which is not the same as the archi

Re: [PATCH] Run phi_only_cprop after 2nd VRP

On 6 June 2014 09:25, Richard Biener wrote: > > This moves the 2nd VRP pass to run befoe phi_only_cprop as > VRP performs jump-threading which can result in BBs with > PHI singletons. > > Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. > > Richard. > Hi, This caused PR 61430 https:/

Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 6 June 2014 17:57, Ramana Radhakrishnan wrote: > On 06/06/14 15:40, Christophe Lyon wrote: >> >> On 6 June 2014 01:32, Joseph S. Myers wrote: >>> >>> Have these been tested for both big and little endian (especially for >>> tests where memory layout

Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios

Hello, This commit (211211) causes gcc.target/aarch64/vect-mull.c execution test to FAIL for target aarch64_be-none-elf. (tested using qemu) Christophe. On 3 June 2014 13:08, Marcus Shawcroft wrote: > On 28 May 2014 08:30, Bin.Cheng wrote: >> Missing patch. >> >> On Wed, May 28, 2014 at 3:02

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