[PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused

The current vsetvl pass eliminates a vsetvl instruction when the previous info is "available," but does not when "compatible." This can lead to not only redundancy, but also incorrect behaviors when the previous info happens to be compatible with a later vector instruction, which ends of using the

FW: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused

Hi Juzhe, > Could you show me what the codegen looks like after this patch ?> I would be > expecting the codegen become: > > foo: >         vsetvli a5,a0,e16,m1,ta,ma >         vmv.x.s a4,v8 >         vadd.vx v9,v8,a4 >         vsetvli zero,a5,e16,m1,ta,ma >         vadd.vv v8,v9,v8 >         re

[PATCH v2] RISC-V: Eliminate latter vsetvl when fused

Hi all, A simple assembly check has been added in this version. Previous version: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662783.html Thanks, Bohan -- The current vsetvl pass eliminates a vsetvl instruction when the previous info is "available," but does not when "compatibl

RE: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused

An updated version has been submitted: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662854.html -- From:Bohan Lei Send Time:2024 Sep. 11 (Wed.) 17:12 To:"gcc-patches" Subject:[PATCH 2/2] RISC-V: Eliminate latter vsetvl wh

[PATCH v2] RISC-V: Eliminate latter vsetvl when fused

Resent to cc Juzhe. -- Hi all, A simple assembly check has been added in this version. Previous version: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662783.html Thanks, Bohan -- The current vsetvl pass eliminates a vsetvl instruction when the previous info is "available,"

[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

The RISC-V vector machine description relies on the helper function `sew64_scalar_helper` to emit actual insns for the DI variants of vssub.vx and vssubu.vx. This works with vssub.vx, but can cause problems with vssubu.vx with the scalar operand being constant zero, because `has_vi_variant_p` retu

[RFC PATCH] cselib: Reuse VALUEs on reg adjustments

The commit 2c0fa3ecf70d199af18785702e9e0548fd3ab793 reuses VALUEs on sp adjustments. We can generalize the idea and reuse VALUEs on other registers. This can help the postreload pass find more opportunities to simplify insns. The following assembly code is generated from the testcase using the c

[PATCH] testsuite: Fix CRC testcases

Hi all, The latest CRC optimization patches include some testcases that do not work well. Some testcases in gcc/testsuite/gcc.dg lead to UNRESOLVED results when testing without an explicit -O flag. Other testcases in gcc/testsuite/gcc.target/riscv do not work when testing with RV32 -march/-mabi

[PATCH] testsuite: Fix CRC testcases

e: Fix CRC testcases On Tue, 2024-12-03 at 15:23 +0800, Bohan Lei wrote: > > diff --git a/gcc/testsuite/gcc.dg/crc-linux-1.c > b/gcc/testsuite/gcc.dg/crc-linux-1.c > index 918b423a583..3261ba48b8b 100644 > --- a/gcc/testsuite/gcc.dg/crc-linux-1.c > +++ b/gcc/testsuite/gcc.dg/

[PATCH] testsuite: Fix CRC testcases

Re: [PATCH] testsuite: Fix CRC testcases On Tue, 2024-12-03 at 17:14 +0800, Bohan Lei wrote: > Thank you for pointing it out. I guess the RV32 issue may still exist. Please send v2 with only the RISC-V fixes if you can still reproduce the issue

Ping: [RFC PATCH v2] cselib: Reuse VALUEs on reg adjustments

Hi all! I would like to ping the patch in https://gcc.gnu.org/pipermail/gcc-patches/2024-December/670763.html (Message-Id: <20241204045717.12982-1-garth...@linux.alibaba.com>). It is supposed to be a generalization of the existing stack pointer VALUE reuse mechanism, based on Jakub's commit 2c0fa

[RFC PATCH v2] cselib: Reuse VALUEs on reg adjustments

This is v2 of the patch in https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669380.html. I missed the ChangeLog entry in that version. The commit 2c0fa3ecf70d199af18785702e9e0548fd3ab793 reuses VALUEs on sp adjustments. We can generalize the idea and reuse VALUEs on other registers. This

[PATCH] RISC-V: Disable RV64-only crc testcases for RV32

These testcases require RV64 targets. They fail when -march=rv32* is specified while using an riscv64* compiler. gcc/testsuite/ChangeLog: * gcc.target/riscv/crc-21-rv64-zbc.c: Disallow rv32 targets. * gcc.target/riscv/crc-21-rv64-zbkc.c: Ditto. --- gcc/testsuite/gcc.target/riscv

Re: [PATCH] RISC-V: xtheadmemidx: Split slli.uw pattern

patches" CC:"christoph.muellner" Subject:Re: [PATCH] RISC-V: xtheadmemidx: Split slli.uw pattern On 3/23/25 8:43 PM, Bohan Lei wrote: > The combine pass can generate an index like (and:DI (mult:DI (reg:DI) > (const_int scale)) (const_int mask)) when XTheadMemIdx is avai

[PATCH] RISC-V: xtheadmemidx: Split slli.uw pattern

The combine pass can generate an index like (and:DI (mult:DI (reg:DI) (const_int scale)) (const_int mask)) when XTheadMemIdx is available. LRA may pull it out, and thus a splitter is needed when Zba is not available. A similar splitter were introduced when XTheadMemIdx support was added, but remov

Ping^2: [RFC PATCH v2] cselib: Reuse VALUEs on reg adjustments

Ping. -- From:Jeff Law Send Time:2024 Dec. 19 (Thu.) 00:18 To:Bohan Lei; "gcc-patches" CC:jakub Subject:Re: Ping: [RFC PATCH v2] cselib: Reuse VALUEs on reg adjustments On 12/17/24 9:48 PM, Bohan Lei wrote: > H