RE: [PATCH RFA] Implement register pressure directed hoist pass

Thanks for comments. > -Original Message- > From: Steven Bosscher [mailto:stevenb@gmail.com] > Sent: Friday, September 28, 2012 4:29 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org; Eric Botcazou; Richard Sandiford; > vmaka...@redhat.com > Subject: Re: [PATCH RF

RE: [PATCH RFA] Implement register pressure directed hoist pass

> -Original Message- > From: Steven Bosscher [mailto:stevenb@gmail.com] > Sent: Friday, September 28, 2012 4:29 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org; Eric Botcazou; Richard Sandiford; > vmaka...@redhat.com > Subject: Re: [PATCH RFA] Implement regis

RE: [PATCH RFA] Implement register pressure directed hoist pass

Hi Steven, Thanks for the comments and sorry for the delay with this message. > -Original Message- > > Hello, > > Thanks for the update. The first look wasn't a very thorough review, so I have > more comments now. Sorry for that, I should have taken the time for this the > first time rou

RE: [PATCH RFA] Implement register pressure directed hoist pass

Hi Jeff, Thanks for reviewing and sorry for this delayed message. > > > + /* Only decrease distance if bb has high register pressure or EXPR > > +is const expr, otherwise EXPR can be hoisted through bb without > > +cost. */ > ?!? This comment makes no sense to me. To accurately kn

RE: [PING Updated]: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1

Ping. > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Tuesday, September 25, 2012 4:00 PM > To: 'Richard Sandiford' > Cc: Ramana Radhakrishnan; Richard Earnshaw; gcc-patch

RE: [PING Updated]: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1

Ping^2 > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Monday, October 08, 2012 2:36 PM > To: gcc-patches@gcc.gnu.org > Cc: Ramana Radhakrishnan; Richard Earnshaw; 'Richard Sandifor

RE: [PATCH RFA] Implement register pressure directed hoist pass

% Thumb2 X x86 X x86_64 X (X means no obvious effect, unfortunately.) Also, since this is the simplification of previous patch, I think there is no slowdown in compilation. Please review. Thanks. And updated ChangeLog entry: 2012-10-11 Bin Cheng

RE: [PATCH RFA] Implement register pressure directed hoist pass

> -Original Message- > From: Steven Bosscher [mailto:stevenb@gmail.com] > Sent: Friday, October 12, 2012 7:04 AM > To: Bin Cheng > Cc: Jeff Law; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH RFA] Implement register pressure directed hoist pass > > On Thu,

RE: [PATCH RFA] Implement register pressure directed hoist pass

it's right, this can prove my previous observation that decrease of register pressure during hoisting process is rare. I will continue investigating the correctness of the patch and see what I can get. Please review. Thanks And the ChangeLog: 2012-10-12 Bin Cheng * gcse.c: Update

RE: [PATCH RFA] Implement register pressure directed hoist pass

Hi Steven, Jeff, I found a flaw in original patch, which results in inaccurate register pressure. Here comes the updated patches, improving code size a little bit on Thumb2/powerpc comparing to original patches. Please review. Thanks 2012-10-16 Bin Cheng * gcse.c: Update copyright

RE: [PATCH RFA] Implement register pressure directed hoist pass

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 17, 2012 1:02 AM > To: Bin Cheng > Cc: 'Steven Bosscher'; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH RFA] Implement register pressure directed hoist pass > >

[PATCH GCC]Fix test case failure reported in PR54989

/testsuite/ChangeLog 2012-10-22 Bin Cheng * gcc.dg/hoist-register-pressure.c: Simplify the case by using fewer registers. Index: gcc/testsuite/gcc.dg/hoist-register-pressure.c === --- gcc/testsuite/gcc.dg/hois

RE: [PATCH GCC]Fix test case failure reported in PR54989

> -Original Message- > From: Jakub Jelinek [mailto:ja...@redhat.com] > Sent: Monday, October 22, 2012 3:16 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix test case failure reported in PR54989 > > On Mon, Oct 22, 2012 at 11:00:08A

RE: [PATCH GCC]Fix test case failure reported in PR54989

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Saturday, October 27, 2012 2:54 AM > To: Bin Cheng > Cc: 'Jakub Jelinek'; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix test case failure reported in PR54989 > > On 10

[PATCH GCC]Improving register pressure directed hoist

X x86 X x86_64 X Note: Though X means no obvious effect on code size, this patch does improve it a little bit on these targets. I bootstrapped this patch on x86/x86_64, and tested it on x86/x86_64/arm-none-eabi. Is it OK? Thanks. 2012-10-29 Bin Cheng * gcse

RE: [PATCH GCC]Fix test case failure reported in PR54989

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Tuesday, October 30, 2012 2:27 AM > To: Bin Cheng > Cc: 'Jakub Jelinek'; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix test case failure reported in PR54989 > > On 10

RE: [PATCH GCC]Improving register pressure directed hoist

> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Monday, October 29, 2012 2:59 PM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH GCC]Improving register pressure directed hoist >

RE: GCC 4.8.0 Status Report (2012-10-29), Stage 1 to end soon

> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Jakub Jelinek > Sent: Tuesday, October 30, 2012 1:57 AM > To: g...@gcc.gnu.org > Cc: gcc-patches@gcc.gnu.org > Subject: GCC 4.8.0 Status Report (2012-10-29), Stage 1 to end soo

[PATCH PR67921]Convert pointer expr to proper type before negating it

change. As a matter of fact, we may need to do the same thing for signed int types because -TYPE_MIN is undefined. Unfortunately, I failed to create a test in this case. Bootstrap and test on x64_64, is it OK? 2016-01-27 Bin Cheng PR tree-optimization/67921 * fold-const.c (spli

[PATCH AArch64]Force register scaling out of mem ref and comment why

imizer should be improved. Bootstrap and test on AArch64, is it OK? Thanks, bin 2016-02-04 Bin Cheng * config/aarch64/aarch64.c (aarch64_legitimize_address): Force register scaling out of memory reference and comment why. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/c

[PATCH PR68021]Don't add biv candidate if it's not incremented by a single stmt

owing passes. This patch fixes the issue by the 2nd method. Bootstrap and test on x86_64 and AArch64 (test ongoing). Is it OK if no failures? Thanks, bin 2016-02-04 Bin Cheng PR tree-optimization/68021 * tree-ssa-loop-ivopts.c (increment_stmt_for_biv_p): New function.

[PATCH PR69052]Check if loop inv can be propagated into mem ref with additional addr expr canonicalization

AArch64. Is it OK? Thanks, bin 2016-02-09 Bin Cheng PR tree-optimization/69052 * loop-invariant.c (canonicalize_address): New function. (inv_can_prop_to_addr_use): Check validity of address expression which is canonicalized by above function. gcc/testsuite/

[PATCH PR68021]Set ratio to 1 when computing the value of biv cand by itself

t is known that the use has the value of the biv cand. Bootstrap and test on x86_64 and aarch64. Is it OK if no failures? Thanks, bin 2016-02-09 Bin Cheng PR tree-optimization/68021 * tree-ssa-loop-ivopts.c (get_computation_aff): Set ratio to 1 if when computing th

Re: [PATCH PR69052]Check if loop inv can be propagated into mem ref with additional addr expr canonicalization

From: Jeff Law Sent: 11 February 2016 23:26 To: Bin.Cheng Cc: Bin Cheng; gcc-patches@gcc.gnu.org; nd Subject: Re: [PATCH PR69052]Check if loop inv can be propagated into mem ref with additional addr expr canonicalization >> On 02/11/2016 10

[PATCH GCC]Obvious change, dump min_profitable_estimate, rather than min_profitable_iters

change rule can be applied during stage4 or not. Thanks, bin 2016-02-22 Bin Cheng * tree-vect-loop.c (vect_estimate_min_profitable_iters): Dump min_profitable_estimate, rather than min_profitable_iters. Index: gcc/tree-vect-loop.c

[PATCH PR69052]Set higher precedence for CONST_WIDE_INT than CONST_INT when canonicalizing addr expr

cated case, I worked out a patch forcing CONST_INT to lower precedence than CONST_WIDE_INT, so that for sure it will be sorted after all other kinds sub-parts. This is an obvious change. Bootstrap&test on x86_64, bootstrap&test on AArch64. Is it OK for this stage? Thanks, bin 2016-03-

[PATCH PR66388]Compute use with cand of smaller precision by further exercising scev overflow info.

_overflow info to add_candidate and add_candidate_1. (get_computation_aff, get_computation_cost_at): Handle candidate with smaller precision than iv use. gcc/testsuite/ChangeLog 2015-07-16 Bin Cheng PR tree-optimization/66388 * gcc.dg/tree-ssa/pr66388.c: New test. I

[PATCH GCC]By pass following iterations if expr has already been simplified into const.

Hi, This is an obvious change to bypass following iterations if expr has already been simplified into constant in function simplify_using_loop_initial_conditions. Is it OK? Thanks, bin 2015-07-28 Bin Cheng * tree-ssa-loop-niter.c (simplify_using_initial_conditions): Break

[PATCH GCC]Improve bound information in loop niter analysis

bound information is computed for test cases added by this patch. Is it OK? Thanks, bin 2015-07-28 Bin Cheng * tree-ssa-loop-niter.c (refine_value_range_using_guard): New. (determine_value_range): Call refine_value_range_using_guard for each loop initial condition to

[PATCH GCC]Improve loop bound info by simplifying conversions in iv base

scev analysis itself and simple_iv isn't an interface for that. Is it OK? Thanks, bin 2015-07-28 Bin Cheng * tree-ssa-loop-niter.c (tree_simplify_using_condition): Export the interface. * tree-ssa-loop-niter.h (tree_simplify_using_condition): Declare.

[PATCH GCC]Improve rtl loop inv cost by checking if the inv can be propagated to address uses

d spec2k6 on x86_64, no regression. Bootstrap and test on x86_64 and x86_32. Will test it on aarch64. So any comments? Thanks, bin 2015-09-28 Bin Cheng * loop-invariant.c (struct def): New field cant_fwprop_to_addr_uses. (inv_cant_fwprop_to_addr_use): New function.

[PATCH PR67921]Use sizetype for CHREC_RIGHT when building pointer type CHREC

building pointer type CHREC. This simple patch fixes the ICE issue. Bootstrap and test on x86 & x86_64. Is it OK? Note, I do think the associate logic in fold_binary_loc needs fix, but that should be another patch. 2015-10-20 Bin Cheng PR tree-optimization/67921 *

[PATCH GCC]Fix memory leak and wrong invariant dependence computation in IVOPT

ls to get_computation_cost for a grouped iv use. This results in loss of depends_on information, as well memory leaks for depends_on bitmap. I think this is an obvious fix to the issue. Bootstrap and test on x86_64. OK? Thanks, bin 2015-10-27 Bin Cheng * tree-ssa-loop-ivopts.c (split_address

[PATCH PR52272]Be smart when adding iv candidates

on AArch64. Is it OK? Thanks, bin 2015-11-03 Bin Cheng PR tree-optimization/52272 * tree-ssa-loop-ivopts.c (struct iv_common_cand): New struct. (struct iv_common_cand_hasher): New struct. (iv_common_cand_hasher::hash): New function. (iv_common_can

[PATCH AArch64]Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address

Hi, GIMPLE IVO needs to call backend interface to calculate costs for addr expressions like below: FORM1: "r73 + r74 + 16380" FORM2: "r73 << 2 + r74 + 16380" They are invalid address expression on AArch64, so will be legitimized by aarch64_legitimize_address. Below are what we got from that

[PATCH PR68529]Fix not recognized scev by computing no-overflow info for loop with NE_EXPR exit condition

s isn't appropriate for Stage3. Bootstrap and test on x86_64 and x86. I don't expect any issue on aarch64 either. Is it OK? 2015-11-27 Bin Cheng PR tree-optimization/68529 * tree-ssa-loop-niter.c (number_of_iterations_ne): Add new param. Compute no-overf

[PATCH AArch64]Use aarch64_sync_memory_operand in atomic_store pattern

generated: 67 add x1, x29, 48 68 add x1, x1, x0, sxtw 3 69 stlrx19, [x1] Bootstrap and test on aarch64. Is it OK? Thanks, bin 2015-12-01 Bin Cheng * config/aarch64/atomics.md (atomic_store): Use predicate aarch64_sync_memory_operand. diff --g

[PATCH GCC][01/13]Introduce internal function IFN_LOOP_DIST_ALIAS

. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * cfgloop.h (struct loop): New field ldist_alias_id. * cfgloopmanip.c (lv_adjust_loop_entry_edge): Comment change. * internal-fn.c (expand_LOOP_DIST_ALIAS): New function

[PATCH GCC][02/13]Skip distribution if there is no loop

Hi, this is a simple patch skipping distribution if there is no loop at all. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * cfgloop.h (pass_loop_distribution::execute): Skip if no loops.From eb6a795331efde92fd6df1c6e612fb1ffa9f482f Mon Sep 17

[PATCH GCC][03/13]Mark and skip distributed loops

Hi, This simple patch marks distributed loops and skips it in following distribution. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (generate_loops_for_partition): Mark distributed loops

[PATCH GCC][05/13]Refactoring partition merge

Hi, This simple patch refactors partition merge code and dump information. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (enum fuse_type, fuse_message): New. (partition_merge_into): New parameter. Dump reason

[PATCH GCC][07/13]Preserve data references for whole distribution life time

Hi, This patch collects and preserves all data references in loop for whole distribution life time. It will be used afterwards. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (datarefs_vec, datarefs_map): New

[PATCH GCC][04/13]Sort statements in topological order for loop distribution

issue by sorting in topological order. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (bb_top_order_index): New. (bb_top_order_index_size, bb_top_order_cmp): New. (stmts_from_loop): Use topological

[PATCH GCC][06/13]Preserve loop nest in whole distribution life time

Hi, This simple patch computes and preserves loop nest vector for whole distribution life time. The loop nest will be used multiple times in on-demand data dependence computation. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop

[PATCH GCC][09/13]Simply cost model merges partitions with the same references

only merge partitions with the same references. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (ref_base_address): Delete. (similar_memory_accesses): Rename ... (share_memory_accesses): ... to this. Che

[PATCH GCC][11/13]Annotate partition by its parallelism execution type

x27;t work very well because it does blind distribution/fusion. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (alias.h): Include header file. (enum partition_type): New. (struct partition): New field

[PATCH GCC][08/13]Refactoring structure partition for distribution

it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (struct partition): New fields recording its data references. (partition_alloc, partition_free): Init and release data refs. (partition_merge_into): Merge data refs. (build_rdg_partition_for_v

[PATCH GCC][10/13]Compute and cache data dependence relation

Hi, This patch computes and caches data dependence relation in a hash table so that it can be queried multiple times later for partition dependence check. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (struct

[PATCH GCC][13/13]Distribute loop with loop versioning under runtime alias check

in SCC now. A better fusion algorithm is desired to minimize loop overhead, maximize parallelism and maximize Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c: Add general explanantion on the pass.

[PATCH GCC][12/13]Workaround reduction statements for distribution

patch simply workarounds reduction issue by checking if the statement belongs to all partitions. If yes, the reduction must be computed in the last partition no matter how the loop is distributed. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng

[PATCH GCC][1/2]Feed bound computation to folder in loop split

test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-12 Bin Cheng * tree-ssa-loop-split.c (compute_new_first_bound): Feed bound computation to folder, rather than force to gimple operands too early.From 372dc98aa91fd495c98c2326f854eb5f2c76500b Mon Sep 17 00:00:00

[PATCH GCC][2/2]Refine CFG and bound information for split loops

st can be completely unrolled by later passes. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-12 Bin Cheng * tree-ssa-loop-split.c (compute_new_first_bound): Compute and return bound information for the second split loop. (adjust_loop_split): New fu

[PATCH GCC][2/4]Remove interface initialize_root in predcom

Hi, This simple patch removes interface initialize_root. It's simple enough and called only once. Bootstrap(O2/O3) in patch series on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-21 Bin Cheng * tree-predcom.c (initialize_root): Delete. (execute_pred_commoning_

[PATCH GCC][3/4]Generalize dead store elimination (or store motion) across loop iterations in predcom

re. Bootstrap(O2/O3) in patch series on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-21 Bin Cheng * tree-predcom.c: Revise general description of pass. (enum chain_type): New enum type for store elimination. (struct chain): New field supporting sto

[PATCH GCC][1/4]Extend interface ref_at_iteration to compute ref @ (NITERS + ITERS)-th iteration

/O3) in patch series on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-21 Bin Cheng * tree-predcom.c (ref_at_iteration): Add parameter NITERS. Compute memory reference to DR at (NITERS + ITERS)-th iteration of loop.From ed1df7daca3d2dc2c3ba1c504d5431fba96d0887 Mon Sep 17 00

[PATCH GCC][4/4]Better handle store-stores chain if eliminated stores only store loop invariant

{ a[i] = 1; } a[n] = 2; a[n+1] = 2; Bootstrap(O2/O3) in patch series on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-21 Bin Cheng * tree-predcom.c: (struct chain): Handle store-store chain in which stores for elimination only store loop inva

[PATCH PR81196]Analyze ntiers for loop with exit condition comparing induction variables

Hi, This patch picks up a missed-optimization case in loop niter analysis. With this patch, niters information for loop as in added test can be analyzed. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-27 Bin Cheng PR tree-optimization/81196 * tree

[PATCH Obvious]Remove redundant check on component distance

Hi, This is an obvious patch removing redundant check on component distance in tree-predcom.c Bootstrap and test along with next patch. Is it OK? Thanks, bin 2017-11-15 Bin Cheng * tree-predcom.c (add_ref_to_chain): Remove check on distance.From

[PATCH GCC]Support load in CT_STORE_STORE chain if dominated by store in the same loop iteration

mixed chain. That would need fundamental rewrite of the pass and not sure how useful it would be. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-11-15 Bin Cheng * tree-predcom.c: Add general comment on Store-Store chains. (split_data_refs_to_components

[PATCH GCC]Rename and make remove_dead_inserted_code a simple dce interface

ge to branch: gcc.gnu.org/svn/gcc/branches/gimple-linterchange. Thanks, bin 2017-11-27 Bin Cheng * tree-ssa-dce.c (simple_dce_from_worklist): Move and rename from tree-ssa-pre.c::remove_dead_inserted_code. * tree-ssa-dce.h: New file. * tree-ssa-pre.c (tree-ssa-

[PATCH branch/gimple-linterchange]Use dyn_cast instread of is_a<> and as_a<>

Hi, This is a simple patch using dyn_cast instead of is_a<> and as_a<> as suggested by review. This is for branches/gimple-linterchange, bootstrap and test as when the branch is created. Is it OK? Thanks, bin 2017-11-30 Bin Cheng * gimple-loop-interchange.cc (is-a.h)

[PATCH branch/gimple-interchange]obvious cleanup

Hi, This is an obvious cleanup patch doing variable renaming, function inlining. Is it OK? Thanks, bin 2017-12-05 Bin Cheng * gimple-loop-interchange.cc (struct induction): Rename fields. (dump_induction, loop_cand::analyze_induction_var): Update uses. (loop_cand

[PATCH TEST]Adjust GRAPHITE tests in preparation for loop interchange

Hi, The loop interchange pass reuses option -floop-interchange from GRAPHITE, this patch adjusts all affected GRAPHITE tests by changing the option to -floop-nest-optimize. Test result checked with/without loop interchange. Is it OK? Thanks, bin gcc/testsuite 2017-12-06 Bin Cheng

[PATCH GCC]Introduce loop interchange pass and enable it at -O3

aves either. So is it OK? Thanks, bin 2017-12-07 Bin Cheng Richard Biener PR tree-optimization/81303 * Makefile.in (gimple-loop-interchange.o): New object file. * common.opt (floop-interchange): Reuse the option from graphite. * doc/invoke.texi (-fl

[PATCH GCC]More conservative interchanging small loops with const initialized simple reduction

this patch. Is it OK if test passes? Thanks, bin 2017-12-08 Bin Cheng * gimple-loop-interchange.cc (struct loop_cand): New field. (loop_cand::loop_cand): Init new field in constructor. (loop_cand::classify_simple_reduction): Record simple reduction initialized

[PATCH PR83320]Fix new/free mismatch issue

Hi, While I am still trying to reproduce and verify the issue (valgrind checking runs very slow for me), It's clear I made stupid mistake using free for newed vector. This simple patch fixes it. Bootstrap and test ongoing. Is it OK? Thanks, bin 2017-12-06 Bin Cheng PR

[PATCH PR81740]Enforce dependence check for outer loop vectorization

enforcing dependence check. It also adds two tests with one shouldn't be vectorized and the other should. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-12-15 Bin Cheng PR tree-optimization/81740 * tree-vect-data-refs.c (vect_analyze_data_ref_depen

[GCC BACKPORT]Backport revision 254777 and 254778 to GCC 7 branch

Hi, This patch backports revision 254777 and 254778 to GCC 7 branch. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2017-12-18 Bin Cheng Backport from mainline 2017-11-15 Bin Cheng PR tree-optimization/82726 PR tree-optimization/70754 * tree

[PATCH BACKPORT]Backport r254778 and test case in r244815 to GCC6

HI, This patch backports r254778 and test case in r244815 to GCC6. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2017-12-18 Bin Cheng Backport from mainline 2017-11-15 Bin Cheng PR tree-optimization/82726 PR tree-optimization/70754 * tree

[PATCH PR83695]Fix ICE by resetting cached scev info after interchange.

en we only interchange in limited cases. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2018-01-11 Bin Cheng PR tree-optimization/83695 * gimple-loop-linterchange.cc (tree_loop_interchange::interchange_loops): Call scev_reset_htab to reset cached

[PATCH PR82604]Fix regression in ftree-parallelize-loops

han now, so parloop can parallelize as before. Bootstrap and test on x86_64 and AArch64 ongoing. Is it OK if no errors? Thanks, bin 2018-01-19 Bin Cheng PR tree-optimization/82604 * tree-loop-distribution.c (enum partition_kind): New enum item PKIND_PARTIAL_MEMSET.

[PATCH PR82965/PR83991]Fix invalid profile count in vectorization peeling

rap and test on x86_64 and AArch64. gcc.dg/vect/pr79347.c is fixed for both PR82965 and PR83991. Is this OK? Thanks, bin 2018-01-30 Bin Cheng PR tree-optimization/82965 PR tree-optimization/83991 * cfgloopmanip.c (scale_loop_profile): Further scale loop's profile

[PATCH AArch64]Fix test failure for pr84682-2.c

Hi, This simple patch fixes test case failure for pr84682-2.c by returning false on wrong mode rtx in aarch64_classify_address, rather than assert. Bootstrap and test on aarch64. Is it OK? Thanks, bin 2018-03-16 Bin Cheng * config/aarch64/aarch64.c (aarch64_classify_address

[PATCH PR84969]Don't reorder builtin memsets if they set different rhs values

ould be resolved in a more general way maximizing parallelism as well as merging opportunities when sorting partitions into topological order from dependence graph, which isn't GCC8 task. Bootstrap and test on x86_64 and AArch64 ongoing. Okay if no failures? Thanks, bin 2018-03-20 Bin Che

[PATCH testsuite]Fix pr83126.c failure for bare-metal toolchains

Hi, The new test pr83126.c requires pthread for compiling, this simple patch skips it for bare-metal toolchains. Test checked. Is it OK? Thanks, bin gcc/testsuite 2018-03-22 Bin Cheng * gcc.dg/graphite/pr83126.c: Require pthread for the test.diff --git a/gcc/testsuite/gcc.dg

[wwwdocs]Mention -ftree-loop-distribution

Hi, Option -ftree-loop-distribution is improved and enabled by default at -O3 for GCC8. This patch describes the change, is it OK? Thanks, binIndex: htdocs/gcc-8/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,

[PATCH PR85190]Adjust pointer for aligned access

04-10 Bin Cheng PR testsuite/85190 * gcc.dg/vect/pr81196.c: Adjust pointer for aligned access.diff --git a/gcc/testsuite/gcc.dg/vect/pr81196.c b/gcc/testsuite/gcc.dg/vect/pr81196.c index 46d7a9e..15320ae 100644 --- a/gcc/testsuite/gcc.dg/vect/pr81196.c +++ b/gcc/testsuite/gcc.dg

[PATCH GCC][1/6]Compute type mode and register class mapping

the original version patch at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html Bootstrap and test on x86_64 and AArch64 ongoing. Any comments? Thanks, bin 2018-04-27 Bin Cheng * ira.c (setup_mode_classes): New function. (find_reg_classes): Call above function.

[PATCH GCC][2/6]Compute available register for each register classes

Hi, This is the second patch computing available/clobber registers for register classes. It's the same as the original patch posted @https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01022.html Bootstrap and test on x86_64 and AArch64 ongoing. Any comments? Thanks, bin 2017-04-27 Bin

[PATCH GCC][3/6]Delete unnecessary function live_merge_and_clear

HI, This is an obvious patch removing the unnecessary function. Bootstrap and test on x86_64 and AArch64 ongoing. Is it OK? Thanks, bin 2018-04-27 Bin Cheng * tree-ssa-live.h (live_merge_and_clear): Delete.From ba6e47da7faba9a31c776a6d06ef052b1ed392a8 Mon Sep 17 00:00:00 2001 From

[PATCH GCC][4/6]Support regional coalesce and live range computation

hanks, bin 2018-04-27 Bin Cheng * tree-outof-ssa.c (remove_ssa_form): Update use. * tree-ssa-coalesce.c (build_ssa_conflict_graph): Support regional coalesce. (coalesce_with_default): Update comment. (create_outofssa_var_map): Support regional coalesce.

[PATCH GCC][5/6]implement live range, reg pressure computation class

e and coalesce data structures and algorithms in the future. Bootstrap and test on x86_64 and AArch64 ongoing. Any comments? Thanks, bin 2018-04-27 Bin Cheng * tree-ssa-live.c (memmodel.h, ira.h, tree-ssa-coalesce.h): Include. (struct stmt_lr_info, free_stmt_lr_info)

[PATCH GCC][6/6]Restrict predcom using register pressure information

2018-04-27 Bin Cheng * tree-predcom.c (stor-layout.h, tree-ssa-live.h): Include. (REG_RELAX_RATIO, prune_chains): New. (tree_predictive_commoning_loop): Compute reg pressure using class region. Prune chains based on reg pressure. Force to not unroll if

[PATCH PR85793]Fix ICE by loading vector(1) scalara_type for 1 element-wise case

Hi, This patch fixes ICE by loading vector(1) scalar_type if it's 1 element-wise for VMAT_ELEMENTWISE. Bootstrap and test on x86_64 and AArch64 ongoing. Is it OK? Thanks, bin 2018-05-16 Bin Cheng Richard Biener PR tree-optimization/85793 * tree-vect-st

[PATCH PR85804]Fix wrong code by correcting bump step computation in vector(1) load of single-element group access

Bin Cheng PR tree-optimization/85804 * tree-vect-stmts.c (vectorizable_load): Compute correct bump step for vector(1) load in single-element group access. gcc/testsuite 2018-05-17 Bin Cheng PR tree-optimization/85804 * gcc.c-torture/execute/pr85804.c

[PATCH PR85720/partial]Support runtime loop versioning if loop can be distributed into builtin functions

test on x86_64. Is it OK? Thanks, bin 2018-05-22 Bin Cheng * tree-loop-distribution.c (break_alias_scc_partitions): Don't merge SCC if all partitions are builtins. (version_loop_by_alias_check): New parameter. Generate cancelable runtime alias ch

[PATCH testcase]Add bind_pic_locally to case addrtmp.c

Hi, The case depends on GCC inlining of global function, but the callee won't be inlined because it's global function and considered over-writable during run-time. This patch fixes the failure by binding it to pic locally. Is it OK? Thanks, bin gcc/testsuite/ChangeLog 2014-08-07

[PATCH testcase]Skip test pr61772.c for lto tests

nning check is failed in these cases. I think disabling lto won't weaken the test since what it tests has nothing to do with lto. This patch fixes these failures by disabling lto. Is it OK? Thanks, bin gcc/testsuite/ChangeLog 2014-08-07 Bin Cheng * gcc.dg/torture/pr61772.c: Skip l

[PATCH lto]Fix the mis-matched arguments of lto_define_builtins

Hi, As analyzed in PR62032, this patch fixes the latent lto bug by switching arguments of lto_define_builtins, otherwise vsnprintf-chk.c would fail on arm/aarch64 with lto options. Is it ok if bootstrap and test pass? 2014-08-07 Bin Cheng PR lto/62032 * lto/lto-lang.c

[PATCH testcase]fix failure of g++.dg/ext/arm-fp16/fp16-mangle-1.C

ly? Thanks very much. Thanks, bin gcc/testsuite/ChangeLog 2014-08-14 Bin Cheng * g++.dg/ext/arm-fp16/fp16-mangle-1.C: Also check .weak. Index: gcc/testsuite/g++.dg/ext/arm-fp16/fp16-mangle-1.C === --- gcc/testsuite/g++.dg

[PATCH GCC]Fix broken Canadian when checking isl library support

sl library is available or not. We also can't set it to `no' by default, because "--with-isl=" option would be nullified in this way. I think the best we can do here is add AC_LINK_IFELSE when checking. This patch fixes the issue. Is it OK? 2014-08-21 Bin Cheng

[PATCH GCC]Cleanup interface of iv_ca_add_use and the calls to it

86_64/x86. So is it OK? Thanks, bin 2014-08-27 Bin Cheng * tree-ssa-loop-ivopts.c (iv_ca_add_use): Delete parameter important_candidates. Consider all important candidates if IVS doesn't give any result. Remove check on ivs->upto. (try_add_cand_for): Cal

[PATCH PR62151]Fix uninitialized register issue caused by distribute_notes in combine pass

later. So is it OK? Any comments will be appreciated. Thanks, bin 2014-08-27 Bin Cheng PR rtl-optimization/62151 * combine.c (distribute_notes): Check i2 if it modifies register in REG_DEAD note immediately, set tem_insn accordingly.Index: gcc/combine.c

[PATCH ARM]Use stricter constraint for pattern arm_movqi_insn to avoid constant pool

03. This patch is necessary for inlining memset calls on ARM target. It passes tests on arm-none-eabi/arm-none-linux-gnueabi/arm-none-linux-gnueabihf with different test variants. It also passes bootstrap and glibc build on arm-none-linux-gnueabihf. Is it OK? Thanks, bin 2014-09-04 Bin C

[PATCH COMMIT]Handle REG addressing mode in output_move_neon explicitly

idn't have enough time to fixed back that time. Now with the potential bug resolved by https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00298.html , I will apply this patch in 24h again if no objection. Retested along with memset-inlining patch set. Thanks, bin 2014-09-04 Bin Cheng

[PATCH ARM]memset inlining patch for arm

09-04 Bin Cheng PR target/55701 * config/arm/arm.md (setmem): New pattern. * config/arm/arm-protos.h (struct tune_params): New fields. (arm_gen_setmem): New prototype. * config/arm/arm.c (arm_slowmul_tune): Initialize new fields. (arm_fastmul

[PATCH PR62631]Return shiftadd cost only when it's smaller than normal one

eparated shift and add instructions. Probably sparc64 should return cost no larger than cost(shift)+cost(add) in the first place?. Bootstrap and tested on x86_64/cortex-m3, the case is fixed on sparc64 now. Is it OK? Thanks, bin 2014-09-04 Bin Cheng * tree-ssa-loop-

[PATCH PING]Improve induction variable elimination

patch, spec2k/fp can be improved a little on aarch64. Bootstrap and test on x86_64 and x86, I am also prepared to fix any regression in the future. Is it OK? 2014-09-30 Bin Cheng * tree-ssa-loop-ivopts.c (iv_nowrap_period) (nowrap_cand_for_loop_niter_p): New func

[PATCH]Enable elimination of IV use with unsigned type candidate

nce otherwise there is type overflow. These two patch fix the mentioned problem. They pass bootstrap and regression test on x86_64/x86/aarch64/arm, so any comments? Thanks, bin PATCH A) 2014-06-23 Bin Cheng * tree-ssa-loop-ivopts.c (iv_elimination_compare_lt): Check number

RE: [PATCH ARM]Handle REG addressing mode in output_move_neon explicitly

> -Original Message- > From: Bin.Cheng [mailto:amker.ch...@gmail.com] > Sent: Wednesday, July 02, 2014 1:46 PM > To: Ramana Radhakrishnan > Cc: Bin Cheng; Richard Earnshaw; gcc-patches > Subject: Re: [PATCH ARM]Handle REG addressing mode in > output_move_neon explic

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