We are trying to examine all uses of a reg, but overlook those in a
REG_EQUIV note. This is problematic as documented in the PR.
The following patch fixes it according to Pat Haugen. Bootstrapped and
tested on x86_64-linux, ok?
Bernd
* ira.c (find_moveable_pseudos): Skip registers whose
DF
On 05/15/2012 09:12 AM, Eric Botcazou wrote:
Ok, that looks like three votes in favour. I've checked in the following
variant with a few minor changes. I've added strcpy and memset to the
list of functions, and split off a new function in ira-lives.
Changes to subdirectories must be documented
ChangeLog
===
--- gcc/ChangeLog (revision 187744)
+++ gcc/ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2012-05-21 Bernd Schmidt
+
+ PR rtl-optimization/53373
+ * caller-save.c (save_call_clobbered_regs): Look into a possible
+ PARALLEL manually rather than using single_set on a call insn.
+
2
On 05/25/2012 04:15 PM, Diego Novillo wrote:
On 12-05-25 09:56 , Jakub Jelinek wrote:
On Fri, May 25, 2012 at 03:51:25PM +0200, Michael Matz wrote:
On Fri, 25 May 2012, Gabriel Dos Reis wrote:
That's one of my fears, namely that those used to the libstdc++ style
impose that on the compiler sour
On 06/09/2012 01:58 AM, Mike Stump wrote:
On Jun 8, 2012, at 4:11 PM, Mike Stump wrote:
On Apr 17, 2012, at 2:08 PM, Bernd Schmidt wrote:
This patch enables GET_MODE_WIDER_MODE for MODE_PARTIAL_INT (by setting
the wider mode to the one the partial mode is based on), which is useful
for the
On 08/03/11 12:41, Alan Modra wrote:
> This patch makes rebuild_jump_labels set JUMP_LABEL appropriately
> for return jumps, and fixes sharing for RETURN. Since ANY_RETURN_P(X)
> is defined as ((X) == ret_rtx), RETURNs need to stay shared.
> Bootstrapped and regression tested powerpc-linux and pow
On 08/04/11 13:16, Richard Sandiford wrote:
> Tested in the same way as the previous patch. OK to install?
You don't actually need to ask, and based on Revital's reaction, yes.
Bernd
On 07/21/11 17:42, Richard Sandiford wrote:
> At the moment, auto-inc-dec.c only considers pairs of instructions,
> so it can't optimise this kind of sequence. The attached patch is a
> WIP (but almost complete) attempt to handle longer sequences too.
So, I promised to look at it, I guess I bett
On 07/22/11 19:23, Bernd Schmidt wrote:
> On 07/22/11 19:17, Richard Henderson wrote:
>> On 07/22/2011 10:00 AM, Eric Botcazou wrote:
>>>> It's getting confused about loads/stores being control_flow_insns and
>>>> getting scheduled past each other nonetheless.
On 08/04/11 16:31, Paul Brook wrote:
> C6X uses an unwinding/exception handling echeme very similar to that defined
> by the ARM EABI. The core of the unwinder is the same, so I've pulled it out
> into a common file.
>
> Other than the obvious target specific bits, the main compiler visible
>
On 08/23/11 11:05, Jakub Jelinek wrote:
> On Mon, Jun 20, 2011 at 09:38:22PM +0200, Bernd Schmidt wrote:
>> D'oh. Blackfin has a (clrsb:HI (operand:SI)) instruction, so adding this
>> showed a problem with some of the existing simplify_const_unop cases:
>> for ffs/clz/ctz
On 08/23/11 11:52, Jakub Jelinek wrote:
> On Tue, Aug 23, 2011 at 11:35:07AM +0200, Bernd Schmidt wrote:
>>> cse_process_notes_1
>>> perhaps could be changed for VOIDmode new_rtx to try to
>>> simplify_replace_rtx it...
>>
>> Is this where the probl
Ping for the patch at
http://gcc.gnu.org/ml/gcc-patches/2011-06/msg01595.html
> This patch requires
> http://gcc.gnu.org/ml/gcc-patches/2011-05/msg02193.html
> as a prerequisite, and supersedes
> http://gcc.gnu.org/ml/gcc-patches/2011-05/msg02194.html
>
> The idea here is to allow regrename t
On 08/23/11 17:42, Jakub Jelinek wrote:
> On Tue, Aug 23, 2011 at 02:06:05PM +0200, Jakub Jelinek wrote:
>> We can remove that restriction again once CONST_INTs are no longer VOIDmode.
>>
>> Here is an untested patch, will bootstrap/regtest it now on x86_64-linux
>> and i686-linux, on c6x it should
On 08/23/11 22:23, Uros Bizjak wrote:
> On Tue, Aug 23, 2011 at 10:04 PM, Richard Henderson wrote:
>
>>> * config/i386/constraints.md (Yp): New register constraint.
>>> * config/i386/i386.md (*addhi_1): Merge with *addhi_1_lea using
>>> Yp register constraint.
>>> (*addqi_
On 08/03/11 17:38, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> +@findex simple_return
>> +@item (simple_return)
>> +Like @code{(return)}, but truly represents only a function return, while
>> +@code{(return)} may represent an insn that also performs other fu
On 08/24/11 19:17, Richard Sandiford wrote:
> OK with that change from a MIPS and rtl and perspective.
Thanks. What else is in there? Trivial x86 changes, and a slightly less
trivial but still tiny ARM bit, I suppose. Richard/Ramana?
Bernd
-linux).
Bernd
Index: gcc/ChangeLog
===
--- gcc/ChangeLog (revision 178062)
+++ gcc/ChangeLog (working copy)
@@ -1,5 +1,12 @@
+2011-08-25 Bernd Schmidt
+
+ * regrename.c (scan_rtx_reg, scan_rtx_addres
below, with extra comments. Let me know if more are needed.
> One thing though:
>
> Bernd Schmidt writes:
>> @@ -215,8 +306,9 @@ merge_overlapping_regs (HARD_REG_SET *ps
>>IOR_HARD_REG_SET (*pset, head->hard_conflicts);
>>EXECUTE_IF_SET_IN_BITMAP (&head-
On 07/18/11 18:47, Vladimir Makarov wrote:
> But I guess comb-vector is popular for a reason. We could tolerate slow
> compression time because it is done once but worse compression and
> slower access would have a really bad impact on the compiler time.
With some fixes that I need to make to the
On 08/26/11 16:32, Ramana Radhakrishnan wrote:
> On 24 August 2011 18:23, Bernd Schmidt wrote:
>> On 08/24/11 19:17, Richard Sandiford wrote:
>>> OK with that change from a MIPS and rtl and perspective.
>>
>> Thanks. What else is in there? Trivial x86 changes, and
In rest_of_reorder_blocks, we avoid reordering if
!optimize_function_for_speed_p. However, we still call
insert_section_bounary_note, which can cause problems because now, if we
have a sequence of HOT-COLD-HOT blocks, the second set of HOT blocks
will end up in the cold section. This causes assembl
On 08/29/11 11:03, Jakub Jelinek wrote:
> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01767.html
> PR middle-end/48722
> Fix RTL sharing problem with CALL_INSN_FUNCTION_USAGE
Looks OK.
Bernd
On 08/23/11 12:12, Richard Sandiford wrote:
> Ping for:
>
> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01181.html
> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01182.html
Ok.
Bernd
We currently generate
__i686.get_pc_thunk.bx:
movl(%esp), %ebx
ret
in PIC binaries. This can cause problems if the assembly output ends up
in a .S file which is then compiled again: __i686 is a predefined macro
and expands to "1". This happens in glibc when compiling csu/crti.S
On 08/29/11 18:37, H.J. Lu wrote:
> On Mon, Aug 29, 2011 at 9:36 AM, H.J. Lu wrote:
>> Doesn't Google have a patch to change it to __x86.get_pc_thunk.bx?
>>
>
> http://gcc.gnu.org/ml/gcc-patches/2011-04/msg02422.html
Cool. I guess I'll approve and commit this version, unless someone sees
a reas
With the final shrink-wrapping patch applied, I see failures in
dwarf2cfi on mips64-elf. The problem is that reorg.c uses copy_rtx to
copy instructions, and for some reason that clears the frame_related
bit. We end up with a prologue insn in a delay slot, and dwarf2cfi
disregards its effects.
I se
This is necessary when adding shrink-wrapping; otherwise dwarf2cfi sees
inconsistent information and aborts.
Tested on mips64-elf together with the rest of the shrink-wrapping
patches. Ok?
Bernd
* config/mips/mips.c (cfa_restores): New static variable.
(mips_restore_reg): Add to
This is a new version of the original 4/6 shrink wrapping patch, minus
the preliminary bits that were already approved, and with some extra bug
fixes that were discovered in the meantime. This is now mostly contained
to just function.c. I'll resubmit the other parts (i.e. exposing more
shrink-wrapp
On 08/31/11 20:43, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> This is necessary when adding shrink-wrapping; otherwise dwarf2cfi sees
>> inconsistent information and aborts.
>>
>> Tested on mips64-elf together with the rest of the shrink-wrapping
>> pa
On 08/31/11 19:43, Jeff Law wrote:
> Presumably the jump & call flags are copied as part of the
> shallow_copy_rtx call, thus removing the explicit copy is safe?
That's the conclusion I came to.
Bernd
On 08/29/11 18:02, Jeff Law wrote:
> On 08/26/11 08:47, Bernd Schmidt wrote:
>> In rest_of_reorder_blocks, we avoid reordering if
>> !optimize_function_for_speed_p. However, we still call
>> insert_section_bounary_note, which can cause problems because now, if
>> we
Shrink-wrapping tests on ARM had one additional failure, which I could
track down to a stmfd instruction being emitted where an stmhifd was
intended. The following patch fixes the testcase; full tests running
now. Ok?
Bernd
* config/arm/arm.md (push_multi): Emit predicates.
Index: gcc/co
On 08/26/11 14:57, Richard Sandiford wrote:
>> + /* There must be some kind of conflict. Set the unusable for all
>> + overlapping registers. */
>> + min_reg = chain->regno;
>> + if (incoming_nregs < 0)
>> +min_reg += incoming_nregs;
>> + max_reg = chain->regno + chain->nregs;
>> + f
The following change
2011-05-26 Rainer Orth
PR gcov-profile/48845
causes testsuite failures on C6X. Specifically,
@@ -495,11 +495,16 @@ proc check_profiling_available { test_wh
# These conditions depend on the argument so examine them before
# looking at the cache va
On 08/31/11 20:43, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> This is necessary when adding shrink-wrapping; otherwise dwarf2cfi sees
>> inconsistent information and aborts.
>>
>> Tested on mips64-elf together with the rest of the shrink-wrapping
>> pa
On 09/01/11 21:19, Richard Sandiford wrote:
> Richard Sandiford writes:
>> Gah, my bad, sorry. I'd forgotten mipsisa32-elf is EABI32
>> rather than o32. mips-elf with -mips32/-mips16 would test
>> what I was after.
>
> Sigh. Obviously not my day. I just remembered that the default
> mips-elf
On 09/02/11 12:35, Ramana Radhakrishnan wrote:
> On 1 September 2011 12:50, Bernd Schmidt wrote:
>> Shrink-wrapping tests on ARM had one additional failure, which I could
>> track down to a stmfd instruction being emitted where an stmhifd was
>> intended. The following pat
Scheduling floating point insns is broken on C6X; unfortunately in a way
that the simulator doesn't detect.
We let the sched DFA pick a valid schedule, and later on we try to
reconstruct a valid unit assignment. This does not work if an insn has
multiple units it can choose, and that insn's reserv
On 09/01/11 16:16, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> On 08/26/11 14:57, Richard Sandiford wrote:
>>> Wouldn't a reverse post-order (inverted_post_order_compute) allow even
>>> more pre-opening (as well as being less code)?
>>
>> I c
This showed up with a coldfire-linux toolchain. get_condition can return
NULL in some cases when the condition is reversed and there are float
modes involved; in that case we will move instructions in between a cc0
user and setter.
This patch fixes it. Tested on cris-elf, since I currently have no
Here's a new version, which adds support for mips16 and tries to avoid
the window with the frame pointer restore.
Testing mips16 is problematic, all the execute tests fail before and
after - I interpret one of your earlier mails to say that this is
expected. There are no new compilation failures w
Testing with the shrink-wrapping patch added reveals a problem with the
mips16 "save" insn: sometimes we store registers that shouldn't be
considered saved registers; we have to clear RTX_FRAME_RELATED_P for
these. Testing in progress with mips-elf, "ips16/arch=mips32r2/abi=32"
and some other multi
On 09/06/11 12:37, Richard Sandiford wrote:
> Maybe here:
[...]
> it would be better to use:
>
> this_info = (struct bb_rename_info *) bb1->aux;
>
> if (this_info == NULL)
> continue;
>
> so that we don't care which order the rename_info array is. You could
> then keep the original f
On 09/07/11 10:28, Ramana Radhakrishnan wrote:
> On 2 September 2011 12:42, Bernd Schmidt wrote:
>> On 09/02/11 12:35, Ramana Radhakrishnan wrote:
>>> On 1 September 2011 12:50, Bernd Schmidt wrote:
>>>> Shrink-wrapping tests on ARM had one additional failure, whic
On 09/08/11 16:08, Richard Sandiford wrote:
> Also, this:
>
> @@ -10442,7 +10495,7 @@ mips_expand_epilogue (bool sibcall_p)
> }
>else
> {
> - unsigned int regno;
> + rtx pat;
>
> /* When generating MIPS16 code, the normal
>mips_for_each_saved_g
On 09/06/11 23:56, Maxim Kuvyrkov wrote:
> I agree. I would rather remove the entirety of haifa-sched.c:
> check_cfg(); scheduler is not the right place for checking
> consistency of CFG. Check_cfg() was useful for debugging scheduler
> patches, but now it is more of maintainance overhead.
>
> D
On 09/08/11 16:08, Richard Sandiford wrote:
> I suppose I still don't get why this is OK but this:
>
>> @@ -10324,12 +10350,26 @@ mips_expand_epilogue (bool sibcall_p)
>>if (!TARGET_MIPS16)
>> target = stack_pointer_rtx;
>>
>> - emit_insn (gen_add3_insn (target, base, adjust));
On 09/11/11 11:03, Richard Sandiford wrote:
> Richard Sandiford writes:
>> I think I need to play around with it a bit before I understand enough
>> to review. I'll try to find time this weekend.
>
> Does the attached patch look OK? It should fix a couple of things.
Sure!
Bernd
On 09/12/11 17:13, Jakub Jelinek wrote:
> dwarf2cfi.c generates sometimes different .eh_frame with/without
> -fvar-tracking-assignments. The problem is that in add_cfis_to_fde
> when adding NOTE_INSN_CFI_LABEL notes there is a scan to find consecutive
> NOTE_INSN_CFI notes, but if there are any va
On 09/01/11 15:57, Richard Sandiford wrote:
> add_to_hard_reg_set (pused, GET_MODE (x), REGNO (x));
Done.
> Strange line break, and comment doesn't match code (no "changed" variable).
Fixed.
>> +/* Return true if INSN requires the stack frame to be set up.
>> + PROLOGUE_USED contains the hard
On 09/13/11 10:35, Richard Sandiford wrote:
>> Also, it turns out I need to pretend that trap_if requires the prologue
>> due to the testcase you also ran across, so a for_each_rtx walk is
>> required anyway.
>
> Why does TRAP_IF inherently need a prologue though? The CFA information
> should be
On 09/13/11 13:37, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> On 09/13/11 10:35, Richard Sandiford wrote:
>>>> Also, it turns out I need to pretend that trap_if requires the prologue
>>>> due to the testcase you also ran across, so a for_each_rtx walk is
On 09/13/11 15:05, Richard Sandiford wrote:
> It just feels like checking for trap_if or turning off cross-jumping
> are working around problems in the representation of shrink-wrapped
> functions. There should be something in the IL to say that those
> two blocks cannot be merged for CFI reasons.
On 09/13/11 19:49, Richard Sandiford wrote:
> As per the subject. Tested by making sure that there were no new
> warnings building bfin-elf, and that there were no changes in the
> assembly output for the C and C++ testsuite. OK to install?
Sure!
Bernd
C6X has some rather nifty hardware support for modulo scheduling.
Consider the following loop:
.L13:
ldh .d1t1 *++A5[1], A7
|| add .s1 -1, A0, A0
ldh .d2t1 *B5++[1], A8
nop 1
[A0]b .s1 .L13
This makes haifa-sched capable of acting like a modulo-scheduler in
cooperation with a caller (expected to be in a port's md_reorg). As
explained in [0/4], most of the necessary code is already there in form
of the delay slot support that was added for C6X.
The main new entry point is set_modulo_p
This is just some code rearrangement to make it possible for c6x.c to
call schedule_ebbs_init, schedule_ebb and schedule_ebbs_finish.
Bernd
* sched-ebb.c (schedule_ebb): No longer static. Remove declaration.
New arg modulo_scheduling. All callers changed. Move note handling
This fixes an oversight that led to a compare-debug failure in the
testsuite with the other changes applied. We really don't care if a
DEBUG_INSN uses the iteration register or not.
Will commit soon as obvious.
Bernd
* hw-doloop.c (scan_loop): Compute register usage only for non-debug
This is the final piece that makes use of the new haifa-sched
functionality in c6x.c. It also makes use of the hw-doloop code which I
adapted from Blackfin a while ago.
After finding a candidate loop, the hwloop_optimize function unrolls it
to a suitable degree, then tries successive values for II
On 09/14/11 11:03, Richard Sandiford wrote:
> ...I didn't see from an admittedly quick read of the patch how you
> handle memory disambiguation between iterations. If a loop includes:
>
> lb $3,($4)
> sb $5,1($4)
>
> then the two instructions can be reordered by normal ebb scheduling,
While testing the altest iteration of shrink-wrapping on mips-elf, a new
failure showed up in gcc.dg/pr43139.c. When restoring floating-point
registers, we attach REG_CFA_RESTORE notes for DFmode registers, but the
dwarf2cfi code only records a single regno for such a multiword hard reg.
Fixed wit
On 09/17/11 09:16, Alan Modra wrote:
> This patch series adds shrink-wrap support for PowerPC. The patches
> are on top of Bernd's "Initial shrink-wrapping patch":
> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg02557.html, but with the
> tm.texi patch applied to tm.texi.in. Bootstrapped and regre
On 09/19/11 02:16, Alan Modra wrote:
> On Sat, Sep 17, 2011 at 03:26:21PM +0200, Bernd Schmidt wrote:
>> On 09/17/11 09:16, Alan Modra wrote:
>>> This patch series adds shrink-wrap support for PowerPC. The patches
>>> are on top of Bernd's "Initial shrink-wr
On 09/20/11 19:09, Tom de Vries wrote:
>
> * final.c (final): Handle if JUMP_LABEL is not LABEL_P.
This is ok.
Bernd
On 09/16/11 17:14, Richard Sandiford wrote:
> Ping for this patch to emit_library_call_value_1:
>
> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg00735.html
>
> which fixes a bootstrap failure on MIPS since:
>
> http://gcc.gnu.org/ml/gcc-patches/2011-06/msg02341.html
>
> Tested on mips64
On 09/15/11 21:42, Richard Henderson wrote:
> On 09/14/2011 06:12 PM, Bernd Schmidt wrote:
>> + unsigned int orig_regno = REGNO (reg);
>> + int nregs = hard_regno_nregs[orig_regno][GET_MODE (reg)];
>> + while (nregs-- > 0)
>
> The rest of the file seems to u
This fixes a reload problem found by Tom de Vries while testing another
patch. An analysis of the problem is in PR50249. Essentially, we have
multiple reloads with the same type, for the same operand, feeding each
other and reusing the same register:
Reload 1: reload_in (SI) = (reg/f:SI 10 sl [588
On 09/01/11 15:20, Bernd Schmidt wrote:
> The following change
>
> 2011-05-26 Rainer Orth
> PR gcov-profile/48845
>
> causes testsuite failures on C6X. Specifically,
>
> @@ -495,11 +495,16 @@ proc check_profiling_available { test_wh
> # The
On 09/21/11 19:33, Richard Henderson wrote:
> Why, then, is this the only place in dwarf2cfi that needs to handle
> registers via a loop over nregs? It seems to me that we should either
> be handling multi-register spans everywhere or nowhere.
>
> Because alternately, this could be a bug in your
On 09/27/11 00:32, Alan Modra wrote:
> On Mon, Sep 26, 2011 at 11:22:54PM +0930, Alan Modra wrote:
>> Two regressions appeared due to a problem in the shrink-wrap code.
>
> These two.
> +FAIL: g++.dg/torture/pr46111.C -O1 (internal compiler error)
> +FAIL: gcc.dg/autopar/pr46099.c (internal comp
On 09/27/11 02:11, Alan Modra wrote:
> On Tue, Sep 27, 2011 at 12:39:36AM +0200, Bernd Schmidt wrote:
>> On 09/27/11 00:32, Alan Modra wrote:
>>> On Mon, Sep 26, 2011 at 11:22:54PM +0930, Alan Modra wrote:
>>>> Two regressions appeared due to a problem in the shrin
On 09/25/11 19:27, Richard Sandiford wrote:
> The store itself can still be a single SDC1 instruction, so we should
> generate the same notes regardless of mips_split_64bit_move_p.
>
> If that's right, then how about the patch below (tested on
> mips64-linux-gnu, but without the shrink-wrap patche
Ping:
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00811.html
Bernd
On 09/15/11 00:51, Richard Henderson wrote:
> On 09/13/2011 08:36 AM, Bernd Schmidt wrote:
>> On 09/13/11 15:05, Richard Sandiford wrote:
>>> It just feels like checking for trap_if or turning off cross-jumping
>>> are working around problems in the representation of s
On 09/29/11 11:26, Richard Guenther wrote:
> Maybe that was the PR the patch is about, but surely we can't treat
> a memcpy (p, ..) like *p. Which means we'd use the declared type
> of p only. And we can do so only for parameters (intermediate conversions
> are dropped), which would make the case
On 09/29/11 23:32, Vladimir Makarov wrote:
> Bernd, sorry for the delay.
No problem.
> I thought for long time about this approach because we already have
> selective scheduler which with some modifications could be used for
> this. Selective scheduler was implemented for Itanium, designed to
Hi Nick,
>> Experiments show that the
>> existing multi-if-block support isn't terribly effective on FRV;
>> before-after comparisons show that by turning it off, there are three
>> spots in gcc that are meaningfully changed, and below 20 in the C
>> benchmarks of SPEC2k.
>>
>> FRV also doesn't bu
The main purpose of this patch is to move some declarations to a new
file, regrename.h, and make regrename_analyze and do_replace callable
from elsewhere. The second patch will add code to c6x.c to make use of
this from the modulo-scheduling code.
This also adds a small amount of new functionality
This is the final piece which makes use of all the previous regrename
patches, and transforms this loop (which occurs in a popular embedded
benchmark):
sploop 2
.L4:
ldh .d1t1 *A6++[1], A7
ldh .d1t1 *++A5[1], A8
nop 4
On 10/03/11 10:23, Richard Sandiford wrote:
> Bernd Schmidt writes:
>> On 09/14/11 11:03, Richard Sandiford wrote:
>>> ...I didn't see from an admittedly quick read of the patch how you
>>> handle memory disambiguation between iterations. If a loop includes:
>
On 10/03/11 16:21, Richard Sandiford wrote:
> so inter-iteration dependencies aren't a problem. Whereas I thought your
> modulo instruction did:
>
> A1
> B1 A2
> C1 B2 A3
> D1 C2 B3
> D2 C3
> D3
>
> so if D1 writes to memory that A2 (but not A1) _might_ load, then t
On 10/03/11 16:21, Richard Sandiford wrote:
> I'm not sure I follow. Unrolling a loop {A, B, C, D} gives:
>
> A1
> B1
> C1
> D1
> A2
> B2
> C2
> D2
> A3
> B3
> C3
> D3
>
> so inter-iteration dependencies aren't a problem.
Expanding on
On 10/03/11 17:26, Richard Sandiford wrote:
> are necessarily equivalent to:
>
> Loop 3:
> A
> B A
> C B A
> D C B A
> A D C B
> B A D C
> C B A D
> D C B A
> D C B
> D C
> D
Sort of. The insns wouldn't rotate like this in a modulo-scheduled loop.
> Is that righ
On 10/03/11 13:28, Basile Starynkevitch wrote:
> Regarding this shrink-wrapping patch, I would suggest to describe, in a
> comments of one or two sentences, what shkink-wrapping means in the context
> of GCC.
See the documentation part of the patch.
Bernd
On 10/03/11 17:57, Paul Brook wrote:
> Patch below makes gcc emit the resuired assembly directives for c6x unwinding
> tables, same as ARM and IA64. This fixes most of the unwinding related
> failures.
Most?
> * config/c6x/c6x.c (c6x_asm_emit_except_personality,
> c6x_asm_init_sect
On 10/03/11 19:23, Richard Sandiford wrote:
> Bernd Schmidt writes:
>>> Reason for asking is that (AIUI) SMS used to use stronger memory
>>> disambiguation, but had to pull back to something more conservative
>>> for similar reasons.
>>
>> Pointers? All I
On 10/03/11 20:12, Richard Sandiford wrote:
> But what I'm trying to say is that you're not just doing loop
> unrolling followed by scheduling. You're doing loop unrolling,
> followed by scheduling, followed by an overlapping of the unrolled loop
> iterations. It just felt strange that the overla
On 09/25/11 19:16, Richard Sandiford wrote:
> The last bit is indirect, via a new HARD_REG_SET called operand_reg_set.
> And this set is the reason why I'm sending the patch now. The MIPS16 port
> has always had a problem with the HI and LO registers: they can only be
> set by multiplication and d
On 09/30/11 18:51, Richard Henderson wrote:
> Please do leave out RETURN_ADDR_REGNUM for now. If you remember why,
> then you could bring it back alongside the patch for the ARM backend.
Changed.
> As for the i386 backend changes, not an objection per se, but I'm
> trying to understand why we n
On 10/05/11 17:13, Richard Guenther wrote:
> On Wed, Oct 5, 2011 at 12:29 AM, Richard Henderson wrote:
>> On 10/04/2011 03:10 PM, Bernd Schmidt wrote:
>>> * doc/invoke.texi (-fshrink-wrap): Document.
>>> * opts.c (default_options_table): Add it.
>>&
On 10/05/11 18:21, Richard Henderson wrote:
> On 10/05/2011 08:59 AM, Bernd Schmidt wrote:
>> Bootstrapping the following now. Ok? (Alternatively, could keep the
>> redzone logic, but make it depend on !flag_shrink_wrap).
>
> It's a good space-saving optimization, that r
On 10/05/11 00:29, Richard Henderson wrote:
> As a followup, I think this option needs to be disabled for profiling
> and profile_after_prologue. Should be a mere matter of frobbing the
> options at startup.
The other code seems to test crtl->profile rather than an option flag,
so how's this? Boo
This adds a little mini-pass to shrink-wrapping, to eliminate a common
case that often makes shrink-wrapping unavailable. If a move insn copies
an argument registers to a call-saved register, the prologue must be
emitted before this insn. We should therefore try to delay such moves
for as long as p
On 10/05/11 23:23, Steven Bosscher wrote:
> On Wed, Oct 5, 2011 at 10:48 PM, Bernd Schmidt
> wrote:
>> Bootstrapped and tested on i686-linux. Ok?
>
>> +/* Return true if BB has any active insns. */
>> +static bool
>> +bb_active_p (basic_block bb)
>>
On 10/06/11 01:04, Ian Lance Taylor wrote:
> On Wed, Oct 5, 2011 at 10:17 AM, Bernd Schmidt
> wrote:
>>
>> I've committed the following after a x86_64-linux bootstrap.
>
> This patch appears to have broken the Go bootstrap when compiling a C
> file in lib
On 10/06/11 05:17, Ian Lance Taylor wrote:
> Thinking about it I think this is the wrong approach. The -fsplit-stack
> code by definition has to wrap the entire function and it can not modify
> any callee-saved registers. We should do shrink wrapping before
> -fsplit-stack, not the other way arou
ernd
Index: gcc/ChangeLog
===
--- gcc/ChangeLog (revision 179606)
+++ gcc/ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2011-10-06 Bernd Schmidt
+
+ PR target/49049
+ * config/arm/arm.md (arm_subsi3_insn): Los
On 10/06/11 01:47, Bernd Schmidt wrote:
> This appears to be because the split prologue contains a jump, which
> means the find_many_sub_blocks call reorders the block numbers, and our
> indices into bb_flags are off.
Testing of the patch completed - ok? Regardless of split-stack it see
On 10/06/11 17:57, Ian Lance Taylor wrote:
> There is absolutely no reason to try to shrink wrap that code. It will
> never help. That code always has to be first. It especially has to be
> first because the gold linker recognizes the prologue specially when a
> split-stack function calls a non-
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