On Thu, Nov 12, 2015 at 8:52 AM, Michael Matz wrote:
> Hello,
>
> this new pass implements loop iteration space splitting for loops that
> contain a conditional that's always true for one part of the iteration
> space and false for the other, i.e. such situations:
>
> for (i = beg; i < end; i++)
On Wed, Dec 2, 2015 at 5:23 AM, Michael Matz wrote:
> Hi,
>
> On Tue, 1 Dec 2015, Jeff Law wrote:
>
>> > So, okay for trunk?
>> -ENOPATCH
>
> Sigh :)
> Here it is.
I found one problem with it.
Take:
void f(int *a, int M, int *b)
{
for(int i = 0; i <= M; i++)
{
if (i < M)
a[i
On Tue, Jul 26, 2016 at 4:32 AM, Richard Biener
wrote:
> On Mon, Jul 25, 2016 at 10:57 PM, Andrew Pinski wrote:
>> On Wed, Dec 2, 2015 at 5:23 AM, Michael Matz wrote:
>>> Hi,
>>>
>>> On Tue, 1 Dec 2015, Jeff Law wrote:
>>>
>>>> > So, o
On Mon, Aug 1, 2016 at 12:15 AM, Prathamesh Kulkarni
wrote:
> Hi Richard,
> The attached patch tries to fold strlen (s) eq/ne 0 to *s eq/ne 0 on GIMPLE.
> I am not sure where was the ideal place to put this transform in and ended up
> adding it to strlen_optimize_stmt().
> Does that look OK ?
I s
On Mon, Aug 1, 2016 at 12:22 AM, Andrew Pinski wrote:
> On Mon, Aug 1, 2016 at 12:15 AM, Prathamesh Kulkarni
> wrote:
>> Hi Richard,
>> The attached patch tries to fold strlen (s) eq/ne 0 to *s eq/ne 0 on GIMPLE.
>> I am not sure where was the ideal place to put this t
On Tue, Nov 1, 2016 at 11:08 AM, Andrew Pinski wrote:
> On Tue, Nov 17, 2015 at 2:10 PM, Andrew Pinski wrote:
>> Since ThunderX T88 pass 1 (variant 0) is a ARMv8 part while pass 2 (variant
>> 1)
>> is an ARMv8.1 part, I needed to add detecting of the variant also for this
olean type if it is a comparison.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* tree-vrp.c (simplify_stmt_using_ranges): Use boolean_type_node
for the EQ_EXPR.
Index: tree-
On Tue, Nov 29, 2016 at 1:09 AM, Kyrill Tkachov
wrote:
> Hi all,
>
> This ICE only occurs on big-endian ILP32 -fpie code. The expansion code
> generates the invalid load:
> (insn 6 5 7 (set (reg/f:SI 76)
> (unspec:SI [
> (mem/u/c:SI (lo_sum:SI (nil)
>
On Wed, Nov 30, 2016 at 1:04 AM, Christophe Lyon
wrote:
> Hi Tamar,
>
>
> On 29 November 2016 at 14:54, James Greenhalgh
> wrote:
>> On Tue, Nov 29, 2016 at 01:48:22PM +, Kyrill Tkachov wrote:
>>>
>>> On 29/11/16 09:50, Tamar Christina wrote:
>>> >Hi All,
>>> >
>>> >The new patch contains th
On Thu, Dec 8, 2016 at 2:55 PM, Josh Conner wrote:
> This patch adds support to gcc for the Fuchsia OS
> (https://fuchsia.googlesource.com/).
>
> OK for mainline?
A few comments:
> +/* Build with PIC by default. */
> +#undef CC1_SPEC
> +#define CC1_SPEC "%{!fno-pic:%{!fno-PIC:%{!fpic:%{!fPIC: -
On Sat, Nov 26, 2016 at 1:54 PM, Andrew Pinski wrote:
> On Tue, Nov 1, 2016 at 11:08 AM, Andrew Pinski wrote:
>> On Tue, Nov 17, 2015 at 2:10 PM, Andrew Pinski wrote:
>>> Since ThunderX T88 pass 1 (variant 0) is a ARMv8 part while pass 2 (variant
>>> 1)
>>>
On Thu, Nov 10, 2016 at 6:58 PM, Andrew Pinski wrote:
> On Tue, Oct 25, 2016 at 3:25 PM, Matthias Klose wrote:
>> On 07.10.2016 23:08, Andrew Pinski wrote:
>>> Hi,
>>> This patch adds ilp32 multi-arch support. This is needed to support
>>> multi-arc
On Mon, Dec 12, 2016 at 3:29 AM, Tamar Christina
wrote:
> Hi Andrew,
>
> These should be fixed now.
Yes they are fixed.
Thanks,
Andrew
>
> Thanks,
> Tamar
>
> ________
> From: Andrew Pinski
> Sent: Wednesday, December 7, 2016 4:
On Mon, Dec 12, 2016 at 11:12 AM, Nathan Sidwell wrote:
> This patch fixes an ICE in a checking build where structural_comptypes
> disagrees with TYPE_CANONICAL.
>
> An (implicit) template alias has a different TYPE_TI_TEMPLATE to the thing
> its aliasing. That make structural comparison think it
on aarch64 with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/value-unwind.h: New file.
* config.host (aarch64*-*-*): Add aarch64/value-unwind.h to tm_file.
Index: libgcc/config.host
===
--- libgcc/config.host (revis
On Wed, Apr 27, 2016 at 2:13 PM, Andrew Pinski wrote:
> Hi,
> AARCH64 ILP32 is like x32 where UNITS_PER_WORD > sizeof(void*) so we
> need to define REG_VALUE_IN_UNWIND_CONTEXT for ILP32. This fixes
> unwinding through the signal handler. This is independent of the ABI
>
On Fri, May 13, 2016 at 12:58 PM, Richard Biener
wrote:
> On May 13, 2016 9:18:57 PM GMT+02:00, Cesar Philippidis
> wrote:
>>The cse_sincos pass tries to optimize sequences such as
>>
>> sin (x);
>> cos (x);
>>
>>into a single call to sincos, or cexpi, when available. However, the
>>nvptx targ
On Sun, May 15, 2016 at 12:03 PM, Gerald Pfeifer wrote:
> While not a bug according to the language of the C++ standard, this
> causes dozens of warnings when building GCC with clang, and there is
> not benefit of mixing struct and class like this.
>
> Mike, when I had a similar case a while ago y
On Tue, May 17, 2016 at 2:10 PM, Cesar Philippidis
wrote:
> On 05/13/2016 01:13 PM, Andrew Pinski wrote:
>> On Fri, May 13, 2016 at 12:58 PM, Richard Biener
>> wrote:
>>> On May 13, 2016 9:18:57 PM GMT+02:00, Cesar Philippidis
>>> wrote:
>>>> Th
On Wed, Aug 12, 2015 at 6:16 PM, Matthew Wahab
wrote:
> ARMv8.1 adds instructions for atomic compare-and-swap with optional
> memory ordering specifiers. This patch adds tests for the
> compare-and-swap instructions as two files. The first is support code to
> run the test with a range of types an
On Mon, Aug 17, 2015 at 5:20 PM, Kyrill Tkachov
wrote:
> Hi Alexandre,
>
> On 17/08/15 03:56, Alexandre Oliva wrote:
>>
>> On Aug 16, 2015, Andreas Schwab wrote:
>>
>>> Alexandre Oliva writes:
On Aug 15, 2015, Andreas Schwab wrote:
> FAIL: gcc.target/aarch64/target_attr_crypt
AARCH64_FUSION_PAIR.
commit 61a89a2f6939fbc97e18d2137daba7f450ef76b2
Author: Andrew Pinski
Date: Wed Aug 19 01:15:00 2015 -0700
Remove index from AARCH64_EXTRA_TUNING_OPTION
Instead of doing an explict index in aarch64-tuning-flags.def, we
should have an enum which does the
to AARCH64_FUSION_PAIR.
* config/aarch64/aarch64.c: Remove the last argument to AARCH64_FUSION_PAIR.
commit 69a828bfdcd2f4de2c9d4f27e3878213d04ed353
Author: Andrew Pinski
Date: Tue Aug 18 22:13:32 2015 -0700
Remove index from AARCH64_FUSION_PAIR
Instead of doing an explict
On Wed, Aug 19, 2015 at 7:39 PM, James Greenhalgh
wrote:
> On Wed, Aug 19, 2015 at 12:11:04PM +0100, Andrew Pinski wrote:
>> Instead of doing an explicit index in aarch64-fusion-pairs.def, we
>> should have an enum which does the index instead. This allows
>> y
On Wed, Aug 19, 2015 at 11:39 PM, James Greenhalgh
wrote:
>
> Hi,
>
> This patch has been sitting in my tree for a while - it comes in handy
> when trying out bootstrap or test with -mcpu values like -mcpu=cortex-a72
> with a system assmebler which trails trunk binutils.
>
> Essentially, we rewrit
does
> not understand.
>
> Ok?
+ modified string, which seems much worse! */
+ char *output = (char*) xmalloc (sizeof (*output)
+ * (outstr.length () + 1));
+ strcpy (output, outstr.c_str ());
Why not just:
char *output = xstrdup (outstr.c_str ());
Or at least use XNEWVEC instea
shifted value on the index instead
Rewrite AARCH64_FUSE_ALL to be based on the end index.
of the argument to AARCH64_FUSION_PAIR.
* config/aarch64/aarch64.c: Remove the last argument to AARCH64_FUSION_PAIR.
commit 8a02e03360852b9261d45528384fa8b87c673e53
Author: Andrew Pinski
Date
Just like the patch for AARCH64_FUSION_PAIR, this is a patch for
AARCH64_EXTRA_TUNING_OPTION. Note I tested this patch on top of the
patch for AARCH64_EXTRA_TUNING_OPTION.
Changes in v2:
Remove the hack for AARCH64_EXTRA_TUNE_ALL.
Remove index from AARCH64_EXTRA_TUNING_OPTION
Instead of
On Thu, Aug 20, 2015 at 12:08 AM, James Greenhalgh
wrote:
> On Wed, Aug 19, 2015 at 05:00:14PM +0100, Andrew Pinski wrote:
>> Just like the patch for AARCH64_FUSION_PAIR, this is a patch for
>> AARCH64_EXTRA_TUNING_OPTION. Note I tested this patch on top of t
TRY16 ((x)) CASE_ENTRY16 ((x)+16)
#define CASE_ENTRY64 (x) CASE_ENTRY32 ((x)) CASE_ENTRY32 ((x)+32+1)
#define CASE_ENTRY128 (x) CASE_ENTRY64 ((x)) CASE_ENTRY16 ((x)+64+1)
#define CASE_ENTRY256 (x) CASE_ENTRY128 ((x)) CASE_ENTRY128 ((x)+128+1)
And then use
CASE_ENTRY256 (1)
You can do the same trick to reduce the size of CASE_ENTRY too.
Thanks,
Andrew Pinski
On Tue, Aug 25, 2015 at 5:50 PM, Andrew Pinski wrote:
> On Tue, Aug 25, 2015 at 5:37 PM, Andre Vieira
> wrote:
>> Conditional branches have a maximum range of [-1048576, 1048572]. Any
>> destination further away can not be reached by these.
>> To be able to have cond
hing
> (rather than using costs inconsistently all over the place). But that's a
> different
> discussion...
This is the pattern which I have in my tree (I need someone here to
submit it still):
(define_insn "*and3_ze_nr_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(zero_extract:GPI ; loc size pos
(match_operand:GPI 0 "register_operand" "r")
(match_operand:GPI 1 "const_int_operand" "n")
(match_operand:GPI 2 "const_int_operand" "n"))
(const_int 0)))]
"aarch64_bitmask_imm HOST_WIDE_INT_1U << UINTVAL (operands[1]))
- 1) << UINTVAL (operands[2])),mode)"
{
unsigned HOST_WIDE_INT value = (((HOST_WIDE_INT_1U << UINTVAL
(operands[1])) - 1) << UINTVAL (operands[2]));
operands[1] = GEN_INT (value);
return "tst\\t%0, %1";
}
[(set_attr "type" "logics_reg")]
)
--- CUT ---
And then under case COMPARE part of rtx_costs:
/* CC_NZmode supports zero extract for free. */
if (GET_MODE (x) == CC_NZmode && GET_CODE (op0) == ZERO_EXTRACT)
op0 = XEXP (op0, 0);
And in aarch64_select_cc_mode:
if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
&& (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND
|| GET_CODE (x) == NEG || GET_CODE (x) == ZERO_EXTRACT))
return CC_NZmode;
Note I also have the following too, to solve the case where
zero_extend is need being used in some cases for ands (yes this shows
up mostly right after returns from functions)
(define_insn "*andsi3_compare0_uxtw"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2]
""
"ands\\t%w0, %w1, %w2"
[(set_attr "type" "logics_reg,logics_imm")]
Thanks,
Andrew Pinski
>
> Wilco
>
>
On Thu, Sep 3, 2015 at 11:20 PM, Bill Schmidt
wrote:
> Hi,
>
> It was pointed out to me recently that multiplying two vector chars is
> performed using scalarization, even though we have hardware support for
> byte multiplies in vectors. This patch adds an expansion for mulv16qi3
> to correct thi
On Wed, Sep 9, 2015 at 11:11 PM, Mike Stump wrote:
> On Sep 3, 2015, at 9:45 AM, Jonathan Roelofs
> wrote:
>> Moral of the story is: these tests fail in our environment, but only because
>> the regexes do not expect the presence of the ansi color codes, and we can't
>> trick the runtime into n
rch64-linux-gnu.
> Ok for trunk?
I really think this kind of special casing is not correct and does not
belong in the compiler. The main reason it complicates the back-end
more than the benefit of easier of reading the assembly code.
Thanks,
Andrew Pinski
>
> Thanks,
> Kyrill
>
On Fri, Nov 4, 2016 at 7:08 AM, Marc Glisse wrote:
> Ping https://gcc.gnu.org/ml/gcc-patches/2016-10/msg02220.html
I think this is obvious.
Thanks,
Andrew
>
>
> On Thu, 27 Oct 2016, Marc Glisse wrote:
>
>> Hello,
>>
>> some optimization patch I was working on simplified __TMC_END__ -
>> __TMC_L
/On Wed, Nov 2, 2016 at 3:54 AM, James Greenhalgh
wrote:
> On Tue, Nov 01, 2016 at 11:08:53AM -0700, Andrew Pinski wrote:
>> On Tue, Nov 17, 2015 at 2:10 PM, Andrew Pinski wrote:
>> > Since ThunderX T88 pass 1 (variant 0) is a ARMv8 part while pass 2
>> > (variant 1)
otstrap with the following options:
--with-cpu=thunderx+lse --enable-languages=c,c++,fortran,go
--disable-werror --with-sysroot=/ --enable-plugins
--enable-gnu-indirect-function
I have not tried removing the +lse part though
Thanks,
Andrew Pinski
>
> Thanks,
> Kugan
>
>
On Wed, Nov 9, 2016 at 12:01 AM, kugan
wrote:
> Hi Andrew,
>
> On 09/11/16 17:02, Andrew Pinski wrote:
>>
>> Either this patch or the patch for "Handle unary pass-through jump
>> functions for ipa-vrp" caused a bootstrap failure on
>> aarch64-linux-gnu.
>>
>>
>> On 31/10/16 11:54, Kyrill Tkachov wrote:
>>>
>>>
>>> On 24/10/16 17:15, Andrew Pinski wrote:
>>>>
>>>> On Mon, Oct 24, 2016 at 7:27 AM, Kyrill Tkachov
>>>> wrote:
>>>>>
>>>>> Hi
On Thu, Nov 10, 2016 at 6:25 AM, Kyrill Tkachov
wrote:
> Hi all,
>
> This patch implements the new separate shrink-wrapping hooks for aarch64.
> In separate shrink wrapping (as I understand it) we consider each register
> save/restore as
> a 'component' that can be performed independently of the o
On Wed, Nov 9, 2016 at 2:13 PM, Pat Haugen wrote:
> The following fixes a problem introduced by my earlier loop unroller patch,
> https://gcc.gnu.org/ml/gcc-patches/2016-09/msg01612.html. In instances where
> the niter expr is not reliable we need to still emit an initial peel copy of
> the loo
ested on ThunderX on aarch64-linux-gnu with no
regressions and making sure /proc/cpuinfo is not read (by using
strace).
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-option-extensions.def: Document extra
argument to AARCH64_OPT_EXTENSION. Update for the extra argument for
all of t
On Tue, Oct 25, 2016 at 3:25 PM, Matthias Klose wrote:
> On 07.10.2016 23:08, Andrew Pinski wrote:
>> Hi,
>> This patch adds ilp32 multi-arch support. This is needed to support
>> multi-arch on Debian like systems.
>>
>> OK? Bootstrapped and tested on aarc
On Fri, Nov 11, 2016 at 7:59 AM, Andreas Tobler wrote:
> On 11.11.16 11:06, Richard Earnshaw wrote:
>>
>> On 11/11/16 02:56, Andrew Pinski wrote:
>>>
>>> As I mentioned in my other emails, parsing /proc/cpuinfo has one issue
>>> is that the current parsi
On Fri, Oct 7, 2016 at 1:01 AM, Kyrill Tkachov
wrote:
> Hi Andrew,
>
>
> On 24/09/16 06:46, Andrew Pinski wrote:
>>
>> Hi,
>>As reported in PR 61367, the aarch64 back-end is too verbose when it
>> is dealing with the cost model. I tend to agree, no othe
enabled.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-option-extensions.def (LSE): Change
FEAT_STRING to "atomics".
Index: aarch64-option-extensions.def
===
--- aarch64-option-extensions.def (revis
On Thu, Dec 17, 2015 at 12:58 AM, Yury Gribov wrote:
> Some obvious symmetry fixes.
>
> Cc-ing
> * Andrey (Belevantsev) for bb_top_order_comparator
> * Andrew (MacLeod) for compare_case_labels
> * Andrew (Pinski) for resort_field_decl_cmp
IIRC this was actually not written by
On Thu, Dec 17, 2015 at 5:00 PM, Bernd Schmidt wrote:
> This is a small problem found by a static analyzer, a function in bt-load
> can in theory return the address of a local variable.
>
> Bootstrapped and tested on x86_64-linux, ok?
Except PATTERN (insn) will never be a REG.
The only case where
On Fri, Dec 11, 2015 at 11:54 AM, Andrew Pinski wrote:
> Hi,
> The Linux kernel calls lse as atomics in /proc/cpuinfo. We should
> change aarch64-option-extensions.def to take that into account.
>
> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions
> and
Hi,
With LSE enabled by default a few failures in libgomp happen.
The shortest testcase I came up with was:
extern void abort (void);
int x = 6;
int f(void) __attribute__((noinline,noclone));
int f(void)
{
return 32;
}
int
main ()
{
int v, l = 2, s = 1;
x = f();
#pragma omp atomic capture
r any such global variables, and undoing the
> conversion where necessary. Bootstrapped and ran Go testsuite on
> x86_64-pc-linux-gnu. Committed to mainline and gccgo branch.
VIEW_CONVERT_EXPR on different size types is invalid for GCC's IR.
So this patch cause other issues.
Thanks,
On Tue, Jan 5, 2016 at 2:00 PM, Evandro Menezes wrote:
> Hi, Wilco.
>
> On 12/15/2015 04:32 AM, Wilco Dijkstra wrote:
>>>
>>> -Original Message-
>>> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
>>> Sent: 17 November 2015 18:36
>>> To: gcc-patches@gcc.gnu.org
>>> Subject: [PATCH 2/4
bout doing this at
the time I added Octeon 3 support.
Thanks,
Andrew Pinski
>
> gcc:
> 2016-01-09 Joseph Myers
>
> * config/mips/mips.h (ISA_HAS_PAIRED_SINGLE): Require
> !TARGET_OCTEON.
>
> gcc/testsuite:
> 2016-01-09 Joseph Myers
>
>
? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
c-family/ChangeLog:
* c-opts.c (c_common_post_options): Move the error message about "two
or more source files" such that it is unconditional.
Index: c-famil
mems. It will do a
peephole of two volatile mems into a pair which is not correct as the
order in the architecture is not defined and might even swap the order
of the load/store incorrectly.
I noticed this when I was merging in my changes for an improved
peephone which already has a check for volatile.
Thanks,
Andrew Pinski
On Sat, Dec 6, 2014 at 5:54 PM, Andrew Pinski wrote:
> On Fri, Dec 5, 2014 at 9:08 AM, Marcus Shawcroft
> wrote:
>> On 18 November 2014 at 08:34, Bin Cheng wrote:
>>
>>> 2014-11-18 Bin Cheng
>>>
>>> * config/aarch64/aarch64.md
On Sat, Dec 6, 2014 at 6:35 PM, Andrew Pinski wrote:
> On Sat, Dec 6, 2014 at 5:54 PM, Andrew Pinski wrote:
>> On Fri, Dec 5, 2014 at 9:08 AM, Marcus Shawcroft
>> wrote:
>>> On 18 November 2014 at 08:34, Bin Cheng wrote:
>>>
>>>> 2014-11-18 B
On Sun, Dec 7, 2014 at 5:47 PM, Bin.Cheng wrote:
> On Sun, Dec 7, 2014 at 6:24 PM, Andrew Pinski wrote:
>> On Sat, Dec 6, 2014 at 6:35 PM, Andrew Pinski wrote:
>>> On Sat, Dec 6, 2014 at 5:54 PM, Andrew Pinski wrote:
>>>> On Fri, Dec 5, 2014 at 9:08 AM, Marcus S
On Sun, Dec 7, 2014 at 7:35 PM, Bin.Cheng wrote:
> On Mon, Dec 8, 2014 at 11:26 AM, Bin.Cheng wrote:
>> On Mon, Dec 8, 2014 at 11:16 AM, Andrew Pinski wrote:
>>> On Sun, Dec 7, 2014 at 5:47 PM, Bin.Cheng wrote:
>>>> On Sun, Dec 7, 2014 at 6:24 PM, Andrew Pins
any regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp): Reject
volatile mems.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
testsuite/ChangeLog:
* gcc.target/aarch64/volatileloadpair-1.c: New testcase.
* gcc.target/aarch64
64-bit system?
>
> https://lkml.org/lkml/2012/7/6/570
> https://lkml.org/lkml/2012/7/6/545
>
> If we have 64-bit kernel and 64-bit application is executed sys_getresuid is
> used for getresuid syscall, otherwise if 32-bit application is executed --
> sys_getresuid16 is used. Thus 64-bit application will never call
> sys_getresuid16 implemenation. Then
> getresuid16/getresgid16/getgroups16/setgroups16/etc only needs to in 32-bit
> binary of libsanitizer. Same should apply for x86_64/i*86.
>
> Is that correct?
Kinda. It only applies for aarch32 and not for AARCH64:ILP32.
AARCH64:ILP32 uses the standard system calls here too.
Thanks,
Andrew Pinski
>
> david
On Mon, Nov 24, 2014 at 1:32 PM, Jeff Law wrote:
> On 11/22/14 21:20, Andrew Pinski wrote:
>>
>> Hi,
>>The problem here is here is that OBJCOPY is not being set to the
>> newly built objcopy when compiling libgo. This patch adds
>> OBJCOPY_FOR_TARGET to t
On Wed, Dec 24, 2014 at 9:28 AM, Dimitris Papavasiliou
wrote:
> Hello,
>
> The attached patch fixes an issue reported a couple of years ago in Bug
> 51891 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51891). The problem is
> caused because classes without instance variables have no ivar list at
On Thu, Jan 8, 2015 at 9:35 PM, Jeff Law wrote:
> On 01/05/15 14:18, Mike Stump wrote:
>>
>> On Dec 24, 2014, at 9:28 AM, Dimitris Papavasiliou
>> wrote:
>>>
>>> The attached patch fixes an issue reported a couple of years ago in Bug
>>> 51891 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51891).
QI (const_int 1 [0x1])
> (reg:QI 0 x0 [ bit ]))
>
>
> Similarly for the case:
>
>
> (ashift:QI (subreg:QI (reg:SI 85) 0)
> (subreg:QI (and:SI (reg:SI 0 x0 [ bit ])
> (const_int 7 [0x7])) 0))
>
>
> Again, QImode ASHIFT, so the masking of the shift count is redundant
> resulting in:
>
> (ashift:QI (subreg:QI (reg:SI 85) 0)
> (reg:QI 0 x0 [ bit ]))
>
>
> I think you need to do some further analysis. Is it perhaps the case that
> SHIFT_COUNT_TRUNCATED is nonzero when in fact it should be zero?
Jeff is correct here. SHIFT_COUNT_TRUNCATED cannot be true if the
aarch64 back-end has shifts patterns for smaller than 32/64bit but the
aarch64 target only has shifts for 32 and 64bit.
The middle-end is doing the correct thing, with SHIFT_COUNT_TRUNCATED
true and a pattern for a QIshift, means the shifter does not to be
truncated before use.
Thanks,
Andrew Pinski
>
> Jeff
>
>
On Tue, Nov 11, 2014 at 6:47 AM, Marcus Shawcroft
wrote:
> On 30 October 2014 08:54, Gopalasubramanian, Ganesh
> wrote:
>
>> 2014-10-30 Ganesh Gopalasubramanian
>
> Check the whitespace in your ChangeLog line.
>
>> * config/arm/types.md (define_attr "type"): Add prefetch.
>
> The existi
On Mon, Jan 12, 2015 at 7:52 AM, Kyrill Tkachov wrote:
> Hi all,
>
> As raised in https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01237.html and
> discussed in that thread, using __builtin_sqrt for vsqrt_f64 may end up in a
> call to the library sqrt at -O0. To avoid that this patch uses a target
>
On Mon, Jan 12, 2015 at 12:19 PM, Jakub Jelinek wrote:
> Hi!
>
> The 991213-3.c testcase ICEs on aarch64-linux with -mabi=ilp32
> since wide-int merge. The problem is that
> x = convert_memory_address (Pmode, x)
> is used twice on a VOIDmode CONST_INT, which is wrong.
> For non-VOIDmode rtl the s
On Tue, Dec 9, 2014 at 6:18 PM, Andrew Pinski wrote:
> Hi,
> As mentioned in
> https://gcc.gnu.org/ml/gcc-patches/2014-12/msg00609.html, the
> load/store pair peepholes currently accept volatile mem which can
> cause wrong code as the architecture does not define which par
where store pair was not being created before but is
after.
OK? Build and tested for aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (fusion_load_store): Check dest mode
instead of src mode.
* gcc.target/aarch64/store-pair-1.c: New testcase.
Index
On Tue, Jan 13, 2015 at 6:13 AM, Marcus Shawcroft
wrote:
> On 11 January 2015 at 02:37, Andrew Pinski wrote:
>> On Tue, Nov 11, 2014 at 6:47 AM, Marcus Shawcroft
>> wrote:
>>> On 30 October 2014 08:54, Gopalasubramanian, Ganesh
>>> wrote:
>>>
nd you should run the full GCC
testsuite.
https://gcc.gnu.org/contribute.html is a good page to start with how
to handle most of the items above.
https://gcc.gnu.org/wiki/HowToPrepareATestcase is a good page on how
to write the testcase for testing the added optimization.
Thanks,
Andrew Pinski
&g
53 55 7 (set (reg:SI 108)
>> (const:SI (plus:SI (symbol_ref:SI ("_dl_rtld_map") [flags
>> 0x42] )
>> (const_int -1073742800 [0xbc30] x.i:22 -1
>> (nil))
>> x.i:30:1: internal compiler error: in extr
), where C is constant, can be simplified to
(GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
But this is wrong when C is 0. Anyways I committed this patch as
obvious to fix the issue in simplify-rtx.c but I have not looked into
why CSE does simplify the plus.
Thanks,
Andrew Pinski
function (abort1).
Committed as obvious after testing on mips64-linux-gnu that the
testcase passes now.
Thanks,
Andrew Pinski
* gcc.target/mips/octeon-bbit-3.c: Change the second call to abort to
call abort1 so that cross jumping does not happen.
Index: testsuite/gcc.target/mips/octeon-bbit-3.c
On Mon, 2012-11-05 at 19:19 +, Richard Sandiford wrote:
> Hi Andrew,
>
> Andrew Pinski writes:
> > On Fri, Oct 5, 2012 at 8:43 PM, Andrew Pinski
> > wrote:
> >> On Sun, Aug 19, 2012 at 10:13 AM, Richard Sandiford
> >> wrote:
> >>> Andrew
l { scan-tree-dump-times "L\\\$?C0" 2 "gimple" } } */
> +/* { dg-final { scan-tree-dump-times "L\\\$?C\\\.*0" 2 "gimple" } } */
I think .* will match too much as it will match newlines too. I think
[^\n\]* is better.
Thanks,
Andrew Pinski
> /* { dg-final { cleanup-tree-dump "gimple" } } */
On Tue, Nov 6, 2012 at 8:07 AM, Andrew Pinski wrote:
> On Tue, Nov 6, 2012 at 6:54 AM, David Edelsohn wrote:
>> The regex in const-uniq-1.c assumes ELF label format, which does not
>> match AIX XCOFF. The following patch broadens the regex so that it
>> also cor
Hi,
The problem here is with section anchors turned on, we generate a
BSS rather than a local common symbol and we no longer match the
pattern: "_ZGVZ3foovE1x,8,8". This fixes this testcase by just adding
-fno-section-anchors.
Thanks,
Andrew Pinski
2012-11-06 Andrew Pinski
Hi,
The problem here is the vector cost model causes some of the
functions not be vectorized even though we are scanning for the
explicit vectorization. This fixes the testcase by turning off the
cost model.
Thanks,
Andrew Pinski
2012-11-06 Andrew Pinski
* gcc.target/aarch64/vect
On Mon, 2012-11-05 at 11:20 -0800, Andrew Pinski wrote:
> On Mon, 2012-11-05 at 19:19 +, Richard Sandiford wrote:
> > Hi Andrew,
> >
> > Andrew Pinski writes:
> > > On Fri, Oct 5, 2012 at 8:43 PM, Andrew Pinski
> > > wrote:
> > >>
quick test to make sure it
works. Note someone might need to mark the testcase as only
executable on targets which have 32bit ints.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.c-torture/execute/20121108-1.c: New testcase.
Index: gcc.c-torture/execute/20121108-1.c
testing from the
combined tree either.
OK? Bootstrapped and tested with and without being in a combined tree
without any regressions.
Thanks,
Andrew Pinski
* configure.ac: Set PLUGIN_LD_SUFFIX to just "ld" if it was "ld-new".
* configure: Regenerate.
diff --git a/gcc/confi
On Sat, Nov 10, 2012 at 6:46 AM, Paolo Bonzini wrote:
> Il 10/11/2012 05:30, Andrew Pinski ha scritto:
>> Hi,
>> The problem here is that set PLUGIN_LD_SUFFIX to ld-new which is not
>> the final installed binary name. This patch fixes the problem by
>> changing
; single test or two is IMHO really too much, and similarly adding gtest
> as another requirement to build gcc. Does gtest support all the targets
> that gcc does btw?
Also does gtest support cross testing; that is testing over rsh/ssh
and testing via a simulator? We should require that as a re
work on little-endian and also update the code to
use the aliasing oracle and some of the new VEC interface.
Yes I know I forgot to add documentation for the new option and for
the new pass. I will add it soon.
Thanks,
Andrew Pinski
ChangeLog:
* tree-merge-const-bfstores.c: New file.
* tree-pass.h
On Mon, Nov 12, 2012 at 4:50 PM, Andrew Pinski
wrote:
> Hi,
> I know we are in stage3, I thought I would send this out now for
> review as I finally have it ready for consumption as I finally got
> around to removing the limitation of it only working on big-endian.
> This pass
s like this in two different
places. Why can't the people who added the target library like this
take responsibility for doing the merges from the GCC source to the
upstream? Like libffi is handled.
Thanks,
Andrew Pinski
>
>
> Thanks. Diego.
On Tue, Nov 13, 2012 at 1:40 PM, Konstantin Serebryany
wrote:
> On Tue, Nov 13, 2012 at 3:42 AM, Jakub Jelinek wrote:
>> On Tue, Nov 13, 2012 at 03:31:21AM -0800, H.J. Lu wrote:
>>> On Tue, Nov 13, 2012 at 3:20 AM, Dodji Seketeli wrote:
>>> > Diego Novillo a écrit:
>>> >
>>> >> Patches to libsa
libbfd-based tool.
> Or is python not allowed in gcc testing infrastructure?
> Then you can probably write a simple script in perl that does the same.
Why not just use TCL for this. Since there is already a scripting
language with dejagnu via TCL.
Thanks,
Andrew Pinski
>
>&
time on linux anyway.
Because x86_64 is defined even for x32. And it is the only one
currently supported does not mean there will be more in the future.
Thanks,
Andrew Pinski
>
>
> On Tue, Nov 13, 2012 at 1:53 PM, H.J. Lu wrote:
>> On Tue, Nov 13, 2012 at 1:40 PM, Konstantin Serebr
On Tue, Nov 13, 2012 at 2:31 PM, Ramana Radhakrishnan
wrote:
>
>
> On 13 Nov 2012, at 21:18, Konstantin Serebryany
> wrote:
>
>> On Tue, Nov 13, 2012 at 8:21 AM, Diego Novillo wrote:
>>> On Tue, Nov 13, 2012 at 12:07 AM, David Miller wrote:
This has broken the build on every Linux ta
in the temp that we are creating for the conditional
> move.
>
> Tested on mips-mti-elf with no regressions.
>
> OK for checkin?
Do you have a testcase? As I added expand_cond_expr_using_cmove, I
think this is the correct fix.
Thanks,
Andrew Pinski
>
> Steve Ellcey
> sell
On Wed, Nov 14, 2012 at 11:27 AM, Steve Ellcey wrote:
> On Wed, 2012-11-14 at 11:15 -0800, Andrew Pinski wrote:
>
>> Do you have a testcase? As I added expand_cond_expr_using_cmove, I
>> think this is the correct fix.
>>
>> Thanks,
>> Andrew Pinski
>
&g
On Wed, Nov 14, 2012 at 1:45 PM, Steve Ellcey wrote:
> On Wed, 2012-11-14 at 12:00 -0800, Andrew Pinski wrote:
>
>> I know exactly where this code comes from; I have looked at the
>> benchmark as one of the reason why I add expand_cond_expr_using_cmove
>> in the first pl
On Wed, Nov 14, 2012 at 1:51 PM, Andrew Pinski
wrote:
> On Wed, Nov 14, 2012 at 1:45 PM, Steve Ellcey wrote:
>> On Wed, 2012-11-14 at 12:00 -0800, Andrew Pinski wrote:
>>
>>> I know exactly where this code comes from; I have looked at the
>>> benchma
k StackTrace::FastUnwindStack should never be enabled in
general for GCC since it depends on the frame pointer being enabled
which is not always true on either i686 or x86_64 and it is not very
portable at all.
Thanks,
Andrew Pinski
>
> diff --git a/libsanitizer/include/sanitizer/common_in
On Thu, Nov 15, 2012 at 12:58 PM, Richard Sandiford
wrote:
> Andrew Pinski writes:
>> 2012-07-26 Andrew Pinski
>>
>> Bug #3261
>> * config/mips/mips.md (*mov_on_):
>> Remove mode check from comparisons.
>> (*mov_on_): Likewi
On Thu, Nov 15, 2012 at 1:24 PM, Andrew Pinski
wrote:
> On Thu, Nov 15, 2012 at 12:58 PM, Richard Sandiford
> wrote:
>> Andrew Pinski writes:
>>> 2012-07-26 Andrew Pinski
>>>
>>> Bug #3261
>>> * config/mips/mips.md (*mov_on
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