Hello Kewen:
On 04/12/23 7:31 am, Kewen.Lin wrote:
> Hi Ajit,
>
> on 2023/12/1 17:10, Ajit Agarwal wrote:
>> Hello Kewen:
>>
>> On 24/11/23 3:01 pm, Kewen.Lin wrote:
>>> Hi Ajit,
>>>
>>> Don't forget to CC David (CC-ed) :), some c
Hello Kewen:
On 05/12/23 7:13 pm, Ajit Agarwal wrote:
> Hello Kewen:
>
> On 04/12/23 7:31 am, Kewen.Lin wrote:
>> Hi Ajit,
>>
>> on 2023/12/1 17:10, Ajit Agarwal wrote:
>>> Hello Kewen:
>>>
>>> On 24/11/23 3:01 pm, Kewen.Lin wrote:
&
Hello Kewen:
On 06/12/23 7:52 am, Kewen.Lin wrote:
> on 2023/12/6 02:01, Ajit Agarwal wrote:
>> Hello Kewen:
>>
>>
>> On 05/12/23 7:13 pm, Ajit Agarwal wrote:
>>> Hello Kewen:
>>>
>>> On 04/12/23 7:31 am, Kewen.Lin wrote:
>>>> Hi A
Hello Kewen:
On 07/12/23 4:31 pm, Ajit Agarwal wrote:
> Hello Kewen:
>
> On 06/12/23 7:52 am, Kewen.Lin wrote:
>> on 2023/12/6 02:01, Ajit Agarwal wrote:
>>> Hello Kewen:
>>>
>>>
>>> On 05/12/23 7:13 pm, Ajit Agarwal wrote:
>>>&
Hello Kewen:
On 12/12/23 11:58 am, Kewen.Lin wrote:
> Hi Ajit,
>
> on 2023/12/8 16:01, Ajit Agarwal wrote:
>> Hello Kewen:
>>
>
> [snip...]
>
>> With UNSPEC_MMA_EXTRACT I could generate the register pair but functionally
>> here is the
>> below
tree-ssa-loop-ivopts : Add live analysis in regs used in decision making.
Add live anaysis in regs used calculation in decision making of
selecting ivopts candidates.
2023-11-08 Ajit Kumar Agarwal
gcc/ChangeLog:
* tree-ssa-loop-ivopts.cc (get_regs_used): New function.
(determ
Hello Richard:
On 09/11/23 6:21 pm, Richard Biener wrote:
> On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote:
>>
>> tree-ssa-loop-ivopts : Add live analysis in regs used in decision making.
>>
>> Add live anaysis in regs used calculation in decision making of
>
Ping ^2.
On 23/10/23 2:02 pm, Ajit Agarwal wrote:
>
>
> Ping ^1.
>
> Forwarded Message
> Subject: [PING ^0][PATCH v2] rs6000: Add new pass for replacement of
> contiguous addresses vector load lxv with lxvp
> Date: Sun, 15 Oct 2023 17:43:24 +0530
&g
ping!
Forwarded Message
Subject: [PING ^0] [PATCH v2 3/4] Improve functionality of ree pass with
various constants with AND operation.
Date: Sun, 15 Oct 2023 18:28:51 +0530
From: Ajit Agarwal
To: gcc-patches
CC: Jeff Law , Vineet Gupta ,
Richard Biener , Segher Boessenkool
Ping!
Ok for trunk.
Thanks & Regards
Ajit
Forwarded Message
Subject: [PATCH V15 4/4] ree: Improve ree pass using defined abi interfaces
Date: Sun, 29 Oct 2023 16:14:17 +0530
From: Ajit Agarwal
To: gcc-patches , Jeff Law ,
Vineet Gupta , Bernhard Reutner-Fischer
CC: Ric
Hello Richard:
On 10/11/23 7:29 pm, Richard Biener wrote:
> On Fri, Nov 10, 2023 at 7:42 AM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>>
>> On 09/11/23 6:21 pm, Richard Biener wrote:
>>> On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote:
>>>
send the patch accordingly.
Thanks & Regards
Ajit
On 03/11/23 8:24 pm, Ajit Agarwal wrote:
> Hello Richard:
>
>
> On 03/11/23 7:06 pm, Richard Biener wrote:
>> On Fri, Nov 3, 2023 at 11:20 AM Ajit Agarwal wrote:
>>>
>>> Hello Richard:
>>>
>&
Hello Richard:
This patch does decision making in code sinking considers the following
decision.
High register pressure region is true if the following criteria
satisfied.
a) If liveout (early_bb) <= livein (early_bb).
b) if liveout (best_bb) <= liveout (early_bb).
c) !best_bb->count >= early_bb
Hello Richard:
Currently, code sinking will sink code at the use points with loop having same
nesting depth. The following patch improves code sinking by placing the sunk
code in immediate dominator with same loop nest depth.
Review comments are incorporated.
For example :
void bar();
int j;
vo
Hello Richard:
On 16/11/23 3:28 pm, Richard Biener wrote:
> On Mon, Oct 30, 2023 at 1:10 PM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>> Currently, code sinking will sink code at the use points with loop having
>> same
>> nesting depth. The following pat
Hello Richard:
This patch does decision making in code sinking considers the following
decision.
High register pressure region is true if the following criteria
satisfied.
a) If liveout (early_bb) <= livein (early_bb).
b) if liveout (best_bb) <= liveout (early_bb).
c) !best_bb->count >= early_bb
Hello All:
Loop invariant code motion can increase register pressure if the
live ranges increases and there could be spill happening.
In tree-ssa representaion, we have the proof tha livein at
the loop header will be live-in across all the basic blocks
inside the loop.
We want to evaluate that h
Hello All:
This patch marked LOOP_DATA->live as the livein at the loop header basic
block. This is because Livein at each basic block is live in at the loop header.
Bootstrapped and regtested on powerpc64-linux-gnu.
SPEC CPU 2017 benchmarks score is better than trunk wit this
change for INT and
On 21/11/23 3:02 pm, Richard Biener wrote:
> On Tue, Nov 21, 2023 at 9:30 AM Ajit Agarwal wrote:
>>
>> Hello All:
>>
>> This patch marked LOOP_DATA->live as the livein at the loop header basic
>> block. This is because Livein at each basic block is live
On 21/11/23 3:15 pm, Ajit Agarwal wrote:
>
>
> On 21/11/23 3:02 pm, Richard Biener wrote:
>> On Tue, Nov 21, 2023 at 9:30 AM Ajit Agarwal wrote:
>>>
>>> Hello All:
>>>
>>> This patch marked LOOP_DATA->live as the livein at the loop header
Ping ^2!
Ok for trunk?
Thanks & Regards
Ajit
Forwarded Message
Subject: [PING][PATCH V15 4/4] ree: Improve ree pass using defined abi
interfaces
Date: Fri, 10 Nov 2023 12:37:25 +0530
From: Ajit Agarwal
To: Vineet Gupta , Jeff Law ,
Bernhard Reutner-Fischer
CC: Ric
Ping^2!
Forwarded Message
Subject: [PING ^1] [PATCH v2 3/4] Improve functionality of ree pass with
various constants with AND operation.
Date: Fri, 10 Nov 2023 12:39:02 +0530
From: Ajit Agarwal
To: gcc-patches
CC: Jeff Law , Vineet Gupta ,
Richard Biener , Segher
Ping ^3!
Thanks & Regards
Ajit
Forwarded Message
Subject: [PING ^3][PATCH v2] rs6000: Add new pass for replacement of contiguous
addresses vector load lxv with lxvp
Date: Mon, 27 Nov 2023 10:15:26 +0530
From: Ajit Agarwal
To: Kewen.Lin , Segher Boessenkool
, Peter Ber
Hello All:
I am working on fixing the below issues and incorporating comments from Kewen
and
Michael.
Thanks & Regards
Ajit
On 28/11/23 9:11 pm, Michael Meissner wrote:
> On Tue, Nov 28, 2023 at 05:44:43PM +0800, Kewen.Lin wrote:
>> on 2023/11/28 15:05, Michael Meissner wrote:
>>> I tried using
This new version of patch 7 use improve ree pass for rs6000 target using
defined ABI interfaces.
Bootstrapped and regtested on power64-linux-gnu.
Review comments incorporated.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target using defined abi interfaces
For rs6000 target we see re
8e21...@linux.ibm.com/
> [2]
> https://patchwork.sourceware.org/project/gcc/patch/65ed79a3-9964-dd50-39cb-98d5dbc72...@linux.ibm.com/
>
> --
> Maxim Kuvyrkov
> https://www.linaro.org
>
>> On Sep 18, 2023, at 09:59, Ajit Agarwal via Gcc-patches
>> wrote:
>>
Hello Vineet:
Version 7 of the patch incorporates the below review comments.
Please review.
Thanks & Regards
Ajit
On 19/09/23 1:57 am, Vineet Gupta wrote:
> Hi Ajit,
>
> On 9/17/23 22:59, Ajit Agarwal wrote:
>> This new version of patch 6 use improve ree pass for
On 19/09/23 2:36 pm, Xi Ruoyao wrote:
> On Tue, 2023-09-19 at 14:29 +0530, Ajit Agarwal wrote:
>> This new version of patch 7 use improve ree pass for rs6000 target
>> using defined ABI interfaces.
>> Bootstrapped and regtested on power64-linux-gnu.
>
> You should d
Hello Jeff:
This patch eliminates redundant zero and sign extension with ree pass for rs6000
target.
Bootstrapped and regtested for powerpc64-linux-gnu.
Thanks & Regards
Ajit
ree: Improve ree pass
For rs6000 target we see redundant zero and sign extension and ree pass
s improved to eliminat
Hello All:
This version 8 of the patch uses abi interfaces to remove zero and sign
extension elimination.
Bootstrapped and regtested on powerpc-linux-gnu.
Incorporated all the review comments of version 6. Added sign extension
elimination using abi
interfaces.
Thanks & Regards
Ajit
ree: Impr
Hello Vineet:
This patch is without sign_extension implementation.
I have sent patch 8 that incorporates sign_extension using abi interfaces.
Please review.
Thanks & Regards
Ajit
On 19/09/23 2:48 pm, Ajit Agarwal wrote:
>
>
> On 19/09/23 2:36 pm, Xi Ruoyao wrote:
>> On Tu
Hello All:
This patch determines Unroll factor based on loop register pressure.
Unroll factor is quotient of max of available registers in loop
by number of liveness.
If available registers increases unroll factor increases.
Wherein unroll factor decreases if number of liveness increases.
Loop
Hello All:
This patch determines unroll factor based on loop register pressure.
Unroll factor is quotient of max of available registers in loop
by number of liveness.
If available registers increases unroll factor increases.
Wherein unroll factor decreases if number of liveness increases.
Loop
Hello All:
This version of patch relaxes store fusion for more use cases.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
Hello Richard:
Based on your feedback I have changed the logic of determining
unroll factor for loops.
Unroll factor is calculated based on available registers and regs
needed inside the loops.
Unroll factor is quotient of max of available registers in loop
over regs needed inside the loops.
Co
Hello Richard:
On 03/07/24 2:18 pm, Richard Biener wrote:
> On Sun, Jun 30, 2024 at 4:15 AM Ajit Agarwal wrote:
>>
>> Hello All:
>>
>> This patch determines Unroll factor based on loop register pressure.
>>
>> Unroll factor is quotient of max of avai
Ping ! Please let me know OK for trunk.
Thanks & Regards
Ajit
Forwarded Message
Subject: [Patch, rs6000, middle-end] v6: Add implementation for different
targets for pair mem fusion
Date: Tue, 2 Jul 2024 14:15:02 +0530
From: Ajit Agarwal
To: Alex Coplan , Richard Sandi
Hello All:
Unroll factor is determined with max distance across loop iterations.
The logic for determining the loop unroll factor is based on
data dependency across loop iterations.
The max distance across loop iterations is the unrolling factor
that helps in predictive commoning.
Bootstrapped a
Hello Richard:
On 11/07/24 2:21 pm, Richard Biener wrote:
> On Thu, Jul 11, 2024 at 10:30 AM Ajit Agarwal wrote:
>>
>> Hello All:
>>
>> Unroll factor is determined with max distance across loop iterations.
>> The logic for determining the loop unroll factor is b
Hello Richard:
On 12/07/24 6:20 pm, Richard Biener wrote:
> On Fri, Jul 12, 2024 at 12:09 PM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>> On 11/07/24 2:21 pm, Richard Biener wrote:
>>> On Thu, Jul 11, 2024 at 10:30 AM Ajit Agarwal
>>> wrote:
&g
Hello Richard:
On 12/07/24 6:20 pm, Richard Biener wrote:
> On Fri, Jul 12, 2024 at 12:09 PM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>> On 11/07/24 2:21 pm, Richard Biener wrote:
>>> On Thu, Jul 11, 2024 at 10:30 AM Ajit Agarwal
>>> wrote:
&g
Hello Richard:
On 13/07/24 8:16 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 12/07/24 6:20 pm, Richard Biener wrote:
>> On Fri, Jul 12, 2024 at 12:09 PM Ajit Agarwal wrote:
>>>
>>> Hello Richard:
>>>
>>> On 11/07/24 2:21 pm, Richard Biene
Ping^1. Ok to install?
Thanks & Regards
Ajit
Forwarded Message
Subject: [PING^0][Patch, rs6000, middle-end] v6: Add implementation for
different targets for pair mem fusion
Date: Mon, 8 Jul 2024 07:55:19 +0530
From: Ajit Agarwal
To: Alex Coplan , Richard Sandi
Hello Richard:
On 18/07/24 1:17 am, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello All:
>>
>> This version of patch relaxes store fusion for more use cases.
>>
>> Common infrastructure using generic code for pair mem fusion of different
>> tar
Hello Richard:
On 18/07/24 2:04 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 18/07/24 1:17 am, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>> Hello All:
>>>
>>> This version of patch relaxes store fusion for more use cases.
>>>
>&g
Hello Richard:
All comments are addressed.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
Bootstrapped and regtested on p
Hello Richard:
On 18/07/24 4:44 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> [...]
>>>> +// Set subreg for OO mode pair to generate sequential registers given
>>>> +// insn_info pairs I1, I2 and LOAD_P is true iff load insn and false
&
Hello Alex/Richard:
All comments are addressed.
There were some issues in sending the patch sending it again.
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independent code is the Generic code with pure virtual funct
Hello Alex/Richard:
All comments are addressed.
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independent code is the Generic code with pure virtual function
to interface betwwen target independent and dependent code.
Hello Alex/Richard:
All review comments are incorporated.
Changes since v4:
- changed prototype of destructure_pair from rti parameter to pattern
parameter.
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independe
sion.
>
There were issues sending the patch through thunderbird, hence multople
pacthes. Sorry for inconvenience caused.
> Mostly the comments below are just style nits and things you missed from
> the last review(s) (please try not to miss so many in the future).
>
Addressed.
>
Hello Alex/Richard:
All review comments are addressed.
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independent code is the Generic code with pure virtual function
to interface between target independent and dependen
iew.
>
Sorry for the inconvenience caused. Hopefully I have incorporated
all the comments in v6 version of the patch.
> On 14/05/2024 15:08, Ajit Agarwal wrote:
>> Hello Alex/Richard:
>>
>> All comments are addressed.
>>
>> Common infrastructure of load store pai
ake the final judgement on that. I don't really
> mind either way.
Sure.
Thanks & Regards
Ajit
>
> On 15/05/2024 15:06, Ajit Agarwal wrote:
>> Hello Alex/Richard:
>>
>> All review comments are addressed.
>>
>> Common infrastructure of load store
Hello Alex:
On 17/05/24 6:22 pm, Alex Coplan wrote:
> Hi Ajit,
>
> On 17/05/2024 18:05, Ajit Agarwal wrote:
>> Hello Alex:
>>
>> On 16/05/24 10:21 pm, Alex Coplan wrote:
>>> Hi Ajit,
>>>
>>> Thanks a lot for working through the review feedb
Hello Alex/Richard:
All comments are addressed.
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independent code is the Generic code with pure virtual function
to interface between target independent and dependent code.
Hello Richard:
On 17/05/24 11:07 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Alex/Richard:
>>
>> All review comments are addressed.
>>
>> Common infrastructure of load store pair fusion is divided into target
>> independent and targ
to something else,
>probably there are other bits too).
> - Move the generic parts out of gcc/config/aarch64 to a .cc file in the
>middle-end.
>
> I'll let Richard S make the final judgement on that. I don't really
> mind either way.
>
> On 15/05/2024 15
Hello Alex/Richard:
Renaming of generic code is done to make target independent
and target dependent code to support multiple targets.
Target independent code is the Generic code with pure virtual function
to interface betwwen target independent and dependent code.
Target dependent code is the i
Hello Alex:
On 21/05/24 1:16 am, Alex Coplan wrote:
> On 20/05/2024 18:44, Alex Coplan wrote:
>> Hi Ajit,
>>
>> On 20/05/2024 21:50, Ajit Agarwal wrote:
>>> Hello Alex/Richard:
>>>
>>> Move pair fusion pass from aarch64-ldp-fusion.cc to middle-end
Hello Alex:
On 21/05/24 6:02 pm, Alex Coplan wrote:
> On 21/05/2024 16:02, Ajit Agarwal wrote:
>> Hello Alex:
>>
>> On 21/05/24 1:16 am, Alex Coplan wrote:
>>> On 20/05/2024 18:44, Alex Coplan wrote:
>>>> Hi Ajit,
>>>>
>>>>
Hello Alex:
On 21/05/24 6:50 pm, Alex Coplan wrote:
> On 20/05/2024 21:50, Ajit Agarwal wrote:
>> Hello Alex/Richard:
>>
>> Move pair fusion pass from aarch64-ldp-fusion.cc to middle-end
>> to support multiple targets.
>>
>> Common infrastructure of
Hello Alex:
On 21/05/24 10:22 pm, Alex Coplan wrote:
> Hi Ajit,
>
> I've left some more comments below. It's getting there now, thanks for
> your patience.
>
> On 21/05/2024 20:32, Ajit Agarwal wrote:
>> Hello Alex/Richard:
>>
>> All comments a
e changes, but you'll need Richard S to approve.
>
> Thanks a lot for doing this.
>
> On 22/05/2024 00:16, Ajit Agarwal wrote:
>> Hello Alex/Richard:
>>
>> All comments are addressed.
>>
>> Move pair fusion pass from aarch64-ldp-fusion.cc to middle-end
Hello Richard:
On 30/05/24 4:44 pm, Richard Sandiford wrote:
> Thanks for the update. Some comments below, but looks very close
> to ready.
>
Thanks a lot.
> Ajit Agarwal writes:
>> diff --git a/gcc/pair-fusion.cc b/gcc/pair-fusion.cc
>> new file mode 100644
>>
Hello All:
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific specific code implements virtual functions defined
by generic code.
Code is implemented with pure virtual functions to interface with target
code.
Target specific code are added
Hello Richard:
On 31/05/24 3:23 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello All:
>>
>> Common infrastructure using generic code for pair mem fusion of different
>> targets.
>>
>> rs6000 target specific specific code implements virtu
Hello Richard:
On 31/05/24 8:08 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 31/05/24 3:23 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> Hello All:
>>>>
>>>> Common infrastructure using generic code for pair mem fus
Hello Richard:
On 31/05/24 10:29 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 31/05/24 8:08 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>> On 31/05/24 3:23 pm, Richard Sandiford wrote:
>>>> Ajit Agarwal writes:
>>>>> Hello All:
&
Hello All:
All comments are addressed and patch is split into rs6000 and aarch64 target
changes.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implements virtual functions defined by generic
code.
Target specific code are added
Hello All:
Common infrastructure using generic code for pair mem fusion of different
targets.
Implements additional interface virtual function implementation
required for rs6000 target.
Tested for aarch64-linux-gnu.
Thanks & Regards
Ajit
aarch64: Additional interface function implementation.
Hello Richard:
On 31/05/24 3:23 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello All:
>>
>> Common infrastructure using generic code for pair mem fusion of different
>> targets.
>>
>> rs6000 target specific specific code implements virtu
Hello All:
Common infrastructure using generic code for pair mem fusion of different
targets.
Implements additional interface virtual function implementation
required for rs6000 target.
Tested for aarch64-linux-gnu.
Thanks & Regards
Ajit
aarch64: Additional interface function implementation
C
Hello Richard:
On 03/06/24 2:07 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>> On 31/05/24 8:08 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 31/05/24 3:23 pm, Richard Sandiford wrote:
>>>>> Ajit Agar
Hello Richard:
On 03/06/24 5:03 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>>> [...]
>>> If it is intentional, what distinguishes things like vperm and xxinsertw
>>> (and all other unspecs) from plain addition?
>>>
>>> [(set (m
Hello Richard:
On 03/06/24 7:47 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 03/06/24 5:03 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>>> [...]
>>>>> If it is intentional, what distinguishes things like vperm and xx
Hello Richard:
On 03/06/24 8:24 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>>
>> On 03/06/24 7:47 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 03/06/24 5:03 pm, Richard Sandiford wrote:
>>>>
Hello Richard:
On 03/06/24 9:28 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 03/06/24 8:24 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>> Hello Richard:
>>>
>>> On 03/06/24 7:47 pm, Richard Sandiford wrote:
>>>> Ajit Agarwal
Hello Richard:
This patch addresses all the review comments.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
Bootstrapped
Hello Richard:
On 12/08/24 5:30 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> [...]
>> +static void
>> +update_change (set_info *set)
>> +{
>> + if (!set->has_any_uses ())
>> +return;
>> +
>> + auto *use = *set->all_uses
Hello Richard:
On 15/08/24 3:45 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> +static void
>> +update_change (set_info *set)
>> +{
>> + if (!set->has_any_uses ())
>> +return;
>> +
>> + auto *use = *set->all_uses ().begin ()
Hello All:
All comments are addressed.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
Tested for powerpc64-linux-gnu.
Th
Hello Richard:
On 06/06/24 2:28 pm, Richard Sandiford wrote:
> Hi,
>
> Just some comments on the fuseable_load_p part, since that's what
> we were discussing last time.
>
> It looks like this now relies on:
>
> Ajit Agarwal writes:
>> + /* We use DF d
Hello Richard:
On 06/06/24 8:03 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 06/06/24 2:28 pm, Richard Sandiford wrote:
>>> Hi,
>>>
>>> Just some comments on the fuseable_load_p part, since that's what
>>> we were discussing l
Hello Richard:
On 07/06/24 4:24 am, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 06/06/24 8:03 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 06/06/24 2:28 pm, Richard Sandiford wrote:
>>>>> Hi,
>>>>>
>&g
Hello Richard:
On 07/06/24 1:52 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>>>>>>>> +
>>>>>>>> + df_ref use;
>>>>>>>> + df_insn_info *insn_info = DF_INSN_INFO_GET (info->rtl ());
>>>>>
Hello Richard:
On 10/06/24 2:12 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>>>>>>>>>> +
>>>>>>>>>> + rtx set = single_set (insn);
>>>>>>>>>> + if (set == NULL
Hello Richard:
On 10/06/24 2:52 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 10/06/24 2:12 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>>>>>>>>>> +
>>>>>>>>>>>> +rtx set =
Hello Richard:
On 10/06/24 3:20 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>>
>> On 10/06/24 2:52 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 10/06/24 2:12 pm, Richard S
Hello Richard:
On 10/06/24 3:20 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>>
>> On 10/06/24 2:52 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 10/06/24 2:12 pm, Richard S
Hello Richard:
On 10/06/24 3:58 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 10/06/24 3:20 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
>>>> On 10/06/24 2:52 pm, Richard Sandiford wrote:
>>>>> Ajit Agarwal writes:
>&g
Hello Richard:
On 11/06/24 4:36 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>>>>>> After LRA reload:
>>>>>>
>>>>>> (insn 9299 2472 2412 187 (set (reg:V2DF 51 19 [orig:240 vect__302.545 ]
>>>>>> [240])
Hello Richard:
On 11/06/24 5:15 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>> On 11/06/24 4:56 pm, Ajit Agarwal wrote:
>>> Hello Richard:
>>>
>>> On 11/06/24 4:36 pm, Richard Sandiford wrote:
>>>
Hello Richard:
On 11/06/24 4:56 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 11/06/24 4:36 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>>>>>> After LRA reload:
>>>>>>>
>>>>>>> (insn 9
Hello Richard:
On 11/06/24 4:56 pm, Ajit Agarwal wrote:
> Hello Richard:
>
> On 11/06/24 4:36 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>>>>>> After LRA reload:
>>>>>>>
>>>>>>> (insn 9
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