which decided by
> TARGET_POWERPC64. This mode iterator is used in "mr." and its split
> pattern. The original P iterator is wrong when -m32/-mpowerpc64 is set.
> In this situation, the "mr." should compares the whole 64-bit register
> with 0 other than the low 3
> mr 4,3
> cmp 0,3,0
>
> The patch also creates a new mode iterator which decided by
> TARGET_POWERPC64. This mode iterator is used in "mr." and its split
> pattern. The original P iterator is wrong when -m32/-mpowerpc64 is set.
> In this situation, the "
I notice there's some refactor in vectorizable_conversion
for code_helper,so I've adjusted my patch to that.
Here's the patch I'm going to commit.
We have already use intermidate type in case WIDEN, but not for NONE,
this patch extended that.
gcc/ChangeLog:
{-m32,}.
Ready to push to master.
gcc/ChangeLog:
PR target/110309
* config/i386/sse.md (maskload):
Refine pattern with UNSPEC_MASKLOAD.
(maskload): Ditto.
(*_load_mask): Extend mode iterator to
VI12HFBF_AVX512VL.
(*_load): Ditto.
gcc/testsuite
rt, and that leads to the
ICE described in the bug.
This patch sets the address space of the array type to that of the
element type.
Regression tests for avr look ok. Ok for trunk?
Regards
Senthil
PR 86869
gcc/c/ChangeLog:
* c-typeck.cc (c_build_qualified_typ
below vmv.
vsetvli zero,a2,e32,m1,ta,ma
vmv.v.i v1,0
vs1r.v v1,0(a0)
It will elimate the mul with const 0 instruction to the simple mov
instruction.
Signed-off-by: Yanzhang Wang
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add a split pattern.
gcc/testsuite/ChangeLog
On Wed, 2023-06-21 at 18:37 +, Joseph Myers wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Wed, 21 Jun 2023, Richard Biener via Gcc-patches wrote:
>
> > > This patch sets the address space of the a
/i386/pr78904-1b.c scan-assembler-not movb
FAIL: gcc.target/i386/pr78904-1b.c scan-assembler [ \t]andb
FAIL: gcc.target/i386/pr78904-1b.c scan-assembler [ \t]orb
FAIL: gcc.target/i386/pr78904-1b.c scan-assembler [ \t]xorb
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochen
-Os execution test
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2050/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl
--enable
such conversions produce wobbly
> values).
That would mean guarding this with !flag_trapping_math would be the appropriate
thing to do.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} and aarch64-linux-gnu.
Ok for trunk?
gcc/ChangeLog:
PR tree-optimization/110371
The new assembly looks better than original one, so I adjust those testcases.
Ok for trunk?
gcc/testsuite/ChangeLog:
PR tree-optimization/110371
PR tree-optimization/110018
* gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Scan scvt +
sxtw instead of scvt + zip1
When there're multiple operands in vec_oprnds0, vec_dest will be
overwrited to vectype_out, but in multi_step_cvt case, cvt_type is
expected. It caused an ICE when verify_gimple_in_cfg.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} and aarch64-linux-gnu.
Ok for trunk?
gcc/Chan
Hi,
I'd like to gentle ping this patch series:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621460.html
BR,
Kewen
on 2023/6/13 10:03, Kewen Lin via Gcc-patches wrote:
> This patch series follows Richi's suggestion at the link [1],
> which suggest structuring vectoriza
egressions.
This patch is ok for trunk, thanks!
BR,
Kewen
>
> Thanks
> Gui Haochen
>
> ChangeLog
> 2023-06-25 Haochen Gui
>
> gcc/
> PR target/104124
> * config/rs6000/altivec.md (*altivec_vupkhs_direct): Rename
> to...
>
__bfloat16 is redefined from typedef short to real __bf16 since GCC
V13. The patch issues an warning for potential silent implicit
conversion between __bf16 and short where users may only expect a
data movement.
To avoid too many false positive, warning is only under
TARGET_AVX512BF16
than whole vector size
bytes of accessible memory and k is a mask that would prevent reading
the inaccessible bytes from mem_addr, add UNSPEC_MASKMOV to prevent
it to be transformed to any other whole memory access instructions.
Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
Ready to push to t
dent of
optimization level, but still keeps the behavior of architecture
tuning(emit_vzeroupper) unchanged.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386-features.cc (pass_insert_vzeroupper:gate):
Move flag_expensi
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/82735
* config/i386/i386.cc (ix86_avx_u127_mode_needed): Don't emit
vzeroupper for vzeroupper call_insn.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx-vzeroupp
-lto-objects scan-tree-dump-times vect
"vectorizing stmts using SLP" 4
FAIL: gcc.dg/vect/slp-46.c scan-tree-dump-times vect "vectorizing stmts using
SLP" 4
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2117/u
lp of available
> target hooks (TARGET_CONDITIONAL_REGISTER_USAGE).
Nice, thanks for improving this.
>
> 2023-06-23 Jeevitha Palanisamy
>
> gcc/
> PR target/PR110320
> * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change
> GPR2 to volatile and non-fixed registe
Hi Pat,
> On 6/27/23 1:52 PM, Pat Haugen via Gcc-patches wrote:
>> Updated from prior version to address review comments (update
>> rs6000_rtx_cost,
>> update scan strings of mod-1.c/mod-2.c)l.
>>
>> Disable generation of scalar modulo instructions.
>>
Hi Carl,
on 2023/6/22 06:42, Carl Love wrote:
> On Mon, 2023-06-19 at 15:17 +0800, Kewen.Lin wrote:
>> Hi Carl,
>>
>> on 2023/5/31 04:46, Carl Love wrote:
>>> GCC maintainers:
>>>
>>> The following patch takes the tests in vsx-vector-6-p7.h, vs
/pieces-memcmp-2.c scan-assembler-not vptest[ \\t]*%ymm
FAIL: gcc.target/i386/pieces-memcmp-2.c scan-assembler-times vptest[ \\t]*%xmm 2
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2159/usr
--enable-clocale=gnu --with-system-zlib
Hi Carl,
on 2023/6/19 23:57, Carl Love wrote:
> GCC maintainers:
>
>
> The GLibC team requested a builtin to replace the mffscrn and mffscrni inline
> asm instructions in the GLibC code> Previously there was discussion on adding
> builtins for the mffscrn ins
Hi Jeevitha,
on 2023/6/7 13:44, P Jeevitha via Gcc-patches wrote:
> PR106907 has few warnings spotted from cppcheck. In that addressing
> redundant initialization issue. Here the initialized value of 'new_addr'
> was overwritten before it was read. Updated the source by removin
Hi Carl,
on 2023/6/30 05:36, Carl Love wrote:
> Kewen:
>
> On Wed, 2023-06-28 at 16:35 +0800, Kewen.Lin wrote:
>>> Yea, I was going with a runnable test and didn't include the
>>> instruction counts. Added back in. Rather then doing by processor
>>> version (P8, P9, P10) I was able to do it by
ld well on
power for 40+ different ports.
Is it ok for trunk?
gcc/ChangeLog:
* tree.h (wi::from_mpz): Hide from GENERATOR_FILE.
---
gcc/tree.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/tree.h b/gcc/tree.h
index 1854fe4a7d4..7e92a12f9cb 100644
--- a/gcc/tree.h
+++ b/
Is it ok for trunk?
BR,
Kewen
--
PR tree-optimization/110248
gcc/ChangeLog:
* coretypes.h (class code_helper): Add forward declaration.
* doc/tm.texi: Regenerate.
* lra-constraints.cc (valid_address_p): Call target hook
targetm.addr_space.legitimate_add
related {strict_,}memory_address_addr_space_p
and valid_mem_ref_p functions as well.
Bootstrapped and regtested on x86_64-redhat-linux and
powerpc64{,le}-linux-gnu.
Is it ok for trunk?
BR,
Kewen
-
PR tree-optimization/110248
gcc/ChangeLog:
* recog.cc
eems quite fragile.
Bootstrapped and regtested on powerpc64-linux-gnu
P7/P8/P9 and powerpc64le-linux-gnu P9/P10.
Is it ok for trunk?
BR,
Kewen
--
PR tree-optimization/110248
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Check if
the given c
only for direct uses in the targets?
It's only for the direct uses in target codes, the call
sites in generic code of these hooks would use the given
code_helper type variable or an explicit ERROR_MARK, they
don't require target codes to set that.
>
> It looks OK in general but
load_calls.
>> For now, the implementation just follows the handlings in
>> vect_model_load_cost, it isn't so good, so placing one
>> FIXME for any further improvement. This patch should not
>> cause any functional changes.
>>
>> gcc/ChangeLog:
>&g
uses, adding one argument HOIST_P aims to avoid the actual
>> hoisting during costing phase.
>>
>> gcc/ChangeLog:
>>
>> * tree-vect-stmts.cc (hoist_defs_of_uses): Add one argument HOIST_P.
>> (vectorizable_load): Adju
handlings in function
vect_model_load_cost. This patch shouldn't have any
functional changes.
gcc/ChangeLog:
* tree-vect-stmts.cc (vectorizable_load): Adjust the cost handling on
VMAT_GATHER_SCATTER without calling vect_model_load_cost.
(vect_model_load_cost): Adjut t
This is version v2 rebasing from latest trunk.
=
This patch adjusts the cost handling on VMAT_CONTIGUOUS in
function vectorizable_load. We don't call function
vect_model_load_cost for it any more. It removes function
vect_model_load_cost which becomes useless and unreachable
now.
Hi Richard,
on 2023/7/2 16:58, Richard Sandiford wrote:
> Kewen Lin writes:
>> @@ -9743,11 +9739,23 @@ vectorizable_load (vec_info *vinfo,
>>unsigned int n_groups = 0;
>>for (j = 0; j < ncopies; j++)
>> {
>> - if (nloads > 1)
>> + if (nloads > 1 && !costing_p)
>>
Hi Richi,
Thanks for your review comments on this and some others!
on 2023/6/30 19:37, Richard Biener wrote:
> On Tue, Jun 13, 2023 at 4:07 AM Kewen Lin wrote:
>>
>> This patch series follows Richi's suggestion at the link [1],
>> which suggest structuring vectorizable_load to make costing
>> ne
Hi Carl,
on 2023/7/3 23:57, Carl Love wrote:
> Kewen:
>
> On Fri, 2023-06-30 at 15:20 -0700, Carl Love wrote:
>> Segher never liked the above way of looking at the assembly. He
>> prefers:
>> gcc -S -g -mcpu=power8 -o vsx-vector-6-func-2lop.s vsx-vector-6-
>
Hi Carl,
on 2023/6/30 05:36, Carl Love wrote:
> GCC maintainers:
>
> Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
> of the scan-assembler-times checks to cover multiple similar
> instructions. Change the function check macro to a macro to generate a
&
vpternlog is also used for optimization which doesn't need any valid
input operand, in that case, the destination is used as input in the
instruction and that creates a false dependence.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready to push to trunk.
gcc/ChangeLog:
Hi Jeff,
on 2023/7/4 10:18, Jiufu Guo via Gcc-patches wrote:
> Hi,
>
> If a constant is possible to be rotated to/from a positive or negative
> value from "li", then "li;rotldi" can be used to build the constant.
>
> Compare with the previous version:
>
PR target/110438
gcc/ChangeLog:
* config/i386/i386.cc (standard_sse_constant_opcode): Emit PXOR before VPTERNLOG.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr110438-1.c: New test.
* gcc.target/i386/pr110438-2.c: New test.
* gcc.target/i386/pr110438-3.c: New test
ot vect "permutation requires at
least three vectors"
FAIL: gcc.dg/vect/slp-perm-9.c scan-tree-dump-times vect "vectorizing stmts
using SLP" 1
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2281/usr
--enable-clocale
the first parameter of fwrite should be the const char* __s which want write to
FILE *__file,
rather than the FILE *__file write to the FILE *__file.
0001-Fix-fwrite-error-parameter.txt
Description: Binary data
For testcase
void __cond_swap(double* __x, double* __y) {
bool __r = (*__x < *__y);
auto __tmp = __r ? *__x : *__y;
*__y = __r ? *__y : *__x;
*__x = __tmp;
}
GCC-14 with -O2 and -march=x86-64 options generates the following code:
__cond_swap(double*, double*):
movsd x
They should have same cost as vector mode since both generate
pand/pandn/pxor/por instruction.
Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
DF/SFmode AND/IOR/XOR/ANDN operations
t the min/max pattern.
Operands order in MINSS matters for signed zero and NANs, since the
instruction always returns second operand when any operand is NAN or
both operands are zero.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/1
-assembler-not vpternlogq[ \\t]
FAIL: gcc.target/i386/pr53652-1.c scan-assembler-times pandn[ \\t] 2
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2310/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse
-assembler-times pandn 2
FAIL: gcc.target/i386/pr100711-2.c scan-assembler-times vpandn 8
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2314/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable
+; False dependency happens on destination register which is not really
+; used when moving all ones to vector register
+(define_split
+ [(set (match_operand:VMOVE 0 "register_operand")
+ (match_operand:VMOVE 1 "int_float_vector_all_ones_operand"))]
+ "TARGET_AVX512F && reload_completed
+
Hi Carl,
on 2023/7/6 23:33, Carl Love wrote:
> GCC maintainers:
>
> Ver 4. Fixed a few typos. Redid the tests to create separate run and
> compile tests.
Thanks! This new version looks good, excepting that we need vsx_hw
for run and two nits, see below.
>
> Ver 3. A
Hi Carl,
Some more minor comments are inline below on top of Peter's insightful
review comments.
on 2023/7/1 08:58, Carl Love wrote:
>
> GCC maintainers:
>
> Ver 2, Went back thru the requirements and emails. Not sure where I
> came up with the requirement for an ove
on 2023/7/7 07:00, Peter Bergner wrote:
> On 7/6/23 5:54 PM, Peter Bergner wrote:
>> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
>>> +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_2.c
>>> @@ -0,0 +1,153 @@
>>> +/* { dg-do run { target {
This patch adds pre_reload splitter to detect the min/max pattern.
Operands order in MINSS matters for signed zero and NANs, since the
instruction always returns second operand when any operand is NAN or
both operands are zero.
gcc/ChangeLog:
PR target/110170
* config/i386/i386
uot; 0
FAIL: gcc.dg/pr43864.c scan-tree-dump-times pre "myfree \\(" 1
FAIL: gcc.dg/unroll-7.c scan-rtl-dump-not loop2_unroll "Invalid sum"
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2383/usr
--enable-clocale=gnu
scan-assembler-not \\mmovzb
FAIL: gcc.target/i386/pr91681-1.c scan-assembler-not xor
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r14-2386/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable
.
Ready to push to trunk.
gcc/ChangeLog:
PR target/110438
PR target/110202
* config/i386/predicates.md
(int_float_vector_all_ones_operand): New predicate.
* config/i386/sse.md (*vmov_constm1_pternlog_false_dep): New
d
...
>> mask__17.11_43 = vect__4.10_41 != { 0, ... };
>> vec_mask_and_46 = loop_mask_40 & mask__17.11_43;
>> ...
>> vect__33.16_51 = .COND_ADD (vec_mask_and_46, vect_result_18.7_37,
>> vect__7.14_47, vect_result_18.7_37);
>> ...
>&g
Hi Carl,
on 2023/7/8 04:40, Carl Love wrote:
>
> GCC maintainers:
>
> Ver 5. Removed -compile from the names of the compile only tests. Fixed
> up the reference to the compile file names in the .h file headers.
> Replaced powerpc_vsx_ok with vsx_hw in the run test files. R
on 2023/7/11 07:11, Peter Bergner wrote:
> On 6/29/23 4:31 AM, Kewen.Lin via Gcc-patches wrote:
>> This is okay for trunk (no backports needed btw), this fix can even be
>> taken as obvious, thanks!
>>
>>>
>>> 2023-06-07 Jeevitha Palanisamy
>>
Hi Juzhe,
> Hi, Kewen.
>
> You mean COND_LEN_* family I added is unlikely used by power in the future?
Since AFAIK there is no plan to extend len family on Power, it's very likely
that
Power will have no chance to leverage them, so yes.
> Could you revise them to make it possible used by power
Similar like we did for cmpxchg, but extended to all
ix86_comparison_int_operator since cmpccxadd set EFLAGS exactly same
as CMP.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,},
Ok for trunk?
gcc/ChangeLog:
PR target/110591
* config/i386/sync.md (cmpccxadd_): Add a new
dency when destination is also used
in source. So either a pxor should be inserted, or input operand
should be set with constraint '0'.
gcc/ChangeLog:
PR target/110438
PR target/110202
* config/i386/predicates.md
(int_float_vector_all_ones_operand)
on 2023/7/11 03:18, Carl Love wrote:
> On Fri, 2023-07-07 at 12:06 +0800, Kewen.Lin wrote:
>> Hi Carl,
>>
>> Some more minor comments are inline below on top of Peter's
>> insightful
>> review comments.
>>
>> on 2023/7/1 08:58, Carl Love wrote:
&
Hi Carl,
Excepting for Peter's review comments, some nits are inline below.
on 2023/7/11 03:18, Carl Love wrote:
>
> GCC maintainers:
>
> Ver 3, Renamed the patch per comments on ver 2. Previous subject line
> was " [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add
+ cmpl + jcc/setcc to cmpccxadd + jcc/setcc when FLAGS_REG is dead
after jcc/setcc plus adjusting code for jcc/setcc.
gcc/ChangeLog:
PR target/110591
* config/i386/sync.md (cmpccxadd_): Adjust the pattern
to explicitly set FLAGS_REG like *cmp_1, also add extra
3
Antony Polukhin 2023-07-11 09:51:58 UTC
There's a typo at
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/g%2B%2B.target/i386/pr110170.C;h=e638b12a5ee2264ecef77acca86432a9f24b103b;hb=d41a57c46df6f8f7dae0c0a8b349e734806a837b#l87
It should be `|| !test3() || !test3r()` rather
Hi Richard,
on 2023/1/27 19:08, Richard Sandiford via Gcc-patches wrote:
> PR96373 points out that a predicated SVE loop currently converts
> trapping unconditional ops into unpredicated vector ops. Doing
> the operation on inactive lanes can then raise an exception.
>
> As disc
on 2023/2/13 21:57, Richard Sandiford wrote:
> "Kewen.Lin" writes:
>> Hi Richard,
>>
>> on 2023/1/27 19:08, Richard Sandiford via Gcc-patches wrote:
>>> PR96373 points out that a predicated SVE loop currently converts
>>> trapping unconditional
On Fri, Jan 20, 2023 at 10:21 PM Jerry DeLisle via Fortran
wrote:
>
> Hi all,
>
> Similar to a patch I committed a while ago for Cygwin, the attached
> patch allows it to pass on the mingw version of gfortran.
>
> It is trivial.
>
> Ok for trunk?
>
> Regards,
>
> Jerry
ping
On Wed, Feb 15, 2023 at 10:24 AM Eric Botcazou via Gcc-patches
wrote:
>
> Hi,
>
> this is the incompatibility of -fstack-clash-protection with Windows SEH. Now
> the Windows ports always enable TARGET_STACK_PROBE, which means that the stack
> is always probed (out of line
7,8,9}
and powerpc64le-linux-gnu P10.
Is it ok for trunk?
BR,
Kewen
-
PR target/108699
gcc/ChangeLog:
* config/rs6000/altivec.md (*p9v_parity2): Rename to ...
(p9v_parityb2): ... this. Adjust pattern with UNSPEC_PARITYB,
and replace mode_iterator VParity w
Hi Segher,
Thanks for the review comments!
on 2023/2/16 19:14, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Feb 16, 2023 at 05:23:40PM +0800, Kewen.Lin wrote:
>> This patch is to fix the handling with one more pre-insn
>> vpopcntb. It also fixes an oversight having V8HI in VEC_IP,
>> replaces VP
jr ra
However, there may be some optimization opportunates after
the mode precision adjustment. It can be token care of in
the RISC-V backend in the underlying separted PR(s).
PR 108185
PR 108654
gcc/ChangeLog:
* config/riscv/riscv-modes.def
Hi Segher,
Thanks for the comments!
on 2023/2/16 23:10, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Feb 16, 2023 at 08:06:02PM +0800, Kewen.Lin wrote:
>> on 2023/2/16 19:14, Segher Boessenkool wrote:
>>> On Thu, Feb 16, 2023 at 05:23:40PM +0800, Kewen.Lin wrote:
This patch is to fix the han
On Thu, Feb 16, 2023 at 3:16 AM Eric Botcazou wrote:
>
> > This fixes dg.exp/stack-check-2.c, -7, 8, and -16.c, which is great!
>
> Try the attached patch.
Well... that patch just marks all of the tests as unsupported. But
for example, the ones quoted above run, work, and pass. And when they
di
PR target/108699
gcc/ChangeLog:
* config/rs6000/altivec.md (*p9v_parity2): Rename to ...
(parityb2): ... this.
* config/rs6000/rs6000-builtins.def (VPRTYBD): Replace parityv2di2 with
paritybv2di2.
(VPRTYBW): Replace parityv4si2 with parityb
}
and powerpc64le-linux-gnu P10.
Is it ok for trunk?
BR,
Kewen
-
PR target/108807
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_expand_vector_set_var_p9): Fix gen
function for permutation control vector by considering big endianness.
---
gcc/config/rs6000/rs6000.cc
On Sat, Feb 18, 2023, 17:32 Gerald Pfeifer wrote:
> That was a bit too much in terms of additions things. :-)
>
> Pushed.
>
> Gerald
> ---
> htdocs/gcc-12/changes.html | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-1
en. :)
>
> Something longer and less confusing please. Or maybe just with the insn
> name, that isn't a problem in the machine desription (as it is for
> builtin names or other user-facing stuff). "rs6000_vprtyb" maybe?
Thanks for the suggestion! Will go with "rs6000_vprtyb" if the others in
v2 [1] look good to you.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612212.html
BR,
Kewen
R
> target/107299
> | Message-ID:
>
> In terms of history, I wrote the original code just as I was starting to test
> GCC on systems where IEEE 128-bit long double was the default. At the time,
> we
> had not yet started mangling the built-in function names as a way to bridge
EE 128-bit types used in libgcc.
>
> At the moment, we cannot build GCC when the target uses IEEE 128-bit long
> doubles, such as building the compiler for a native Fedora 36 system. The
> build dies when it is trying to build the _mulkc3.c and _divkc3 modules.
>
> This patch
pc64-linux BE and LE with no
> regressions.
>
> Thanks
> Gui Haochen
>
>
> ChangeLog
> 2023-02-20 Haochen Gui
>
> gcc/
> * config/rs6000/altivec.md (*altivec_vsldoi_dup_): New
> insn_and_split to merge two vsldoi.
>
> gcc/testsuite/
>
^\\n]* = foo\\.simdclone" 2
FAIL: gcc.dg/vect/vect-simd-clone-18.c scan-tree-dump-times vect "[\\n\\r]
[^\\n]* = foo\\.simdclone" 2
FAIL: gcc.dg/vect/vect-simd-clone-18e.c scan-tree-dump-times vect "[\\n\\r]
[^\\n]* = foo\\.simdclone" 3
FAIL: gcc.dg/vect/vect-simd-clone-1
On Wed, Feb 15, 2023, 08:45 Jonathan Yong via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/harden-sls-6.c: fix warning on LLP64
> targets.
>
> Attached patch OK?
Ping
On Tue, Feb 14, 2023, 05:42 Jonathan Yong via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Attached patches OK?
Ping
? x : 0; }
the current asm output in rv64gc_zba_zbb
li rtmp,0
max a0,a0,rtmp
could be optimized into
max a0,a0,zero
gcc/ChangeLog:
* config/riscv/bitmanip.md: allow 0 constant in max/min
pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-03.c: New test.
---
gcc/config/ri
-linux-gnu P7/P8/P9 and
powerpc64le-linux-gnu P9/P10.
I'm going to push this soon if no objections.
BR,
Kewen
-----
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/bfp/scalar-test-data-class-12.c: Adjust with
has_arch_ppc64 effective target.
* gcc.target/powerpc/bfp/vec
9/P10.
I'm going to push this soon if no objections.
BR,
Kewen
-
PR testsuite/108730
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/bfp/scalar-test-neg-8.c: Adjust with lp64
effective target requirement.
---
gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c | 1
Hi,
On BE, the extracted index for the leftmost element is 0
rather than 1, adjust the test case accordingly.
Tested on powerpc64-linux-gnu P7/P8/P9 and
powerpc64le-linux-gnu P9/P10.
I'm going to push this soon if no objections.
BR,
Kewen
-
PR testsuite/108810
gcc/test
Hi,
Compiled with cpu type Power9 or later, GCC generates
xxspltib rather than vspltis*, so adjust the test
case scanning content accordingly.
Tested on powerpc64-linux-gnu P7/P8/P9 and
powerpc64le-linux-gnu P9/P10.
I'm going to push this soon if no objections.
BR,
Kewen
-
.
I'm going to push this soon if no objections.
BR,
Kewen
-----
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/bfp/scalar-test-data-class-14.c: Adjust with
int128 effective target requirement.
* gcc.target/powerpc/bfp/scalar-test-data-class-15.c: Likewise.
---
On Thu, Feb 16, 2023, 11:10 LIU Hao via Gcc-patches
wrote:
>
> --
> Best regards,
> LIU Hao
>
Ping
>
e is an example. It doesn't have a unique memory presentation
> for some real values. So it may not pass the verification. The new test
> case shows the problem.
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
>
> Thanks
> Gui Haochen
&g
hr-3.c target llp64 (test for warnings, line 9)
with GCC configured with
../../gcc/configure
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r13-6414/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable-languages=c,c++,fortran --enab
Hi,
As PR108727 shows, when cleanup code called by the stack
unwinder calls function _Unwind_Resume, it goes via plt
stub like:
function .plt_call._Unwind_Resume:
=> 0x10003580 <+0>: std r2,40(r1)
0x10003584 <+4>: ld r12,-31760(r2)
0x1000
inux-gnu P7/P8/P9 and
powerpc64le-linux-gnu P9/P10.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613302.html
BR,
Kewen
-
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/ppc-fortran/ppc-fortran.exp: Override
gcc_{warning,error}_prefix with Fortran specific one used
Hi Haochen,
on 2023/3/3 20:54, Tobias Burnus wrote:
> Hi Haochen,
>
> On 03.03.23 10:56, HAO CHEN GUI via Gcc-patches wrote:
>> Sure, I will merge it into the patch and do the regression test.
> Thanks :-)
>> Additionally, Kewen suggested:
>>>> Since this t
Hi Peter,
on 2023/3/9 07:01, Peter Bergner via Gcc-patches wrote:
> PR109073 shows a problem where GCC 11 and GCC 10 do not accept a const
> __vector_pair pointer operand to some MMA builtins, which GCC 12 and later
> correctly accept. Fixed here by initializing the builtins to acc
The reason would be to show that they continue to not ICE as they used to.
No go paths are just as useful as go paths.
On Sat, Mar 11, 2023, 10:57 Jeff Law wrote:
>
>
> On 2/16/23 01:16, Eric Botcazou via Gcc-patches wrote:
> >> This fixes dg.exp/stack-check-2.c, -7, 8, a
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