On Fri, Dec 20, 2024 at 4:27 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 04:22:19PM +0100, Christoph Müllner wrote:
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c
> > @@ -0,0 +1,37 @@
> > +/* { dg-do compile } */
> > +/* { d
-10.c: Rename dg-additional-options
to dg-options and add -msse2 to it.
* gcc.dg/tree-ssa/vector-11.c: Likewise.
* gcc.dg/tree-ssa/vector-8.c: Rename dg-additional-options
to dg-options.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
On Fri, Dec 20, 2024 at 4:51 PM Christoph Müllner
wrote:
>
> On Fri, Dec 20, 2024 at 4:27 PM Jakub Jelinek wrote:
> >
> > On Fri, Dec 20, 2024 at 04:22:19PM +0100, Christoph Müllner wrote:
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.dg/tree-
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 37 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
orwprop.cc (get_vect_selector_index_map):
(recognise_vec_perm_simplify_seq):
(calc_perm_vec_perm_simplify_seqs):
(process_vec_perm_simplify_seq_list):
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/vector-11.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.d
/config/riscv/riscv-common.cc (riscv_get_valid_option_values):
Skip adding mtune entries that are already in the list.
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/gcc/common
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 36 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
On Fri, Dec 20, 2024 at 3:38 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 02:55:51PM +0100, Christoph Müllner wrote:
> > A recent bugfix (eee2891312) for PR117830 also addressed PR118149.
> > This patch adds two test cases for PR118149.
> > These tests are diffe
On Fri, Dec 20, 2024 at 4:07 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 03:56:41PM +0100, Christoph Müllner wrote:
> > > Also, why are you using dg-additional-options in tree-ssa/ ? I think the
> > > default there is just -pedantic-errors which you don't
-10.c: Rename dg-additional-options
to dg-options and add -msse2 to it.
* gcc.dg/tree-ssa/vector-11.c: Likewise.
* gcc.dg/tree-ssa/vector-8.c: Rename dg-additional-options
to dg-options.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 37 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
ingly.
Tested on x86-64.
PR117728
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/satd-hadamard.c: Restrict to aarch64 and x86-64.
* gcc.dg/tree-ssa/vector-8.c: Likewise.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg
On Thu, Nov 21, 2024 at 1:34 PM Sam James wrote:
>
> The default on trunk is --enable-checking=yes,extra (when gcc/DEV-PHASE
> contains "experimental"), otherwise it's --enable-checking=release.
>
> I personally do most testing with --enable-checking=yes,rtl,extra but
> you can do less than that i
: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
index f471877f661..c9a427c4a07 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa
.
This patch adjusts the test condition to fit how the function gets
vectorized after ab18785840d7b8 (and probably further related changes).
Signed-off-by: Christoph Müllner
PR target/117079
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105493.c: Fix expected vectorization
---
gcc
On Tue, Jan 14, 2025 at 1:46 PM Richard Biener wrote:
>
> On Tue, 14 Jan 2025, Christoph Müllner wrote:
>
> > As reported in PR117079, commit ab18785840d7b8 broke the test pr105493.c.
> > When looking at the generated code, we can see that the generated code
> >
On Tue, Jan 14, 2025 at 2:35 PM Richard Biener wrote:
>
> On Tue, 14 Jan 2025, Christoph Müllner wrote:
>
> > On Tue, Jan 14, 2025 at 1:46 PM Richard Biener wrote:
> > >
> > > On Tue, 14 Jan 2025, Christoph Müllner wrote:
> > >
> > > > As
value.
gcc/ChangeLog:
* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Eliminate redundant calls to to_constant().
Signed-off-by: Christoph Müllner
---
gcc/tree-ssa-forwprop.cc | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/tree-ssa
e-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Ensure that shuffle masks are VECTOR_CSTs.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118487.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118487.c | 18 ++
gcc/tree-ssa-forwpr
On Mon, Mar 24, 2025 at 3:44 AM Bohan Lei wrote:
>
> The combine pass can generate an index like (and:DI (mult:DI (reg:DI)
> (const_int scale)) (const_int mask)) when XTheadMemIdx is available.
> LRA may pull it out, and thus a splitter is needed when Zba is not
> available.
>
> A similar splitter
On Wed, Apr 2, 2025 at 5:35 AM Jeff Law wrote:
>
>
> Segher -- there's a combine question near the end...
I've created PR119587 to keep track of this issue.
BR
Christoph
>
>
> On 3/23/25 8:43 PM, Bohan Lei wrote:
> > The combine pass can generate an index like (and:DI (mult:DI (reg:DI)
> > (con
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::riscv_subset_list): Init m_allow_adding_dup.
Reviewed-by: Christoph Müllner
Thanks!
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
alled in insn_info::print_full.
Bootstrapped and regtested x86_64-linux.
gcc/ChangeLog:
* rtl-ssa/insns.h: Fix implementation of has_been_deleted ().
Signed-off-by: Christoph Müllner
---
gcc/rtl-ssa/insns.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/rtl-ssa
On Tue, Jun 24, 2025 at 9:29 PM Richard Sandiford
wrote:
>
> Christoph Müllner writes:
> > insn_info::has_been_deleted () is documented to return true if an
> > instruction is deleted. Such instructions have their `volatile` bit set,
> > which can be tested via rtx_insn:
Jeff and Segher, thanks for the clarifications and hints!
Bohan, I assume you will have a look at this (there is also PR119587
to keep track of it).
BR
Christoph
On Mon, Jun 9, 2025 at 6:28 PM Segher Boessenkool
wrote:
>
> On Mon, Jun 09, 2025 at 08:26:10AM -0600, Jeff Law wrote:
> > On 4/1/25
anged to change INSN in place.
(fold_mem_offsets_single_use): New.
(fold_mem_offsets_multi_use): New.
(pass_fold_mem_offsets::execute): Moved to bottom of file.
(fold_mem_offsets): New.
Signed-off-by: Christoph Müllner
---
gcc/fold-mem-of
On Mon, Jun 30, 2025 at 1:05 PM Richard Sandiford
wrote:
>
> Christoph Müllner writes:
> > This patch converts the fold-mem-offsets pass from DF to RTL-SSA.
> > Along with this conversion, the way the pass collects information
> > was completely reworked. Instead of v
i: Add documentation for 'rnmi' interrupt attribute.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/interrupt-rnmi.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv.cc | 17 +
gcc/config/riscv/riscv.md
t.def: Add allocated group IDs and
group bit positions.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-ext.def | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext
ot;
interrupts.
* gcc.target/riscv/xtheadint-push-pop.c: Likewise.
* gcc.target/riscv/interrupt-umode.c: Removed.
Reported-by: Sam Elliott
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv.cc | 19 ---
gcc/config/risc
[CCing Andrew Pinski, who had the same question]
On 2/15/21 1:12 PM, Richard Earnshaw wrote:
> On 09/12/2020 17:21, Christoph Müllner wrote:
>> From: Christoph Muellner
>>
>> It is possible to call aarch64_declare_function_name() and
>> have cfun not set. Let&#x
On Thu, Mar 4, 2021 at 1:19 AM Andrew Pinski wrote:
> On Wed, Mar 3, 2021 at 4:02 PM Christoph Müllner
> wrote:
> >
> > [CCing Andrew Pinski, who had the same question]
> >
> > On 2/15/21 1:12 PM, Richard Earnshaw wrote:
> > > On 09/12/2020 17:21, Christop
Ping.
On Thu, Jul 29, 2021 at 9:36 PM Christoph Müllner wrote:
>
> On Thu, Jul 29, 2021 at 8:54 PM Palmer Dabbelt wrote:
> >
> > On Tue, 27 Jul 2021 02:32:12 PDT (-0700), cmuell...@gcc.gnu.org wrote:
> > > Ok, so if I understand correctly Palmer and Andrew prefer
&g
Ping.
On Thu, Jul 29, 2021 at 4:33 PM Christoph Muellner
wrote:
>
> The RISC-V cpymemsi expansion is called, whenever the by-pieces
> infrastructure will not be taking care of the builtin expansion.
> Currently, that's the case for e.g. memcpy() with n <= 24 bytes.
> The code emitted by the by-pi
Ping.
On Thu, Aug 5, 2021 at 11:11 AM Christoph Müllner wrote:
>
> Ping.
>
> On Thu, Jul 29, 2021 at 4:33 PM Christoph Muellner
> wrote:
> >
> > The RISC-V cpymemsi expansion is called, whenever the by-pieces
> > infrastructure will not be taking care of the
Ping.
On Thu, Aug 5, 2021 at 11:11 AM Christoph Müllner wrote:
>
> Ping.
>
> On Thu, Jul 29, 2021 at 9:36 PM Christoph Müllner
> wrote:
> >
> > On Thu, Jul 29, 2021 at 8:54 PM Palmer Dabbelt wrote:
> > >
> > > On Tue, 27 Jul 2021 02:32:12 PDT (-0
On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt wrote:
> On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> > Hi Christoph, Kito,
> >
> > On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
> >> This series provides a cleanup of the current atomics implementation
> >> of RISC-V
On Wed, Oct 12, 2022 at 2:15 AM Palmer Dabbelt wrote:
> On Tue, 11 Oct 2022 16:31:25 PDT (-0700), Vineet Gupta wrote:
> >
> >
> > On 10/11/22 13:46, Christoph Müllner wrote:
> >> On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt
> wrote:
> >>
> &
On Fri, Oct 14, 2022 at 1:15 AM Palmer Dabbelt wrote:
> On Thu, 13 Oct 2022 15:39:39 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >
> > On 10/11/22 17:31, Vineet Gupta wrote:
> >>
> >>>
> >>> I expect that the pressure for a proper fix upstream (instead of a
> >>> backward compatible compromise)
On Wed, May 11, 2022 at 2:02 AM Palmer Dabbelt wrote:
>
> [Sorry for cross-posting to a bunch of lists, I figured it'd be best to
> have all the discussions in one thread.]
>
> We currently only support what is defined by official RISC-V
> specifications in the various GNU toolchain projects. The
On Fri, May 13, 2022 at 12:58 PM Florian Weimer wrote:
>
> * Christoph Müllner via Binutils:
>
> > I'd like to add two points to this topic and raise two questions.
> >
> > 1) Accepting vendor extensions = avoidance of fragmentation
> >
> > RISC-V imple
On Tue, Nov 2, 2021 at 8:27 PM Vineet Gupta wrote:
>
> On 7/22/21 6:29 AM, Kito Cheng via Gcc-patches wrote:
> > Could you add a testcase? Otherwise LGTM.
> >
> > Option: -O2 -mtune=thead-c906 -march=rv64gc -mabi=lp64
> > void foo(char *dst){
> > __builtin_memset(dst, 0, 15);
> > }
> >
> > On
On Tue, Nov 2, 2021 at 9:15 PM Vineet Gupta wrote:
>
>
>
> On 11/2/21 1:09 PM, Christoph Müllner wrote:
> >>>> Without overlap_op_by_pieces we get:
> >>>> 8e: 00053023sd zero,0(a0)
> >>>> 92: 00052423
On Thu, Jul 22, 2021 at 10:53 AM Kito Cheng wrote:
>
> It's my first time seeing this hook :p Did you mind describing when we
> need to set it to true?
> I mean when a CPU has some feature then we can/should set it to true?
The by-pieces infrastructure allows to inline builtins quite well and
use
prepare a v2, that uses enables overlap_op_by_pieces if
slow_unaligned_access==false.
>
> On Thu, Jul 22, 2021 at 5:23 PM Christoph Müllner via Gcc-patches
> wrote:
> >
> > On Thu, Jul 22, 2021 at 10:53 AM Kito Cheng wrote:
> > >
> > > It's my first tim
On Thu, Jul 22, 2021 at 2:27 PM Christoph Müllner wrote:
>
> On Thu, Jul 22, 2021 at 11:29 AM Kito Cheng wrote:
> >
> > Sounds like we could just use !tune_param->slow_unaligned_access for
> > TARGET_OVERLAP_OP_BY_PIECES_P?
> > since it improves both performan
On Thu, Jul 22, 2021 at 7:27 PM Palmer Dabbelt wrote:
>
> On Thu, 22 Jul 2021 06:29:46 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> > Could you add a testcase? Otherwise LGTM.
> >
> > Option: -O2 -mtune=thead-c906 -march=rv64gc -mabi=lp64
> > void foo(char *dst){
> >__builtin_memset(dst, 0, 1
ngly.
The new patch can be found here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575864.html
On Thu, Jul 22, 2021 at 8:23 PM Christoph Müllner wrote:
>
> On Thu, Jul 22, 2021 at 7:27 PM Palmer Dabbelt wrote:
> >
> > On Thu, 22 Jul 2021 06:29:46 PDT (-0700), g
Ok, so if I understand correctly Palmer and Andrew prefer
overlap_op_by_pieces to be controlled
by its own field in the riscv_tune_param struct and not by the field
slow_unaligned_access in this struct
(i.e. slow_unaligned_access==false is not enough to imply
overlap_op_by_pieces==true).
I don't h
On Thu, Jul 29, 2021 at 8:54 PM Palmer Dabbelt wrote:
>
> On Tue, 27 Jul 2021 02:32:12 PDT (-0700), cmuell...@gcc.gnu.org wrote:
> > Ok, so if I understand correctly Palmer and Andrew prefer
> > overlap_op_by_pieces to be controlled
> > by its own field in the riscv_tune_param struct and not by th
On Sat, May 1, 2021 at 12:48 AM Jeff Law wrote:
>
>
> On 4/26/2021 5:38 AM, Christoph Muellner via Gcc-patches wrote:
> > [ree] PR rtl-optimization/100264: Handle more PARALLEL SET expressions
> >
> > PR rtl-optimization/100264
> > * ree.c (get_sub_rtx): Ignore SET expressions wi
On Mon, Apr 26, 2021 at 4:40 PM Kito Cheng wrote:
>
> This patch is a good and simple improvement which could be an independent
> patch.
>
> There is only 1 comment from me for this patch, could you also add @
> to cbranch pattern for floating mode, I would prefer make the
> gen_cbranch4 could ha
On Thu, May 6, 2021 at 5:29 AM Jim Wilson wrote:
>
> On Fri, Apr 30, 2021 at 4:10 PM Christoph Müllner via Gcc-patches
> wrote:
>>
>> On Sat, May 1, 2021 at 12:48 AM Jeff Law wrote:
>> > On 4/26/2021 5:38 AM, Christoph Muellner via Gcc-patches wrote:
>>
On Fri, Jan 14, 2022 at 4:42 AM Palmer Dabbelt wrote:
>
> The code generated by -mcmodel=medany is defined to be
> position-independent, but is not guarnteed to function correctly when
> linked into position-independent executables or libraries. See the
> recent discussion at the psABI specificat
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