From: Eric Botcazou
This happens when aggressive optimizations are enabled (i.e. -O2 and above)
because the ivopts pass fails to properly mark the new memory accesses it is
creating as misaligned by means of the build_aligned_type function.
gcc/ada/ChangeLog:
* gcc-interface/utils.cc (m
Status
==
The gcc-12 branch is now frozen for release and closing of
the branch.
Quality Data
Priority # Change from last report
--- ---
P10
P2 572 - 44
P3 112
P4 192
P5
From: Steve Baird
If -gnatwr is enabled, then in some cases a type conversion between two
different Boolean types incorrectly results in a warning that the conversion
is redundant.
gcc/ada/ChangeLog:
* sem_res.adb (Resolve_Type_Conversion): Replace code for
detecting a similar c
From: Eric Botcazou
Initialization procedures are turned into functions under the hood and, even
when they are null (empty), the compiler may generate a convoluted sequence
of instructions that return uninitialized data and, therefore, is useless.
gcc/ada/ChangeLog:
* gcc-interface/tran
From: Eric Botcazou
The second problem occurs on 64-bit platforms where there is a second Out
parameter that is smaller than the access parameter, creating a hole in the
return structure.
gcc/ada/ChangeLog:
* gcc-interface/decl.cc (gnat_to_gnu_subprog_type): In the case of a
sub
From: Eric Botcazou
The debugger cannot correctly interpret the return value in this case.
gcc/ada/ChangeLog:
* gcc-interface/decl.cc (gnat_to_gnu_subprog_type): Only apply the
transformation to integer types.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/gc
On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
wrote:
>
> On Fri, Jul 4, 2025 at 9:46 AM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 3:42 PM Richard Biener
> > wrote:
> > >
> > > On Fri, Jul 4, 2025 at 9:33 AM H.J. Lu wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 2:37 PM Richard Sandiford
> >
On Fri, Jul 4, 2025 at 9:46 AM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 3:42 PM Richard Biener
> wrote:
> >
> > On Fri, Jul 4, 2025 at 9:33 AM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 2:37 PM Richard Sandiford
> > > wrote:
> > > >
> > > > "H.J. Lu" writes:
> > > > > On Thu, Jul 3, 20
On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> wrote:
> >
> > On Fri, Jul 4, 2025 at 9:46 AM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 3:42 PM Richard Biener
> > > wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 9:33 AM H.J. Lu wrote:
>
On Fri, Jul 4, 2025 at 4:10 PM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> > wrote:
> > >
> >
> > /* If we can't trust the parm stack slot to be aligned enough for its
> > ultimate type, don't use that slot afte
On Fri, Jul 4, 2025 at 10:11 AM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> > wrote:
> > >
> > > On Fri, Jul 4, 2025 at 9:46 AM H.J. Lu wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 3:42 PM Richard Biener
> > > > wrot
On Fri, Jul 4, 2025 at 9:33 AM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 2:37 PM Richard Sandiford
> wrote:
> >
> > "H.J. Lu" writes:
> > > On Thu, Jul 3, 2025 at 11:02 PM Richard Sandiford
> > > wrote:
> > >>
> > >> "H.J. Lu" writes:
> > >> > Since a backend may ignore user type alignment for
From: Ronan Desplanques
This patch removes some comments and object definitions that referred to
a hacky use of the Entity field that had been removed by the latest
rework of the internal representation of aspects.
gcc/ada/ChangeLog:
* sem_ch13.adb (Check_Aspect_At_Freeze_Point): Remove
On Fri, Jul 4, 2025 at 3:42 PM Richard Biener
wrote:
>
> On Fri, Jul 4, 2025 at 9:33 AM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 2:37 PM Richard Sandiford
> > wrote:
> > >
> > > "H.J. Lu" writes:
> > > > On Thu, Jul 3, 2025 at 11:02 PM Richard Sandiford
> > > > wrote:
> > > >>
> > > >> "H
From: Piotr Trojanek
Cleanup; technical commit meant to trigger a GNAT continuous builder.
gcc/ada/ChangeLog:
* sem_aux.ads (First_Discriminant): Remove space before period.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_aux.ads | 2 +-
1 file changed, 1 insertio
From: Steve Baird
Even when -gnatw.c is enabled, no warning about a missing component clause
should be generated if the placement of a discriminant of an Unchecked_Union
type is left unspecified in a record representation clause (such a discriminant
occupies no storage). In determining whether to
From: Ronan Desplanques
The format string used for the error in that case requires setting the
Error_Msg_Name_1 global variable. This was not done so this patch adds
the missing assignment.
gcc/ada/ChangeLog:
* sem_ch13.adb (Analyze_Aspect_Specifications): Fix error emission.
Tested on
From: Ronan Desplanques
The newly introduced Finalizable aspect makes it possible to derive from
a type that is not tagged but has a Finalize primitive. This patch fixes
problems where overridings of the Finalize primitive were ignored.
gcc/ada/ChangeLog:
* exp_ch7.adb (Make_Final_Call)
From: Steve Baird
Improve the error message that is generated when the size of tagged type
exceeds a Size'Class limit specified for an ancestor type.
gcc/ada/ChangeLog:
* mutably_tagged.adb (Make_CW_Size_Compile_Check): Include the
value of the Size'Class limit in the message ge
From: Bob Duff
Improve documentation of pragma Short_Circuit_And_Or.
Also disallow renamings, because the semantics as currently
implemented is confusing.
gcc/ada/ChangeLog:
* doc/gnat_rm/implementation_defined_pragmas.rst
(Short_Circuit_And_Or): Add more documentation.
From: Eric Botcazou
We fail to use the implementation permission given by RM 13.9(12) because
the array type does not have the Size_Known_At_Compile_Time flag set.
gcc/ada/ChangeLog:
* freeze.adb (Check_Compile_Time_Size): Try harder to see whether
the bounds of array types are
From: Eric Botcazou
We need to make sure that an integer type exists for the given size.
gcc/ada/ChangeLog:
* gcc-interface/decl.cc (gnat_to_gnu_subprog_type): Add guards.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/gcc-interface/decl.cc | 4
1 file changed,
> -Original Message-
> From: Segher Boessenkool
> Sent: Wednesday, July 2, 2025 10:22 PM
> To: Cui, Lili
> Cc: ubiz...@gmail.com; gcc-patches@gcc.gnu.org; Liu, Hongtao
> ; richard.guent...@gmail.com; Michael Matz
>
> Subject: Re: [PATCH V3] x86: Enable separate shrink wrapping
>
> On We
In preparation for the final release from the GCC 12 branch stop
doing snapshots from it.
maintainer-scripts/
* crontab: Stop doing GCC 12 snapshots.
---
maintainer-scripts/crontab | 1 -
1 file changed, 1 deletion(-)
diff --git a/maintainer-scripts/crontab b/maintainer-scripts/crontab
i
On Fri, Jul 4, 2025 at 2:37 PM Richard Sandiford
wrote:
>
> "H.J. Lu" writes:
> > On Thu, Jul 3, 2025 at 11:02 PM Richard Sandiford
> > wrote:
> >>
> >> "H.J. Lu" writes:
> >> > Since a backend may ignore user type alignment for arguments passed on
> >> > stack, update alignment for arguments p
On Fri, Jul 4, 2025 at 4:22 PM Richard Biener
wrote:
>
> On Fri, Jul 4, 2025 at 10:11 AM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> > > wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 9:46 AM H.J. Lu wrote:
> >
This effectively adds 250 new tests, i.e. around 10% more tests.
Tested on x86-64/Linux, applied on the mainline.
2025-07-04 Eric Botcazou
* gcc-interface/Make-lang.in (ACATSDIR): Change to acats-4.
--
Eric Botcazoudiff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-inter
Implements the class mdspan as described in N4950, i.e. without P3029.
It also adds tests for mdspan. This commit completes the implementation
of P0009, i.e. the C++23 part .
PR libstdc++/107761
libstdc++-v3/ChangeLog:
* include/std/mdspan (mdspan): New class.
* src/c++23
This patch series replaces:
https://gcc.gnu.org/pipermail/libstdc++/2025-June/062207.html
Addresses the review comments and improves commit messages. Most notably
the unnecessary patch to "strength" exception guarantees has been
removed (and tests moved into the mdspan commit).
The outstanding ta
Previously the prerequisite of the extents ctors that
static_extent(i) == dynamic_extent || extent(i) == other.extent(i).
was not checked. This commit adds the __glibcxx_assert and test them.
libstdc++-v3/ChangeLog:
* include/std/mdspan (extents): Check prerequisite of the ctor that
On Fri, Jul 4, 2025 at 10:21 AM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 4:10 PM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> > > wrote:
>
> > > >
> > >
> > > /* If we can't trust the parm stack slot to be al
This implements P3029R1. In P3029R1, the CTAD for span is refined to
permit deducing the extent of the span from an integral constant, e.g.
span((T*) ptr, integral_constant{});
is deduced as span. Similarly, in
auto exts = extents(integral_constant);
auto md = mdspan((T*) ptr, integral_con
On Fri, Jul 4, 2025 at 4:28 PM Richard Biener
wrote:
>
> On Fri, Jul 4, 2025 at 10:21 AM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:10 PM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 4:02 PM Richard Biener
> > > > wrote:
>
The class IntLike is used for testing extents with user-defined classes
that convert to int. This commit places the class into a separate header
file. This allows it to be reused across different parts of the mdspan
related testsuite.
libstdc++-v3/ChangeLog:
* testsuite/23_containers/mdsp
The current code uses __mdspan::__fwd_prod(__exts, __rank) to express
computing the size of an extent. This commit adds an function __mdspan::
__size(__exts) to express the idea more directly.
libstdc++-v3/ChangeLog:
* include/std/mdspan (__mdspan::__size): New function.
Signed-off-by: L
Previously, the prerequisite that the arguments passed to operator() are
a multi-dimensional index (of extents()) was not checked.
Both mapping::operator() and mdspan::operator[] have the same
prerequisite. Since, mdspan must check the prerequisite for user-defined
layout mappings, the preference
On Thu, Jul 3, 2025 at 2:02 PM H.J. Lu wrote:
>
> On Wed, Jul 2, 2025 at 9:12 AM H.J. Lu wrote:
> >
> > While working on
> >
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120881
> >
> > I tried to use check-function-bodies to verify that
> >
> > 1: call mcount
> >
> > generated by "-pg" is pla
On Fri, Jul 4, 2025 at 9:15 AM Richard Sandiford
wrote:
>
> aarch64_expand_vector_init contains some divide-and-conquer code
> that tries to load the odd and even elements into 64-bit registers
> and then ZIP them together. On big-endian targets, the even elements
> are more significant than the
On 2025-07-04 08:12, Siddhesh Poyarekar wrote:
On 2025-07-04 08:08, Siddhesh Poyarekar wrote:
gcc/ChangeLog:
I forgot to add the PR number to the ChangeLog entries, I've fixed it in
my commit message.
* tree-object-size.cc (is_access_with_size): New function.
(collect_object_sizes
This generally looks OK to me (including the tests).
+ HOST_WIDE_INT max = ((uint64_t)1 << bitsize) - 1;
Wouldn't a uint64_t type for max be clearer? I guess the worst that can happen
is compiling on a 32-bit host for a 64-bit target and get bitsize == 32 here.
Do we even support this? If
> Am 04.07.2025 um 18:57 schrieb Richard Sandiford :
>
> In the tree codes and optabs, the "hi" in a vector hi/lo pair means
> "most significant" and the "lo" means "least significant", with
> sigificance following GCC's normal endian expectations. Thus on
> big-endian targets, the hi part ha
Andre,
either your patch to coarray.cc is wrong, or the comment in the code
is not concise, or I am too dense to understand the intent of the
change:
diff --git a/gcc/fortran/coarray.cc b/gcc/fortran/coarray.cc
index ef8fd4e42d0..01aac581a74 100644
--- a/gcc/fortran/coarray.cc
+++ b/gcc/fortran/
On 7/4/25 10:21 AM, Richard Sandiford wrote:
ext-dce had:
if (SUBREG_P (dst) && SUBREG_BYTE (dst).is_constant ())
{
bit = subreg_lsb (dst).to_constant ();
if (bit >= HOST_BITS_PER_WIDE_INT)
bit = HOST_BITS_PER_WIDE_INT - 1;
On 7/4/25 1:43 PM, Vineet Gupta wrote:
Hmm. I'm a little surprised that's needed. But there's new rules in
the era of LRA and define_constraint.
Yeah I was wondering why the fallback reg alternative is not already built-in.
Is that meant to catch bugs in the backends ?
I doubt it's meant
On Fri, Jul 4, 2025 at 9:18 AM Richard Sandiford
wrote:
>
> Lowpart subregs are generally disallowed on big-endian SVE vector
> registers, since the first memory element is stored at the least
> significant end of the register, rather than the most significant end.
> (See the comment at the head o
For the gcc.target/loongarch/bitwise-shift-reassoc-clobber.c,
some extensions are eliminated in ext_dce in commit r16-1835.
This will result in the following rtx being generated in the
combine pass:
(insn 12 10 15 2 (set (reg/v:DI 23 $r23 [ x ])
(sign_extend:DI (plus:SI
(su
在 2025/7/4 上午9:52, Xi Ruoyao 写道:
In GCC 16 the compiler is smarter and it optimizes away the unneeded
zero-extension during the expand pass. Thus we can no longer match
and_alsl_reversed.
Drop the scan-rtl-dump for and_alsl_reversed and add scan-assembler-not
against bstrpick.d to detect the
Hi Jerry,
that is very odd, because the test timeout in Opencoarrays is set to 300
seconds at the max. (There are even smaller ones). I can reproduce the
Opencoarray tests hanging for cmake build-type Release. On a Debug build they
fail.
I just repeated testing against OpenCoarrays. The gcc-15 br
Hello!
I've updated the ChangeLog, since I forgot to do it before.
Thanks, Mateusz Zych
On Thu, Jul 3, 2025 at 9:49 PM Mateusz Zych wrote:
> Hello!
>
> I've prepared a patch, which adds all members missing from
> std::numeric_limits<> specializations for integer-class types.
>
> Jonathan, plea
Hi all,
attached patches goes on top of other 6 caf_shmem coarray patches and fixes
missing includes esp. on non-Linux systems. I have tested this on a FreeBSD,
which is very time consuming due to it being fully virtualized on my system.
Regtests ok on x86_64-pc-linux-gnu and aarch64-unknown-free
On 2025-07-04 08:08, Siddhesh Poyarekar wrote:
gcc/ChangeLog:
I forgot to add the PR number to the ChangeLog entries, I've fixed it in
my commit message.
* tree-object-size.cc (is_access_with_size): New function.
(collect_object_sizes_for): Use it.
gcc/testsuite/ChangeLog:
On 7/3/25 21:26, Jeff Law wrote:
>
> On 7/3/25 5:19 PM, Vineet Gupta wrote:
>> Provide a fallback alternaive register contraint for LRA in the light of
>> the tightened "Q" constraint. Cures the following ICE ...
>>
>> | gcc/testsuite/gcc.target/riscv/pr118241-b.cc:31:19: error: unable to
>> ge
On 7/2/25 4:12 PM, Jerry D wrote:
On 7/2/25 9:40 AM, Jerry D wrote:
On 7/2/25 3:14 AM, Andre Vehreschild wrote:
Hi all,
I successfully created a big mess with the previous patch. First of all by
applying an outdated one and secondly by adding the conformance checks for
coranks in a3f1cdd8ed46f
Add a default case to the switch to suppress warnings about unhandled
enumeration values. This is a consteval function, so if the default case
is ever reached it will be an error not silent miscompilation.
libstdc++-v3/ChangeLog:
* include/bits/chrono_io.h (__formatter_duration::_S_spec_f
The overload taking a signed type was returning unsigned and the
overload taking an unsigned type was returning signed.
libstdc++-v3/ChangeLog:
* include/bits/stl_algobase.h (__size_to_integer): Move
misplaced unsigned keyword on __size_to_integer overloads for
__GLIBCXX_T
For allocations with size > alignment and size % alignment != 0 we were
sometimes returning pointers that did not meet the requested aligment.
For example, allocate(24, 16) would select the pool for 24-byte objects
and the second allocation from that pool (at offset 24 bytes into the
pool) is only
Clang wants this change:
--- a/libstdc++-v3/include/std/mdspan
+++ b/libstdc++-v3/include/std/mdspan
@@ -509,7 +509,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
template
concept __mapping_of =
- is_same_v,
+ is_same_v,
_Mapping>;
template
to fix:
/home/jwake
prefetch was recently fixed/tightened (with Q reg constraint) to only
support right address patterns (REG or REG+D with lower 5 bits clear).
However in some cases that's too restrictive for LRA and it fails to
allocate a reg resulting in following ICE...
| gcc/testsuite/gcc.target/riscv/pr118241-b
In r16-1911-g6596f5ab746533 I claimed to have reordered some attributes
for compatibility with Clang, but it looks like I got the Clang
restriction backwards and put them all in the wrong order.
libstdc++-v3/ChangeLog:
PR libstdc++/120949
* include/bits/stl_iterator.h (__normal_it
Spotted this by chance as I saw a similar fixup in comment.
>From comments, I think this is needed, but I've not hit any issues due
to this.
gcc/ChangeLog:
* config/riscv/predicates.md (prefetch_operand): mack 5 bits.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/predicates.md | 4 +
Hi!
https://eel.is/c++draft/stmt.ranged#2
says that in for-range-declaration only type-specifier or constexpr
can appear. As the following testcases show, we've emitted some
diagnostics in most cases, but not for static/thread_local (the patch
handles __thread too) and register in the non-sb case
> Am 04.07.2025 um 23:19 schrieb H.J. Lu :
>
> On Fri, Jul 4, 2025 at 6:07 PM Richard Biener
> wrote:
>>
>>> On Fri, Jul 4, 2025 at 10:33 AM H.J. Lu wrote:
>>>
>>> On Fri, Jul 4, 2025 at 4:28 PM Richard Biener
>>> wrote:
On Fri, Jul 4, 2025 at 10:21 AM H.J. Lu wrote:
>
>>
> Am 04.07.2025 um 19:57 schrieb Siddhesh Poyarekar :
>
> On 2025-07-04 08:12, Siddhesh Poyarekar wrote:
>>> On 2025-07-04 08:08, Siddhesh Poyarekar wrote:
>>> gcc/ChangeLog:
>>>
>> I forgot to add the PR number to the ChangeLog entries, I've fixed it in my
>> commit message.
>>> * tree-
In the tree codes and optabs, the "hi" in a vector hi/lo pair means
"most significant" and the "lo" means "least significant", with
sigificance following GCC's normal endian expectations. Thus on
big-endian targets, the hi part handles the first half of the elements
in memory order and the lo part
Hello,
On Wed, Jun 25 2025, Martin Jambor wrote:
> Hi,
>
> When compiling GCC (with JIT enabled) by clang, it produces a series
> of warning s like this for all uses of DEF_GOACC_BUILTIN_COMPILER and
> DEF_GOMP_BUILTIN_COMPILER in omp-builtins.def:
>
> -
On Wed, Jun 25 2025, Martin Jambor wrote:
> Hi,
>
> when building GCC with clang, it warns that the private member suffix
> in class element_expected_type_with_indirection (defined in
> gcc/c-family/c-format.cc) is not used which indeed looks like it is
> the case. This patch therefore removes it.
On 7/4/25 1:18 PM, Robin Dapp wrote:
This generally looks OK to me (including the tests).
+ HOST_WIDE_INT max = ((uint64_t)1 << bitsize) - 1;
Wouldn't a uint64_t type for max be clearer? I guess the worst that can
happen is compiling on a 32-bit host for a 64-bit target and get bitsize
> -Original Message-
> From: Richard Biener
> Sent: Friday, July 4, 2025 10:42 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Tamar Christina
>
> Subject: [PATCH 1/2] Allow the target to request a masked vector epilogue
>
> Targets recently got the ability to request the v
On Fri, Jul 4, 2025 at 10:33 AM H.J. Lu wrote:
>
> On Fri, Jul 4, 2025 at 4:28 PM Richard Biener
> wrote:
> >
> > On Fri, Jul 4, 2025 at 10:21 AM H.J. Lu wrote:
> > >
> > > On Fri, Jul 4, 2025 at 4:10 PM H.J. Lu wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 4:09 PM H.J. Lu wrote:
> > > > >
> >
The following adds a x86 tuning to enable the use of AVX512 masked
epilogues in cases we heuristically determine it to be not detrimental
by high chance. Basically problematic cases are when there are
data streams that are both stored and loaded from and an outer loop
could end up executing only t
On Wed, Jul 2, 2025 at 7:31 AM wrote:
>
> From: Pan Li
>
> This patch would like to add the middle-end presentation for the
> unsigend saturation mul. Aka set the result of mul to the max
> when overflow.
>
> Take uint8_t as example, we will have:
>
> * SAT_MUL (1, 127) => 127.
> * SAT_MUL (2,
> The following adds a x86 tuning to enable the use of AVX512 masked
> epilogues in cases we heuristically determine it to be not detrimental
> by high chance. Basically problematic cases are when there are
> data streams that are both stored and loaded from and an outer loop
> could end up execut
This patch would like to introduce the combine of vec_dup + vsadd.vv
into vsadd.vx on the cost value of GR2VR. The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test. There will be two cases for the combine:
OK.
--
Regards
Robin
The following avoids translating expressions through volatile
copies.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/120944
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Gate optimizations
invalid when volatile is involved.
* gcc.
On Thu, Jul 3, 2025, 11:48 PM Richard Biener
wrote:
> On Thu, Jul 3, 2025 at 9:34 PM Andrew Pinski
> wrote:
> >
> > These 2 testcases were originally designed for the default -march= of
> > x86_64 so if you pass -march=native (on a target with AVX512 enabled),
> > they will fail. It fix this, we
Spencer Abson writes:
> This patch extends our vec_cmp expander to support partial FP modes.
>
> We use a predicate mode that is narrower the operation's VPRED to govern
> unpacked FP operations under flag_trapping_math, so the expansion must
> handle cases where the comparison's target and govern
On Wed, Jul 2, 2025 at 7:31 AM wrote:
>
> From: Pan Li
>
> This patch would like to try to match the SAT_MUL during
> widening-mul pass, aka below pattern.
>
> NT __attribute__((noinline))
> sat_u_mul_##NT##_fmt_1 (NT a, NT b)
> {
> uint128_t x = (uint128_t)a * (uint128_t)b;
> NT ma
Hi all,
attached patch narrows the use of intrinsic functions in the caf accessor down
to pure elemental functions. This is needed because functions that get extracted
into the caf accessor routine, have no access to the source image's memory. E.g.
team_number() is marked as pure, but takes a poin
Tested x86_64-pc-linux-gnu, applying to trunk and 15.
-- 8< --
Here we were asserting non-zero errorcount, which is not the case if the
parse error was reduced to a warning (or silenced) in a template body. So
check seen_error instead.
PR c++/120575
PR c++/116064
gcc/cp/ChangeL
> Since you are using ssmul here as well please drop the fixed point
> limitation on that optab as well.
I see, that make sense to me. Thanks Richard and will commit with that change
if backend is Ok.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, July 4, 2025 5:58 PM
To: L
Targets recently got the ability to request the vector mode to be
used for a vector epilogue (or the epilogue of a vector epilogue). The
following adds the ability for it to indicate the epilogue should use
loop masking, irrespective of the --param vect-partial-vector-usage
default setting.
The p
Hi,
Following on from the announcement here:
https://gcc.gnu.org/pipermail/gcc/2025-July/246267.html
adding myself as an aarch64 port reviewer.
Pushed to trunk.
Thanks,
Alex
ChangeLog:
* MAINTAINERS (Reviewers): Add myself for the aarch64 port.
diff --git a/MAINTAINERS b/MAINTAINERS
in
r16-1905-g7165ca43caf470 incorrectly returned the size of *_1 for a
GIMPLE_ASSIGN of type:
ptr = *_1;
This is only OK when _1 is set to .ACCESS_WITH_SIZE, since that builtin
expresses the size of *_1 in the form of _1.
gcc/ChangeLog:
* tree-object-size.cc (is_access_with_size): New fu
I didn't realize the white spaces in this file was just spaces
and not tabs. This replaces the 2 tabs that I added for the aarch64
port reviewer to be spaces rather than tabs.
Pushed as obvious.
ChangeLog:
* MAINTAINERS: Replace tabs with spaces.
Signed-off-by: Andrew Pinski
---
MAINT
Hello,
On Wed, Jun 25 2025, Steve Kargl wrote:
> Thanks for cleaning up gfortran code. I was curious about
> what the GNU Coding Standard said about this case, but it
> does not consider initialization of subobjects. I did find
>
>5.3 Clean Use of C Constructs
>...
>Don't make the pr
aarch64_expand_vector_init contains some divide-and-conquer code
that tries to load the odd and even elements into 64-bit registers
and then ZIP them together. On big-endian targets, the even elements
are more significant than the odd elements and so should come second
in the ZIP.
This fixes many
Pushed as eda5a15909c315f0a4a7e76ad083f5f16cf1aef9
Thanks,
On Fri, Jun 27, 2025 at 11:24 AM Jeff Law wrote:
>
>
>
> On 6/27/25 7:59 AM, Oleg Endo wrote:
> >
> > On Fri, 2025-06-27 at 10:51 -0300, Raphael Moreira Zinsly wrote:
> >> A right shift of 31 will become 0 or 1, this can be checked for
Am 04.07.25 um 14:12 schrieb Andre Vehreschild:
Regtests ok on x86_64-pc-linux-gnu and aarch64-unknown-freebsd14.3. Ok for
mainline?
The whole patch set needs including the library needs rigorous and
extensive testing against race conditions, as outlined in
https://gcc.gnu.org/pipermail/fortran
Lowpart subregs are generally disallowed on big-endian SVE vector
registers, since the first memory element is stored at the least
significant end of the register, rather than the most significant end.
(See the comment at the head of aarch64-sve.md for details,
and aarch64_modes_compatible_p for th
ext-dce had:
if (SUBREG_P (dst) && SUBREG_BYTE (dst).is_constant ())
{
bit = subreg_lsb (dst).to_constant ();
if (bit >= HOST_BITS_PER_WIDE_INT)
bit = HOST_BITS_PER_WIDE_INT - 1;
dst = SUBREG_REG (dst);
But a constant
Richard Biener writes:
> @@ -1738,8 +1738,13 @@ protected:
>unsigned int m_suggested_unroll_factor;
>
>/* The suggested mode to be used for a vectorized epilogue or VOIDmode,
> - determined at finish_cost. */
> + determined at finish_cost. m_masked_epilogue is epilogue should u
Additionally, I think we can set __cpp_lib_mdspan.
On 7/4/25 10:29, Luc Grosheintz wrote:
This patch series replaces:
https://gcc.gnu.org/pipermail/libstdc++/2025-June/062207.html
Addresses the review comments and improves commit messages. Most notably
the unnecessary patch to "strength" except
Hi!
On Fri, Jul 04, 2025 at 07:23:23AM +, Cui, Lili wrote:
> > > Initially, I looked at other architectures and disabled the hard frame
> > > pointer,
> >
> > Like aarch? Yeah I always wondered why they don't do it. I decided that
> > that
> > is because of their ABI and architecture stuff
Thanks Robin and Jeff.
> Wouldn't a uint64_t type for max be clearer?
I see, will commit with that change if no surprise from test.
> Do we even support this? If so it's surely not well tested :)
To double confirm, you mean DImode pattern for rv32? The ANYI iterator restrict
the DI to be TAR
Hello,
On Mon, Jun 23 2025, David Malcolm wrote:
> This patch adds various support for debugging diagnostic paths and
> events, intended initially for myself to help with debugging -fanalyzer.
[...]
> diff --git a/gcc/analyzer/sm.cc b/gcc/analyzer/sm.cc
> index 0abbdd69adf..54bd92c31ab 100644
>
On Fri, Jul 4, 2025 at 6:07 PM Richard Biener
wrote:
>
> On Fri, Jul 4, 2025 at 10:33 AM H.J. Lu wrote:
> >
> > On Fri, Jul 4, 2025 at 4:28 PM Richard Biener
> > wrote:
> > >
> > > On Fri, Jul 4, 2025 at 10:21 AM H.J. Lu wrote:
> > > >
> > > > On Fri, Jul 4, 2025 at 4:10 PM H.J. Lu wrote:
> >
A few arm effective-targets call check_effective_target_arm32 even
though they would force a -march=XXX flag which supports Arm and/or
Thumb-2, thus making the arm32 check useless. This has an impact when
the toolchain is configured with a default -march or -mcpu which
supports Thumb-1 only: in su
Like we do in other effective-targets, add
"-mcpu=unset -march=armv8-a"
directly when setting et_arm_v8_neon_flags in arm_v8_neon_ok_nocache,
to avoid having to add these two flags in all users of arm_v8_neon_ok.
This avoids duplication and possible typos / oversights.
gcc/testsuite/ChangeLog:
We get lots of error messages when compiling arm_neon.h under
e.g. -mcpu=cortex-m55, because Neon builtins are enabled only when
!TARGET_HAVE_MVE. This has been the case since MVE support was
introduced.
This patch uses an approach similar to what we do on aarch64, but only
partially since Neon i
ping?
On Mon, 26 May 2025 at 18:08, Christophe Lyon
wrote:
>
> This effective target implicitly expects -march=armv8-a, otherwise
> with a toolchain configured for instance with
> --with-cpu=cortex-m0 --with-float=soft,
> it fails even when trying
> -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp:
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