Re: [PATCH v2] c++, coroutines: Improve diagnostics for awaiter/promise.

> On 11 Jun 2025, at 17:51, Jason Merrill wrote: > > On 6/9/25 3:49 PM, Iain Sandoe wrote: >> Hi Jason, + error_at (loc, "%sawaitable type %qT is not a structure", + extra, o_type); >>> Generally identifiers should be incorporated with %qs, and relying on the >>> %s to

Re: [PATCH] [lra] force reg update after spilling to memory [PR120424]

This patch introduces an ICE in lra-eliminations.cc:1200 for an existing test case. In $builddir/gcc: $ make -k check-gcc RUNTESTFLAGS="--target_board=atmega128-sim avr-torture.exp=pr118591-1.c" FAIL: gcc.target/avr/torture/pr118591-1.c -O1 (internal compiler error: in update_reg_eliminat

[PATCH v1 2/3] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

From: Pan Li Add asm dump check test for vec_duplicate + vmaxu.vv combine to vmaxu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vmaxu.vx combine. * gcc.target/riscv/rvv/autovec/vx_vf/v

[PATCH v1 0/3] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

From: Pan Li This patch would like to introduce the combine of vec_dup + vmaxu.vv into vmaxu.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 2, 15 in test. There will be two cases for the combine: Case 0:

[PATCH v1 1/3] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

From: Pan Li This patch would like to combine the vec_duplicate + vmaxu.vv to the vmaxu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if th

[PATCH, 4 of 4] Use vector pair for memory operations with -mcpu=future

This is patch #4 of 4 to add -mcpu=future support to the PowerPC. In the development for the power10 processor, GCC did not enable using the load vector pair and store vector pair instructions when optimizing things like memory copy. This patch enables using those instructions if -mcpu=future is

[PATCH v1 3/3] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

From: Pan Li Add asm dump check test for vec_duplicate + vmaxu.vv combine to vmaxu.vx, with the GR2VR cost is 0, 1 and 2. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check for vmaxu.vx combine. * gcc.target/riscv/rvv/autovec/vx_vf/vx

Re: [PATCH v1 0/3] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

LGTM 於 2025年6月14日 週六 22:38 寫道： > From: Pan Li > > This patch would like to introduce the combine of vec_dup + vmaxu.vv > into vmaxu.vx on the cost value of GR2VR. The late-combine will take > place if the cost of GR2VR is zero, or reject the combine if non-zero > like 1, 2, 15 in test. There

[PATCH, 1 of 4] Add -mcpu=future support for PowerPC

This is patch #1 of 4 that adds the support that can be used in developing GCC support for future PowerPC processors. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-13 Michael Meissner

[PATCH, 2 of 4] Add tuning support for -mcpu=future

This is patch #2 of 4 to add -mcpu=future support to the PowerPC. This patch makes -mtune=future use the same tuning decision as -mtune=power10 or -mtune=power11. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into

[PATCH, 3 of 4] Add -mcpu=future tests

This is patch #3 of 4 to add -mcpu=future support to the PowerPC. This patch adds simple tests for -mcpu=future. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-13 Michael Meissner gcc/te

Re: [patch,avr,v15] PR120423, PR116389

Georg-Johann Lay writes: > This patch is to avoid PR120423 and PR116389 on avr. > > The PRs are about paradoxical subregs, that ICE after old reload > as follows: > > For rtxes like (subreg:HI (QI) 0), the inner rtx may be reloaded to > (reg:QI 31) which is fine, but the paradoxical subreg will b

[PATCH] c++, coroutines: Avoid UNKNOWN_LOCATION synthesizing code [PR120273].

Hi Jason, >>+ point to the closing brace. */ >>+ input_location = fn_end; >If we're going to have the loc variable at all, how about adjusting it here... Done. >> resume_fn_ptr, zero_resume); >...so you don't need to change these uses... >> finish_expr_stmt (z

[PATCH] c++, coroutines: Handle unevaluated contexts.

Hi Jason, >>It seems that we had not been marking typeid expressions as unevaluated >>so that is also added here. >This seems to be https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68604 >But only some typeid expressions are unevaluated; the >https://eel.is/c++draft/expr#typeid-4 case (polymorphic

Re: [gcc-wwwdocs PATCH] gcc-15: Correct DMR ISA base platform to include AMX-COMPLEX

On Fri, 13 Jun 2025, Haochen Jiang wrote: > I just found that since AMX-COMPLEX is enabled on Diamond Rapids but > not enabled on Granite Rapids, we should use the ISA level from > Granite Rapids D instead of Granite Rapids to show that. > > Since Diamond Rapids is the actual successor of Granite