On Fri, 16 May 2025, Alejandro Colomar wrote:
> Hmmm, I've been trying to find a compromise between readability and
> simplicity, and I think I have something. I've seen some tests that
> define assert() themselves. I like assert(3) because it's more
> readable compared to a conditional plus abo
On Fri, 16 May 2025 09:18:45 -0600, Jeff Law wrote:
>
>
> On 5/16/25 1:32 AM, Jin Ma wrote:
> > Reported-by: huangcunjian
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
> > break and fixbug for elt index.
> Ideally we'd have a testcase for w
On Thu, May 15, 2025 at 9:59 PM Tomasz Kaminski wrote:
>
>
> On Thu, May 15, 2025 at 9:45 PM Rainer Orth
> wrote:
>
>> Hi Tomasz,
>>
>> >> I've a local patch in tree to support __float128 on SPARC, so I'll try
>> >> with an unmodified tree first. However, 2 days ago I could bootstrap
>> >> with
On Wed, May 14, 2025 at 4:06 PM Spencer Abson wrote:
>
> Floating-point to integer conversions can be inexact or invalid (e.g., due to
> overflow or NaN). However, since users of operation_could_trap_p infer the
> bool FP_OPERATION argument from the expression's type, FIX_TRUNC_EXPR is
> consider
On Tue, May 13, 2025 at 12:47 AM Andrew Pinski wrote:
>
> With some functions, there might be the case where every stack variable is a
> live at the end of a
> basic block. If that is the case then it is known that all stack variables
> will conflict with each
> other so there is no reason to go
Hi Tomasz,
> I am not aware of architectures where the additional specialization for
> __float128
> would be useful, so if my patch of changing _GLIBCXX_FORMAT_F128 > 1 to
> _GLIBCXX_FORMAT_F128 == 2
> addressed your build, I can submit it.
with this patch, the sparc-sun-solaris2.11 bootstrap co
Excuse the delay, I was attending the RISC-V Summit Europe.
The series LGTM.
--
Regards
Robin
Reported-by: huangcunjian
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
break and fixbug for elt index.
---
gcc/config/riscv/riscv.cc | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/ris
> Excuse the delay, I was attending the RISC-V Summit Europe.
Thanks Robin, and never mind.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, May 16, 2025 3:26 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp...
From: Pan Li
Some of the previous scalar unsigned SAT_ADD test data are
duplicated in different test files. This patch would like to
move them into a shared header file, to avoid the test data
duplication.
The below test suites are passed for this patch series.
* The rv64gcv fully regression te
This is a leftover of d6d7afcdbc04adb0ec42a44b2d7e05600945af42. After this change, configuration files of
all three thread models are in 'libgcc/config/mingw/'.
The patch has been bootstrapped on {x86_64,i686}-w64-mingw32. ARM64 port is still working in progress and
I will keep an eye on it for
The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
partial_subreg_p in the function copy_value during the RTL pass
regcprop, failing the assertion in
inline bool
partial_subreg_p (machine_mode outermode, machine_mode innermode)
{
/* Modes involved in a subreg must be ordered
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