Re: [PATCH] rtl-optimization/120182 - wrong-code with RTL DSE and constant addresses

On Fri, 9 May 2025, Jakub Jelinek wrote: > On Fri, May 09, 2025 at 09:17:23AM +0200, Richard Biener wrote: > > RTL DSE forms store groups from unique invariant bases but that is > > confused when presented with constant addresses where it assigns > > one store group per unique address. That cause

Re: [PATCH v2] match.pd: Fold (x + y) >> 1 into IFN_AVG_FLOOR (x, y) for vectors

On Thu, 8 May 2025, Pengfei Li wrote: > This patch folds vector expressions of the form (x + y) >> 1 into > IFN_AVG_FLOOR (x, y), reducing instruction count on platforms that > support averaging operations. For example, it can help improve the > codegen on AArch64 from: > add v0.4s, v0.4

[PATCH][14] tree-optimization/120156 - ICE in ptr_derefs_may_alias_p

This picks the ptr_derefs_may_alias_p fix from the PR99954 fix which said: This makes us run into a latent issue in ptr_deref_may_alias_decl_p when the pointer is something like &MEM[0].a in which case we fail to handle non-SSA name pointers. Add code similar to what we have in ptr_derefs_may_ali

Re: [PATCH] rtl-optimization/120182 - wrong-code with RTL DSE and constant addresses

On Fri, May 09, 2025 at 09:34:14AM +0200, Richard Biener wrote: > > Perhaps better CONST_SCALAR_INT_P instead of CONST_INT_P? > > Do we ever get a wide_int for Pmode/ptr_mode? But sure, I can Most likely not. Only if we start supporting > 64-bit pointers. Jakub

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