On Tue, Jan 07, 2025 at 08:36:29PM +0100, Jakub Jelinek wrote:
> Hi!
>
> The following patch fixes ICEs when the new inline asm syntax
> to use C++26 static_assert-like constant expressions in place
> of string literals is used in templates.
> As finish_asm_stmt doesn't do any checking for
> proce
Tamar's recent improvement to improve affine unsigned folding for
exchange2 twiddle code generation for a couple tests in the RVV
testsuite just enough to cause testsuite failures.
I've looked at both tests before/after Tamar's change and the code is
clearly better -- essentially tighter vecto
On 1/7/25 11:18 AM, Richard Sandiford wrote:
Jeff Law writes:
On 1/7/25 2:09 AM, Tsung Chun Lin wrote:
Hi,
Could someone help merge this patch if there are no further concerns?
It'll get addressed. Many contributors have been on holiday and are
still catching up.
FWIW, I'm happy to pus
Hi!
With the following patch I actually get a simple namespace scope structured
binding working with modules.
The core_vals change ensure we actually save/restore DECL_VALUE_EXPR even
for namespace scope vars, the get_merge_kind is based on the assumption
that structured bindings are always uniqu
On 1/2/25 12:13 AM, Tsung Chun Lin wrote:
Don't use the QI vector if its size is equal to UNITS_PER_WORD for
better code generation.
Before patch:
vsetivlizero,4,e8,mf4,ta,ma
vmv.v.i v1,0
addia4,sp,12
vse8.v v1,0(a4)
After patch:
sw zero,12(sp)
I've pushed this patch to
On 1/1/25 2:16 PM, Keith Packard wrote:
I thought I had sent all of my m68k soft float fixes along last year,
but it looks like I managed to leave some out. I had been building
my toolchain from a private repo (oops), which masked my mistake. We're
fixing that by automatically building toolcha
On 1/7/25 10:25, Patrick O'Neill wrote:
On 1/7/25 10:18, Richard Sandiford wrote:
Jeff Law writes:
On 1/7/25 2:09 AM, Tsung Chun Lin wrote:
Hi,
Could someone help merge this patch if there are no further concerns?
It'll get addressed. Many contributors have been on holiday and are
still
> OK for the trunk. Sorry for the delay.
Never mind, thanks Jeff and Happ New Year, 😉!
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, January 7, 2025 9:32 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
ki
On Tue, 2025-01-07 at 15:08 -0500, Marek Polacek wrote:
> On Thu, Dec 19, 2024 at 06:40:19PM -0500, David Malcolm wrote:
> > Consider this case of a bad call to a callback function (perhaps
> > due to C23 changing the meaning of () in function decls):
> >
> > struct p {
> > int (*bar)();
>
> On 6 Jan 2025, at 18:58, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Monday, January 6, 2025 5:54 PM
>> To: Jennifer Schmitz
>> Cc: Richard Biener ; Richard Biener
>> ; Tamar Chri
Noticed while trying to understand when I can expect the GCC 15 branch
to be created: the GCC 15 release criteria page still mentions GCC 14.
I'll push this as obvious.
Are such pages created via a script? If so I am happy to fix it as well.
---
htdocs/gcc-15/criteria.html | 8
1 file c
Hi Jerry,
thanks for the review. Pushed as gcc-15-6615-gd8970909490
with the tweak ;-)
Have a good year and thanks again,
Andre
On Mon, 6 Jan 2025 09:13:27 -0800
Jerry D wrote:
> On 1/6/25 6:21 AM, Andre Vehreschild wrote:
> > Hi all,
> >
> > during looking for something completely di
Currently, the following items are supported:
__attribute__ ((target ("{no-}strict-align")))
__attribute__ ((target ("cmodel=")))
__attribute__ ((target ("arch=")))
__attribute__ ((target ("tune=")))
__attribute__ ((target ("{no-}lsx")))
__attribute_
Add function attributes support for LoongArch.
Currently, the following items are supported:
__attribute__ ((target ("{no-}strict-align")))
__attribute__ ((target ("cmodel=")))
__attribute__ ((target ("arch=")))
__attribute__ ((target ("tune=")))
__attribut
Pushed to r15-6617.
在 2024/12/31 下午7:33, Deng Jianbo 写道:
In LoongArch, currently uses instruction movgr2fr.{d|w} to move zero
from fixed-point register to floating-pointer regsiter for initializing
fp register to zero. When LSX or LASX is enabled, we can use instruction
vxor.v which has lower la
在 2025/1/2 下午5:46, Zhou Zhao 写道:
If SImode reg is continuous left shifted twice, combine related
instruction to one.
gcc/ChangeLog:
* config/loongarch/loongarch.md (extsv_ashlsi3):
New template
Hi, zhaozhou:
The indentation here is wrong, it needs to be aligned with *.
The target pragmas defined correspond to the target function attributes.
This implementation is derived from AArch64.
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_reset_previous_fndecl): Add function declaration.
(loongarch_save_restore_target_globals)
Hi Jerry,
thanks again for the review. Pushed as gcc-15-6618-g25b380dc63c.
Regards,
Andre
On Mon, 6 Jan 2025 09:15:39 -0800
Jerry D wrote:
> On 1/6/25 2:08 AM, Andre Vehreschild wrote:
> > Hi all,
> >
> > attached patch has been rebased to latest trunk. Just pinging!
> >
> > Regtests o
Paul-Antoine Arras wrote:
This is a followup to
ed49709acda OpenMP: C++ front-end support for dispatch + adjust_args.
The call to cp_parser_omp_dispatch only belongs in cp_parser_omp_construct. In
cp_parser_pragma, handle PRAGMA_OMP_DISPATCH by calling cp_parser_omp_construct.
I think this cha
Hi PA,
Paul-Antoine Arras wrote:
On 06/01/2025 17:12, Paul-Antoine Arras wrote:
This is a followup to
084ea8ad584 OpenMP: middle-end support for dispatch + adjust_args.
This patch fixes a bug that caused arguments in an OpenMP dispatch
call to be
modified even when no variant substitution oc
Hi,
Could someone help merge this patch if there are no further concerns?
Thanks,
Jim
Tsung Chun Lin 於 2025年1月2日 週四 下午4:04寫道：
>
> Add CC patchworks...@rivosinc.com
>
> Thanks,
> Jim
>
> Robin Dapp 於 2025年1月2日 週四 下午3:56寫道：
> >
> > > Add an extra test case that we do not create a vector store bu
On Tue, Jan 7, 2025 at 8:37 AM Hongyu Wang wrote:
>
> Hi,
>
> For later processors, the pipeline went deeper so the penalty for
> untaken branch can be larger than before. Add a new parameter
> br_mispredict_scale to describe the penalty, and adopt to
> noce_max_ifcvt_seq_cost hook to allow longer
在 2025/1/7 下午7:49, Lulu Cheng 写道:
在 2025/1/2 下午5:46, Zhou Zhao 写道:
If SImode reg is continuous left shifted twice, combine related
instruction to one.
gcc/ChangeLog:
* config/loongarch/loongarch.md (extsv_ashlsi3):
New template
Hi, zhaozhou:
The indentation here is wrong, it need
Jeff Law 于2025年1月8日周三 07:06写道：
>
>
>
> On 1/1/25 6:42 PM, YunQiang Su wrote:
> > Matthias Klose 于2025年1月1日周三 22:37写道：
> >>
> >> in https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641619.html
> >>
> >> there are two typos in the patch, compared to the local Debian patch,
> >>
> >
> > Oh, so
> From: Liu, Hongtao
> Sent: Friday, January 3, 2025 6:33 PM
>
> > From: Jiang, Haochen
> > Sent: Friday, January 3, 2025 4:55 PM
> >
> > Hi all,
> >
> > The mnemonics for TCVTROWPS2PBF16[H,L] has been changed to
> > TCVTROWPS2BF16[H,L] in ISE056. There will be also some more BF16
> > mnemonics
On Wed, Jan 8, 2025 at 7:51 AM Haochen Jiang wrote:
>
> Hi all,
>
> In ISE, The model number for Diamond Rapids is 13_01H.
> Remove 0x00 since it is unused.
>
> Ref: https://cdrdv2.intel.com/v1/dl/getContent/671368
>
> Ok for trunk?
OK as a trivial patch.
Thanks,
Uros.
>
> Thx,
> Haochen
>
> gc
> LGTM, but please note there are a whole lot of CMOVE issues on x86,
> collected in [1] meta-bug, especially [2].
>
> [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85559
> [2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56309
Thanks for noting this, I've verified my patch have no impact for t
On Tue, 7 Jan 2025, Jakub Jelinek wrote:
> Hi!
>
> DWARF has voted in yesterday https://dwarfstd.org/issues/241209.1.html ,
> which is basically just a guarantee that the DWARF 6 draft
> DW_AT_language_{name,version} attribute codes and content of
> https://dwarfstd.org/languages-v6.html can be u
On Tue, 7 Jan 2025, Eric Botcazou wrote:
> > The fix feels hackish and I wonder how other frontends handle this, but
> > overall thank you for taking care of this peculiarity.
>
> You're welcome. The main Makefile does the same for xgcc -> gcc-cross and,
> as this example shows, every change is
On 1/7/25 10:58 AM, Marek Polacek wrote:
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
OK.
-- >8 --
Here, cxx_eval_outermost_expression gets a sequence of initialization
statements:
D.2912.t = TARGET_EXPR <...>;
TARGET_EXPR ;
D.2922 = 0;
the last of which wasn't conv
Hi all,
In ISE, The model number for Diamond Rapids is 13_01H.
Remove 0x00 since it is unused.
Ref: https://cdrdv2.intel.com/v1/dl/getContent/671368
Ok for trunk?
Thx,
Haochen
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_intel_cpu): Remove 0x00.
---
gcc/common/config/i386/cpuin
On Mon, Dec 2, 2024 at 9:05 PM Richard Biener wrote:
>
> The PR uncovers unchecked constraints on the ability to code-generate
> with SLP but also latent issues with regard to stmt order checking
> since loop (early-break) and BB (for quite some time) vectorization
> are no longer constraint to si
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