On Mon, 29 Jul 2024, Richard Sandiford wrote:
> Richard Biener writes:
> > On Mon, 29 Jul 2024, Jakub Jelinek wrote:
> >> And, for the GET_MODE_INNER, I also meant it for Aarch64/RISC-V VL vectors,
> >> I think those should be considered as true by the hook, not false
> >> because maybe_ne.
> >
>
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, July 30, 2024 2:57 PM
> To: Hongtao Liu
> Cc: Jiang, Haochen ; gcc-patches@gcc.gnu.org;
> Liu, Hongtao ; ubiz...@gmail.com
> Subject: Re: [PATCH v2] i386: Add non-optimize prefetchi intrins
>
> On Tue, Jul 30, 2024 at 09:28:46AM
On Mon, 29 Jul 2024, Filip Kastl wrote:
> Hi Richard,
>
> > > Sorry, I'm not sure if I understand. Are you suggesting something like
> > > this?
> > >
> > > if (idom(default bb) == cond bb)
> > > {
> > > if (exists a path from default bb to final bb)
> > > {
> > > idom(final bb) = cond
Applied the following patchlet to the documentation.
Johann
--
AVR: Propose to use attribute signal(n) via AVR-LibC's ISR_N.
gcc/
* doc/extend.texi (AVR Function Attributes): Propose to use
attribute signal(n) via AVR-LibC's ISR_N from avr/interrupt.h
diff --git a/gcc/doc/exten
Hello!
The attached patch implements adds support for P2591R5 in libstdc++
(concatenation of strings and string_views, approved in Tokyo for C++26).
Thank you,
--
Giuseppe D'Angelo
From 0a4d44196bced41d97d8086343786b52a6f75faf Mon Sep 17 00:00:00 2001
From: Giuseppe D'Angelo
Date: Tue, 30 Jul
On Tue, 30 Jul 2024, Prathamesh Kulkarni wrote:
>
>
> > -Original Message-
> > From: Richard Sandiford
> > Sent: Monday, July 29, 2024 9:43 PM
> > To: Richard Biener
> > Cc: Prathamesh Kulkarni ; gcc-
> > patc...@gcc.gnu.org
> > Subject: Re: Support streaming of poly_int for offloading
As suggested in
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658249.html,
this patch changes the instruction attribute of "*and_compare0" (TST) from
alus_imm to logics_imm.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennife
Dear Richard,
Thanks for the feedback. Great to see this patch approved! I made the changes
as suggested.
Best,
Jennifer
0001-SVE-intrinsics-Add-strength-reduction-for-division-b.patch
Description: Binary data
> On 29 Jul 2024, at 22:55, Richard Sandiford wrote:
>
> External email: Use cauti
On Tue, 30 Jul 2024, 06:21 Ehrnsperger, Markus,
wrote:
> On 2024-07-29 12:16, Jonathan Wakely wrote:
>
> > On Mon, 29 Jul 2024 at 10:45, Jonathan Wakely
> wrote:
> >> On Mon, 29 Jul 2024 at 09:42, Ehrnsperger, Markus
> >> wrote:
> >>> Hi,
> >>>
> >>>
> >>> I'm attaching two files:
> >>>
> >>> 1
Follow up fix:
As the !GCC$ attributes are now added in reverse order,
the 'stdcall' vs. 'fastcall' in the error message swapped order:
"Error: stdcall and fastcall attributes are not compatible" This didn't
show up here with -m64 ("Warning: 'stdcall' attribute ignored") and I
didn't run it wi
Richard Biener writes:
> On Mon, 29 Jul 2024, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Mon, 29 Jul 2024, Jakub Jelinek wrote:
>> >> And, for the GET_MODE_INNER, I also meant it for Aarch64/RISC-V VL
>> >> vectors,
>> >> I think those should be considered as true by the hook,
On Mon, Jul 29, 2024 at 9:26 PM Tobias Burnus wrote:
>
> The problem is code like:
>
>MEM [(c_char * {ref-all})&arr2]
>
> where arr2 is the value expr '*arr2$13$linkptr'
> (i.e. indirect ref + decl name).
>
> Insidepass_omp_target_link::execute, there is a call to
> gimple_regimplify_operands
Richard Biener writes:
> On Tue, 30 Jul 2024, Prathamesh Kulkarni wrote:
>
>>
>>
>> > -Original Message-
>> > From: Richard Sandiford
>> > Sent: Monday, July 29, 2024 9:43 PM
>> > To: Richard Biener
>> > Cc: Prathamesh Kulkarni ; gcc-
>> > patc...@gcc.gnu.org
>> > Subject: Re: Support
On Tue, Jul 30, 2024 at 5:08 AM wrote:
>
> From: Pan Li
>
> For some target like target=amdgcn-amdhsa, we need to take care of
> vector bool types prior to general vector mode types. Or we may have
> the asm check failure as below.
>
> gcc.target/gcn/cond_smax_1.c scan-assembler-times \\tv_cmp_
On Tue, 30 Jul 2024, Richard Sandiford wrote:
> Richard Biener writes:
> > On Tue, 30 Jul 2024, Prathamesh Kulkarni wrote:
> >
> >>
> >>
> >> > -Original Message-
> >> > From: Richard Sandiford
> >> > Sent: Monday, July 29, 2024 9:43 PM
> >> > To: Richard Biener
> >> > Cc: Prathamesh
Hi,
v3 of patch 2/2 uses your suggested fix about using extra_cost as an
adjustment.
I did not introduce the ARM_INSN_COST macro you suggested because it seems
there's only a handful (maybe two) of cases where it could be used, and I
thought it wouldn't make the code really easier to understand
> -Original Message-
> From: Richard Biener
> Sent: Thursday, July 18, 2024 10:00 AM
> To: Tamar Christina
> Cc: GCC Patches ; Richard Sandiford
>
> Subject: RE: [RFC][middle-end] SLP Early break and control flow support in GCC
>
> On Wed, 17 Jul 2024, Tamar Christina wrote:
>
> > > --
On Sun, 24 Mar 2024 at 21:34, Björn Schäpers wrote:
>
> From: Björn Schäpers
>
> This fixes i.e. https://github.com/msys2/MSYS2-packages/issues/1937
> I don't know if I picked the right way to do it.
>
> When acceptable I think the declaration should be moved into
> ops-common.h, since then we co
Richard Biener writes:
> On Tue, 30 Jul 2024, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Tue, 30 Jul 2024, Prathamesh Kulkarni wrote:
>> >
>> >>
>> >>
>> >> > -Original Message-
>> >> > From: Richard Sandiford
>> >> > Sent: Monday, July 29, 2024 9:43 PM
>> >> > To: Ri
On Tue, 30 Jul 2024, Richard Sandiford wrote:
> Richard Biener writes:
> > On Tue, 30 Jul 2024, Richard Sandiford wrote:
> >
> >> Richard Biener writes:
> >> > On Tue, 30 Jul 2024, Prathamesh Kulkarni wrote:
> >> >
> >> >>
> >> >>
> >> >> > -Original Message-
> >> >> > From: Richard Sa
On Tue, Jul 30, 2024 at 11:25:42AM +0200, Richard Biener wrote:
> Only "relevant" stuff should be streamed - the offload code and all
> trees refered to.
Yeah.
> > > I think all current issues are because of poly-* leaking in for cases
> > > where a non-poly would have worked fine, but I have not
On Tue, 30 Jul 2024, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, July 18, 2024 10:00 AM
> > To: Tamar Christina
> > Cc: GCC Patches ; Richard Sandiford
> >
> > Subject: RE: [RFC][middle-end] SLP Early break and control flow support in
> >
The following adds a target hook to specify whether regs of MODE can be
used to transfer bits. The hook is supposed to be used for value-numbering
to decide whether a value loaded in such mode can be punned to another
mode instead of re-loading the value in the other mode and for SRA to
decide whe
The following implements the hook, excluding x87 modes for scalar
and complex float modes.
Bootstrapped and tested on x86_64-unknown-linux-gnu.
OK?
Thanks,
Richard.
* i386.cc (TARGET_MODE_CAN_TRANSFER_BITS): Define.
(ix86_mode_can_transfer_bits): New function.
---
gcc/config/i3
The following addresses another case where x87 FP loads mangle the
bit representation and thus are not suitable for a representative
in other types. VN was value-numbering a later integer load of 'x'
as the same as a former float load of 'x'.
We can use the new TARGET_MODE_CAN_TRANSFER_BITS hook
On Mon, Jul 29, 2024 at 5:15 PM Alejandro Colomar wrote:
>
> The old name was misleading.
>
> While at it, also rename some temporary variables that are used with
> this function, for consistency.
>
> Link:
> https://inbox.sourceware.org/gcc-patches/9fffd80-dca-2c7e-14b-6c9b509a7...@redhat.com/T/
On Tue, Jul 30, 2024 at 12:22:01PM +0200, Richard Biener wrote:
> On Mon, Jul 29, 2024 at 5:15 PM Alejandro Colomar wrote:
> >
> > The old name was misleading.
> >
> > While at it, also rename some temporary variables that are used with
> > this function, for consistency.
> >
> > Link:
> > https:
On Sat, Jul 27, 2024 at 4:29 AM Andrew Pinski wrote:
>
> While working on isel, I found that the current way of doing
> current_properties
> in function can easily make a mistake and having to do stuff like `(a & b )
> == 0`
> and `a |= b;` and `a &= ~b;` is not so obvious what was going on.
> S
This caused the tests to not be run. I may do further passes for non-run
next.
Tested on x86_64-pc-linux-gnu and checked test logs before/after.
PR c/53548
PR target/101529
PR tree-optimization/102359
* c-c++-common/fam-in-union-alone-in-struct-1.c: Fix whitespace
On Tue, Jul 30, 2024 at 12:18 PM Richard Biener wrote:
>
> The following implements the hook, excluding x87 modes for scalar
> and complex float modes.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
>
> OK?
>
> Thanks,
> Richard.
>
> * i386.cc (TARGET_MODE_CAN_TRANSFER_BITS): Def
Jakub Jelinek writes:
> On Tue, Jul 30, 2024 at 11:25:42AM +0200, Richard Biener wrote:
>> Only "relevant" stuff should be streamed - the offload code and all
>> trees refered to.
>
> Yeah.
>
>> > > I think all current issues are because of poly-* leaking in for cases
>> > > where a non-poly would
Richard Biener writes:
> The following adds a target hook to specify whether regs of MODE can be
> used to transfer bits. The hook is supposed to be used for value-numbering
> to decide whether a value loaded in such mode can be punned to another
> mode instead of re-loading the value in the othe
On Tue, Jul 30, 2024 at 1:07 PM Uros Bizjak wrote:
>
> On Tue, Jul 30, 2024 at 12:18 PM Richard Biener wrote:
> >
> > The following implements the hook, excluding x87 modes for scalar
> > and complex float modes.
> >
> > Bootstrapped and tested on x86_64-unknown-linux-gnu.
> >
> > OK?
> >
> > Tha
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, July 30, 2024 3:16 PM
> To: Richard Biener
> Cc: Richard Sandiford ; Prathamesh Kulkarni
> ; gcc-patches@gcc.gnu.org
> Subject: Re: Support streaming of poly_int for offloading when it's
> degree <= accel's NUM_POLY_INT_COEFFS
Hi Jennifer,
> On 30 Jul 2024, at 09:47, Jennifer Schmitz wrote:
>
> Dear Richard,
> Thanks for the feedback. Great to see this patch approved! I made the changes
> as suggested.
> Best,
> Jennifer
> <0001-SVE-intrinsics-Add-strength-reduction-for-division-b.patch>
Thanks, I’m okay with the pa
Jennifer Schmitz writes:
> As suggested in
> https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658249.html,
> this patch changes the instruction attribute of "*and_compare0" (TST)
> from
> alus_imm to logics_imm.
>
> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
> > > Ah, I see you fix those up. Then 2.) is left - the final block. Iff
> > > the final block needs adjustment you know there was a path from
> > > the default case to it which means one of its predecessors is dominated
> > > by the default case? In that case, adjust the dominator to cond_bb,
> Meanwhile I'll look into source code of the rest of the switch conversion
> pass.
> Switch conversion pass inserts conditions similar to what I'm doing so someone
> before me may have already solved how to properly fix dominators in this
> situation.
Oh nevermind. Switch conversion (gen_inboun
On Tue, 30 Jul 2024, Uros Bizjak wrote:
> On Tue, Jul 30, 2024 at 1:07 PM Uros Bizjak wrote:
> >
> > On Tue, Jul 30, 2024 at 12:18 PM Richard Biener wrote:
> > >
> > > The following implements the hook, excluding x87 modes for scalar
> > > and complex float modes.
> > >
> > > Bootstrapped and te
On Tue, 30 Jul 2024, Filip Kastl wrote:
> > > > Ah, I see you fix those up. Then 2.) is left - the final block. Iff
> > > > the final block needs adjustment you know there was a path from
> > > > the default case to it which means one of its predecessors is dominated
> > > > by the default case?
On Tue, Jul 30, 2024 at 02:26:05PM +0200, Richard Biener wrote:
> > > (Which implies that we should introduce TARGET_I387_MATH to parallel
> > > TARGET_SSE_MATH some day...)
> > >
> > > > + default:
> > > > + return false;
> > >
> > > We don't want to enable HFmode for transfers?
>
> Ja
Prathamesh Kulkarni wrote:
Thanks for your suggestions on RFC email, the attached patch adds support for
streaming of poly_int when it's degree <= accel's NUM_POLY_INT_COEFFS.
First, thanks a lot for your patch!
Secondly, it seems as if this patch is indented to fully or partially
fix the fo
On Tue, 30 Jul 2024, Jakub Jelinek wrote:
> On Tue, Jul 30, 2024 at 02:26:05PM +0200, Richard Biener wrote:
> > > > (Which implies that we should introduce TARGET_I387_MATH to parallel
> > > > TARGET_SSE_MATH some day...)
> > > >
> > > > > + default:
> > > > > + return false;
> > > >
>
On Tue, 30 Jul 2024, Richard Biener wrote:
> > Oh, and please add a small comment why we don't use XFmode here.
>
> Will do.
>
> /* Do not enable XFmode, there is padding in it and it suffers
>from normalization upon load like SFmode and DFmode when
>not using S
On Tue, Jul 30, 2024 at 03:43:25PM +0300, Alexander Monakov wrote:
>
> On Tue, 30 Jul 2024, Richard Biener wrote:
>
> > > Oh, and please add a small comment why we don't use XFmode here.
> >
> > Will do.
> >
> > /* Do not enable XFmode, there is padding in it and it suffers
> >
On Tue, 30 Jul 2024, Jakub Jelinek wrote:
> On Tue, Jul 30, 2024 at 03:43:25PM +0300, Alexander Monakov wrote:
> >
> > On Tue, 30 Jul 2024, Richard Biener wrote:
> >
> > > > Oh, and please add a small comment why we don't use XFmode here.
> > >
> > > Will do.
> > >
> > > /* Do not en
On Tue, 30 Jul 2024, Alexander Monakov wrote:
>
> On Tue, 30 Jul 2024, Richard Biener wrote:
>
> > > Oh, and please add a small comment why we don't use XFmode here.
> >
> > Will do.
> >
> > /* Do not enable XFmode, there is padding in it and it suffers
> >from normalizatio
在 2024/7/26 下午8:43, Xi Ruoyao 写道:
We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions. But this
does not always work: for cases like x << 1 | y, the compiler
tends to do
(sign_extend:DI
(ior:SI (ashift:SI (
On Tue, Jul 30, 2024 at 03:00:49PM +0200, Richard Biener wrote:
> As Jakub said the padding is already dealt with in the caller
> though I only added that there for convenience since padding is
> problematic in general.
>
> If you think XFmode is safe to transfer 10 bytes we could enable it,
> I g
On Mon, 29 Jul 2024 at 21:58, Giuseppe D'Angelo wrote:
>
> Hi,
>
> And this is the corresponding change libstdc++.
Thanks for the patch. Do you have a copyright assignment for GCC in
place, or are you covered by a corporate assignment for KDAB?
If not, please complete that process, or contribute
On Tue, 30 Jul 2024 at 08:31, Giuseppe D'Angelo
wrote:
>
> Hello!
>
> The attached patch implements adds support for P2591R5 in libstdc++
> (concatenation of strings and string_views, approved in Tokyo for C++26).
Thanks for this patch as well. This was on my TODO list so I'll be
happy to not hav
The following adds support for vector conditionals in C. The support
was nearly there already but c_objc_common_truthvalue_conversion
rejecting vector types. Instead of letting them pass there unchanged
I chose to instead skip it when parsing conditionals instead as a
variant with less possible f
On 7/30/24 7:01 AM, Lulu Cheng wrote:
在 2024/7/26 下午8:43, Xi Ruoyao 写道:
We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions. But this
does not always work: for cases like x << 1 | y, the compiler
tends to do
(s
> On Jul 30, 2024, at 6:17 AM, Richard Biener wrote:
>
> The following adds a target hook to specify whether regs of MODE can be
> used to transfer bits. The hook is supposed to be used for value-numbering
> to decide whether a value loaded in such mode can be punned to another
> mode instead
On 29/07/2024 13:13, Richard Sandiford wrote:
> Claudio Bantaloukas writes:
>> Unlike most system registers, fpmr can be heavily written to in code that
>> exercises the fp8 functionality. That is because every fp8 instrinsic call
>> can potentially change the value of fpmr.
>> Rather than just
On Tue, 30 Jul 2024 at 14:08, Jonathan Wakely wrote:
>
> On Tue, 30 Jul 2024 at 08:31, Giuseppe D'Angelo
> wrote:
> >
> > Hello!
> >
> > The attached patch implements adds support for P2591R5 in libstdc++
> > (concatenation of strings and string_views, approved in Tokyo for C++26).
>
> Thanks for
On Tue, Jul 30, 2024 at 03:00:49PM +0200, Richard Biener wrote:
> > What mangling fld performs depends on the contents of the FP control
> > word which is awkward.
For float/double loads (FLDS and FLDL) we know format conversion changes
SNaNs to QNaNs, but it's a widening conversion, so e.g. ro
This LWG issue is about to become Tentatively Ready.
Tested x86_64-linux.
-- >8 --
This uses remove_cv_t for the default template argument used for
deducing a type for a braced-init-list used with std::optional and
std::expected.
libstdc++-v3/ChangeLog:
* include/std/expected (expected
On 29/07/2024 08:30, Kyrylo Tkachov wrote:
> Hi Claudio,
>
>> On 26 Jul 2024, at 18:32, Claudio Bantaloukas
>> wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> This introduces the relevant flags to enable access to the fpmr register and
>> fp8 intrinsics, which w
Hi Richard, Jakub,
I've adjusted the ChangeLog; hopefully it'll be good now.
On Tue, Jul 30, 2024 at 12:22:01PM +0200, Richard Biener wrote:
> The changes look good to me, please leave the frontend maintainers
> time to chime in.
Sure; as much as they need. My latest patch
(-Wunterminated-strin
The old name was misleading.
While at it, also rename some temporary variables that are used with
this function, for consistency.
Link:
https://inbox.sourceware.org/gcc-patches/9fffd80-dca-2c7e-14b-6c9b509a7...@redhat.com/T/#m2f661c67c8f7b2c405c8c7fc3152dd85dc729120
Cc: Gabriel Ravier
Cc: Marti
> > IMO, what ought to happen here is that the RA should spill
> > the inner register to memory and load the V4SI back from there.
> > (Or vice versa, for an lvalue.) Obviously that's not very efficient,
> > and so a patch like the above might be useful as an optimisation.[*]
> > But it shouldn't
I've pushed this for https://github.com/msys2/MSYS2-packages/issues/1937
but I'm taking a slightly different approach to Björn's original patch.
Instead of adding __detail::equivalent_win32 I'm adding fs::equiv_files
to do the check for both POSIX and Windows. The logic in do_copy_file
should be
Committed with spaces -> tabs ChangeLog fix.
Patrick
On 7/29/24 20:27, Kito Cheng wrote:
LGTM, thanks :)
On Tue, Jul 30, 2024 at 10:53 AM Patrick O'Neill wrote:
This patch removes the zabha configure check since it's not a breaking change
and updates the existing zaamo/zalrsc comment.
gcc/C
Peter, Kewen:
Per Peter's request, I did the following testing on ltcd97-lp7 which is
a Power 10 running in BE mode.
On 7/29/24 8:47 AM, Peter Bergner wrote:
Maybe the following will work?
+/* { dg-do run { target power10_hw } } */
+/* { dg-do link { target { ! power10_hw } } } */
+/* { d
The problem here is that in generic types of comparisons don't need
to be boolean types (or vector boolean types). And fixes that by making
sure the types of the conditions match before doing the optimization.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR middle-end/
When this pattern was converted from being only dealing with 0/-1, we missed
that if `e == f` is true
then the optimization is wrong and needs an extra check for that.
This changes the patterns to be:
/* (a ? x : y) != (b ? x : y) --> (a^b & (x != y)) ? TRUE : FALSE */
/* (a ? x : y) == (b ? x :
From: Gianluca Guida
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q
(64/128 bit cas for rv32/64) will be added in a future patch.
Extension: https://github.com/riscv/riscv-zacas
Ratification: https://jira.riscv.org/browse/RVS-680
gcc/ChangeLog:
* common/config/riscv
Committed w/changelog fixup/sign-off and sent final version to the lists
here:
https://inbox.sourceware.org/gcc-patches/20240730152448.4089002-1-patr...@rivosinc.com/T/#u
Approved during risc-v patchworks meeting by Jeff Law.
Patrick
On 7/29/24 15:13, Patrick O'Neill wrote:
From: Gianluca Gui
From: Andi Kleen
AVX2 is widely available on x86 and it allows to do the scanner line
check with 32 bytes at a time. The code is similar to the SSE2 code
path, just using AVX and 32 bytes at a time instead of SSE2 16 bytes.
Also adjust the code to allow inlining when the compiler
is built for an
From: Andi Kleen
Host systems with only MMX and no SSE2 should be really rare now.
Let's remove the MMX code path to keep the number of custom
implementations the same.
The SSE2 code path is also somewhat dubious now (nearly everything
should have SSE4 4.2 which is >15 years old now), but the SS
On Tue, Jul 30, 2024 at 8:43 AM Andi Kleen wrote:
>
> From: Andi Kleen
>
> AVX2 is widely available on x86 and it allows to do the scanner line
> check with 32 bytes at a time. The code is similar to the SSE2 code
> path, just using AVX and 32 bytes at a time instead of SSE2 16 bytes.
>
> Also ad
Andrew Pinski writes:
>
> Using the builtin here seems wrong. Why not use the intrinsic
> _mm256_movemask_epi8 ?
I followed the rest of the vectorized code paths. The original reason was that
there was some incompatibility of the intrinsic header with the source
build. I don't know if it's still
PR preprocessor/90581
* c-c++-common/cpp/fmax-include-depth.c: Fix whitespace in dg directive.
---
Committed as obvious.
gcc/testsuite/c-c++-common/cpp/fmax-include-depth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/c-c++-common/cpp/fmax-incl
* gcc.target/aarch64/simd/vmmla.c: Fix whitespace in dg directive.
---
Committed as obvious.
gcc/testsuite/gcc.target/aarch64/simd/vmmla.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmmla.c
b/gcc/testsuite/gcc.target/aarch64/
Nothing seems to change here in reality at least on x86_64-pc-linux-gnu,
but important to fix nonetheless in case people copy it.
PR rtl-optimization/48633
PR tree-optimization/83072
PR tree-optimization/83073
PR tree-optimization/96542
PR tree-optimization/
As documented in PR116131, we might end up with the following
INSN for rv32i_xtheadmemidx after th_memidx_I_c is applied:
(insn 18 14 0 2 (set (mem:SI (plus:SI (reg/f:SI 141)
(ashift:SI (subreg:SI (reg:DI 134 [ a.0_1 ]) 0)
(const_int 2 [0x2]))) [0 S4 A32])
On Mon, Jul 29, 2024 at 12:41 PM Björn Schäpers wrote:
>
> > Instead of deleting those, move them inside the parentheses:
> >
> > typedef VOID (CALLBACK *LDR_DLL_NOTIFICATION)(ULONG,
> > struct dll_notification_data*,
> >
Hi,
On Tue, 30 Jul 2024, Andi Kleen wrote:
> AVX2 is widely available on x86 and it allows to do the scanner line
> check with 32 bytes at a time. The code is similar to the SSE2 code
> path, just using AVX and 32 bytes at a time instead of SSE2 16 bytes.
>
> Also adjust the code to allow inlini
From: Andi Kleen
... that uses -march=native -mtune=native to build a compiler optimized
for the host.
config/ChangeLog:
* bootstrap-native.mk: New file.
gcc/ChangeLog:
* doc/install.texi: Document bootstrap-native.
---
config/bootstrap-native.mk | 1 +
gcc/doc/install.texi
On Tue, Jul 30, 2024 at 08:41:59AM -0700, Andi Kleen wrote:
> From: Andi Kleen
>
> AVX2 is widely available on x86 and it allows to do the scanner line
> check with 32 bytes at a time. The code is similar to the SSE2 code
> path, just using AVX and 32 bytes at a time instead of SSE2 16 bytes.
>
On Tue 2024-07-30 14:34:54, Richard Biener wrote:
> On Tue, 30 Jul 2024, Filip Kastl wrote:
>
> > > > > Ah, I see you fix those up. Then 2.) is left - the final block. Iff
> > > > > the final block needs adjustment you know there was a path from
> > > > > the default case to it which means one o
> Is that from some kind of rigorous measurement under perf? As you
> surely know, 0.6% wall-clock time can be from boost clock variation
> or just run-to-run noise on x86.
I compared it using hyperfine which does rigorous measurements yes.
It was well above the run-to-run variability.
I had some
Hi!
C23 added in N2956 ( https://open-std.org/JTC1/SC22/WG14/www/docs/n2956.htm )
two new attributes, which are described as similar to GCC const and pure
attributes, but they aren't really same and it seems that even the paper
is missing some of the differences.
The paper says unsequenced is the
On Tue, Jul 30, 2024 at 3:00 PM Richard Biener wrote:
>
> On Tue, 30 Jul 2024, Alexander Monakov wrote:
>
> >
> > On Tue, 30 Jul 2024, Richard Biener wrote:
> >
> > > > Oh, and please add a small comment why we don't use XFmode here.
> > >
> > > Will do.
> > >
> > > /* Do not enable XFmode
PR middle-end/54400
PR target/98161
* gcc.dg/vect/bb-slp-layout-18.c: Fix whitespace in dg directive.
* gcc.dg/vect/bb-slp-pr54400.c: Likewise.
* gcc.target/i386/pr98161.c: Likewise.
---
Committed as obvious.
gcc/testsuite/gcc.dg/vect/bb-slp-layout-18.c | 2
On Tue, 30 Jul 2024, Andi Kleen wrote:
> > I have looked at this code before. When AVX2 is available, so is SSSE3,
> > and then a much more efficient approach is available: instead of comparing
> > against \r \n \\ ? one-by-one, build a vector
> >
> > 0 1 2 3 4 5 6 7 8 9a bc
Richard Biener wrote:
On Mon, Jul 29, 2024 at 9:26 PM Tobias Burnus wrote:
Inside pass_omp_target_link::execute, there is a call to
gimple_regimplify_operands but the value expression is not
expanded.[...]
Where is_gimple_mem_ref_addr is defined as:
/* Return true if T is a valid address oper
> Am 30.07.2024 um 19:22 schrieb Alexander Monakov :
>
>
> On Tue, 30 Jul 2024, Andi Kleen wrote:
>>> I have looked at this code before. When AVX2 is available, so is SSSE3,
>>> and then a much more efficient approach is available: instead of comparing
>>> against \r \n \\ ? one-by-one, build
Andi Kleen writes:
> From: Andi Kleen
>
> ... that uses -march=native -mtune=native to build a compiler optimized
> for the host.
>
I like the idea and I'll probably use this. (I can't approve it though.)
> config/ChangeLog:
>
> * bootstrap-native.mk: New file.
>
> gcc/ChangeLog:
>
>
Thanks! Committed
Edwin
On 7/29/2024 6:37 AM, Kito Cheng wrote:
LGTM, although I said no binutils check for zacas and zabha, but B is
a different situation since GCC will add that if zba, zbb and zbs are
all present.
On Thu, Jul 25, 2024 at 7:51 AM Edwin Lu wrote:
Binutils 2.42 and before
PR target/51492
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr51492.c: New test.
Tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/testsuite/gcc.target/i386/pr51492.c
b/gcc/testsuite/gcc.target/i386/pr51492.c
new file mode 100644
index 000..0892e0c79a7
--- /dev/null
+++
> > +BOOT_CFLAGS := -march=native -mtune=native $(BOOT_CFLAGS)
>
> I was under the impression that -mtune=native is useless with
> -march=native. Is that wrong?
On x86 it's right, but not sure about other architectures. I suppose
it doesn't hurt.
-Andi
> On 30 Jul 2024, at 19:01, Andi Kleen wrote:
>
> External email: Use caution opening links or attachments
>
>
>> Is that from some kind of rigorous measurement under perf? As you
>> surely know, 0.6% wall-clock time can be from boost clock variation
>> or just run-to-run noise on x86.
>
>
On 7/28/24 7:58 PM, Xiao Zeng wrote:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105314-rtl.c: Skip zicond.
* gcc.target/riscv/pr105314-rtl32.c: Dotto.
* gcc.target/riscv/pr105314.c: Dotto.
Why do you want to skip zicond for this test?
Jeff
Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* src/c++17/fs_ops.cc: Fix file name in comment.
---
libstdc++-v3/src/c++17/fs_ops.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/src/c++17/fs_ops.cc b/libstdc++-v3/src/c++17/fs_ops.cc
index 7ffdce677
On 7/30/24 10:17 AM, Christoph Müllner wrote:
As documented in PR116131, we might end up with the following
INSN for rv32i_xtheadmemidx after th_memidx_I_c is applied:
(insn 18 14 0 2 (set (mem:SI (plus:SI (reg/f:SI 141)
(ashift:SI (subreg:SI (reg:DI 134 [ a.0_1 ]) 0)
On 7/29/24 8:52 AM, Raphael Zinsly wrote:
On Mon, Jul 29, 2024 at 11:20 AM Jeff Law wrote:
On 7/29/24 6:18 AM, Raphael Zinsly wrote:
On Fri, Jul 26, 2024 at 6:48 PM Jeff Law wrote:
On 7/24/24 12:00 PM, Raphael Moreira Zinsly wrote:
Adds basic support to vector stack-clash protectio
'dg-compile' is not a thing, replace it with 'dg-do compile'.
PR target/68015
PR c++/83979
* c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo.
* g++.dg/pr83979.C: Likewise.
* g++.target/aarch64/sve/acle/general-c++/attributes_2.C: Likewise.
* g
On 7/29/24 6:51 AM, Andrew Burgess wrote:
Thomas Schwinge writes:
Hi!
On 2024-02-10T17:26:01+, Andrew Burgess wrote:
--- a/libiberty/argv.c
+++ b/libiberty/argv.c
@@ -439,17 +442,8 @@ expandargv (int *argcp, char ***argvp)
}
/* Add a NUL terminator. */
buf
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