Re: [PATCH] testsuite: Allow matching `{_1, { 0, 0, 0, 0 }}` for vect/slp-gap-1.c

On 7/9/24 6:19 PM, Andrew Pinski wrote: While working on adding V4QI support to the aarch64 backend, vect/slp-gap-1.c started to fail but only because the regex was failing. Before it was loading use SI (int) and afterwards, we started to use V4QI. The generated code was the same and the gener

Re: [PATCH] Remove expanding complex EQ/NE inside a GIMPLE_RETURN [PR115721]

On 7/9/24 6:05 PM, Andrew Pinski wrote: This code has been dead at least since the move over to tuples in 0-88576-g726a989a8b74bf, when gimple returns could only have a simple expression in it. So let's remove it. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog

[PATCH] recog: Avoid validate_change shortcut for groups [PR115782]

In this PR, due to the -f flags, we ended up with: bb1: r10=r10 ... bb2: r10=r10 ... bb3: ...=r10 with bb1->bb2 and bb1->bb3. late-combine successfully combined the bb1->bb2 def-use and set the insn code to NOOP_MOVE_INSN_CODE. The bb1->bb3 combination then failed for... reasons. At this po

Re: [PATCH v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins

On Tue, 2024-07-09 at 20:21 -0600, Jeff Law wrote: > > > On 7/9/24 8:14 PM, Xi Ruoyao wrote: > > On Tue, 2024-07-09 at 16:10 -0700, Vineet Gupta wrote: > > > On 7/3/24 21:35, Xi Ruoyao wrote: > > > > On Sun, 2024-06-30 at 17:47 -0700, Vineet Gupta wrote: > > > > >    - Don't hardcode SI in patter

Re: [PATCH] rs6000: Error on CPUs and ABIs that don't support the ROP, protection insns [PR114759]

Hi Peter, on 2024/7/10 05:39, Peter Bergner wrote: > Hi Kewen, > > Here is that promised cleanup patch we discussed in the previous patch review. > I'll note this patch is dependent on the previous patch you approved. I have > not pushed that yet (in case you looked) since I'm waiting on Segher

Re: [to-be-committed] [RISC-V] Improve bset generation for another case

On 7/9/24 12:05 PM, Jeff Law wrote: So another minor improvement for bitmanip code generation. Essentially we have a pattern which matches a bset idiom for x = zero_extend (1 << n).   That pattern only handles SI->DI extension. For the QI/HI case the 1

Re: [PATCH] Fix test errors introduced with fix for PR115157

Am Dienstag, dem 09.07.2024 um 19:11 -0300 schrieb Thiago Jung Bauermann: > Hello Martin, > > Martin Uecker writes: > > > BTW: Did you try the other testsuite patch as well? > > > > [PATCH] Fix test errors after r15-1394 for sizeof(int)==sizeof(long) > > [PR115545] > > I hadn't, but I did tod

Re: [RFC/RFA] [PATCH 11/12] Replace the original CRC loops with a faster CRC calculation.

On Wed, Jul 10, 2024 at 3:17 AM Jeff Law wrote: > > > > On 5/24/24 2:42 AM, Mariam Arutunian wrote: > > Specifically, use the following alternatives: If the target > > supports the crc32 instruction, use it directly. If the target > > supports the > > carry-less multiplication instruction, u

Re: [PATCH 3/6] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr

Jeff Law writes: > On 7/9/24 7:12 AM, Christoph Müllner wrote: >> On Tue, Jul 9, 2024 at 3:01 PM Kito Cheng wrote: >>> >>> IIRC Jeff mentions that it may introduce buffer overflow if the input >>> string is long enough. >> >> The manpage states: >>If the allocation causes stack overflow, pro

[PATCH] [APX NF] Add a pass to convert legacy insn to NF insns

Hi, For APX ccmp, current infrastructure will always generate cstore for the ccmp flag user, like cmpe%rcx, %r8 ccmpnel %rax, %rbx seta%dil add %rcx, %r9 add %r9, %rdx testb %dil, %dil je .L2 For such case, the legacy

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