Re: [PATCH] RISC-V: use fclass insns to implement isfinite and isnormal builtins

2024-06-30 Thread Xi Ruoyao
On Fri, 2024-06-28 at 17:53 -0700, Vineet Gupta wrote: > +  UNSPEC_ISFINITE > +  UNSPEC_ISNORMAL You don't really need them. The RTL pattern of define_expand has no use when you expand it via C code and DONE. i.e. you can just code (define_expand "isfinite2" [(match_operand:SI 0 "register_o

[PATCH 1/3] tree-optimization/115701 - factor out maybe_duplicate_ssa_info_at_copy

2024-06-30 Thread Richard Biener
The following factors out the code that preserves SSA info of the LHS of a SSA copy LHS = RHS when LHS is about to be eliminated to RHS. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/115701 * tree-ssanames.h (maybe_duplicate_ssa_info_at_copy): D

[PATCH 2/3] tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_copy

2024-06-30 Thread Richard Biener
The following restricts copying of points-to info from defs that might be in regions invoking UB and are never executed. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/115701 * tree-ssanames.cc (maybe_duplicate_ssa_info_at_copy): Only cop

[PATCH 3/3] Preserve SSA info for more propagated copy

2024-06-30 Thread Richard Biener
Besides VN and copy-prop also CCP and VRP as well as forwprop propagate out copies and thus it's worthwhile to try to preserve range and points-to info there when possible. Note that this also fixes the testcase from PR115701 but that's because we do not actually intersect info but only copy info

[Patch, rtl-optimization, loop-unroll] Loop unroll factor based on register pressure

2024-06-30 Thread Ajit Agarwal
Hello All: This patch determines unroll factor based on loop register pressure. Unroll factor is quotient of max of available registers in loop by number of liveness. If available registers increases unroll factor increases. Wherein unroll factor decreases if number of liveness increases. Loop

[testsuite PATCH] Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c on RedHat.

2024-06-30 Thread Roger Sayle
This patch fixes the 4 FAILs of gcc.target/i386/pr192464-vrndscaleph.c with --target_board='unix{-m32}' on RedHat 7.x. The issue is that this AVX512 test includes the system math.h, and on older systems this provides inline versions of floor, ceil and rint (for the 387). The work around is to de

Re: [PATCH] RISC-V: use fclass insns to implement isfinite and isnormal builtins

2024-06-30 Thread Jeff Law
On 6/29/24 3:07 PM, Vineet Gupta wrote: On 6/29/24 06:44, Jeff Law wrote: +;; fclass instruction output bitmap +;; 0 negative infinity +;; 1 negative normal number. +;; 2 negative subnormal number. +;; 3 -0 +;; 4 +0 +;; 5 positive subnormal number. +;; 6 positive normal number.

[committed] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-06-30 Thread John David Anglin
Fixes mismatched predicate and constraint in xmpyu patterns. The xmpyu instruction doesn't support multiplying a 32-bit const_int with a floating-point register. So, I just removed these patterns. Tested on hppa-unknown-linux-gnu. Committed to trunk. Dave --- hppa: Fix ICE caused by mismatched

Re: [x86 PATCH]: Additional peephole2 to use lea in round-up integer division.

2024-06-30 Thread Uros Bizjak
On Sat, Jun 29, 2024 at 6:21 PM Roger Sayle wrote: > > > A common idiom for implementing an integer division that rounds upwards is > to write (x + y - 1) / y. Conveniently on x86, the two additions to form > the numerator can be performed by a single lea instruction, and indeed gcc > currently g

[to-be-committed] [V2][RISC-V] DCE analysis for extension elimination

2024-06-30 Thread Jeff Law
Changes since V1: Check flag_ext_dce before running the new pass. I'd forgotten that I had removed that part of the gate to facilitate more testing. Turn flag_ext_dce on at -O2 and above. Adjust one of the riscv tests to explicitly avoid vectors Adjust a few aarch64 tests In tbz_2

RE: [x86 PATCH]: Additional peephole2 to use lea in round-up integer division.

2024-06-30 Thread Roger Sayle
Hi Uros, > On Sat, Jun 29, 2024 at 6:21 PM Roger Sayle > wrote: > > A common idiom for implementing an integer division that rounds > > upwards is to write (x + y - 1) / y. Conveniently on x86, the two > > additions to form the numerator can be performed by a single lea > > instruction, and ind

Re: [x86 PATCH]: Additional peephole2 to use lea in round-up integer division.

2024-06-30 Thread Uros Bizjak
On Sun, Jun 30, 2024 at 9:09 PM Roger Sayle wrote: > > > Hi Uros, > > On Sat, Jun 29, 2024 at 6:21 PM Roger Sayle > > wrote: > > > A common idiom for implementing an integer division that rounds > > > upwards is to write (x + y - 1) / y. Conveniently on x86, the two > > > additions to form the n

[PATCH] build: Fix "make install" for MinGW

2024-06-30 Thread Lewis Hyatt
Hello- I noticed this while trying to test another patch on Windows (using the MSYS2 environment). Tested that it fixes the issue for x86_64-w64-mingw32 and doesn't affect anything for x86_64-pc-linux-gnu. It looks like the same fix for C was applied back in r11-702. OK? Thanks... -Lewis -- >8 -

[x86 SSE PATCH] Remove legacy ternlog patterns from sse.md

2024-06-30 Thread Roger Sayle
As promised here's the final ternlog clean-up, that deletes the now obsolete legacy patterns and mode iterators from sse.md. It also updates the surviving ternlog patterns to consistently use decimal immediate operands (instead of hexadecimal), and updates one last test case to match this change.

Re: [PATCH] RISC-V: use fclass insns to implement isfinite and isnormal builtins

2024-06-30 Thread Vineet Gupta
On 6/30/24 00:41, Xi Ruoyao wrote: > On Fri, 2024-06-28 at 17:53 -0700, Vineet Gupta wrote: >> +  UNSPEC_ISFINITE >> +  UNSPEC_ISNORMAL > You don't really need them. The RTL pattern of define_expand has no use > when you expand it via C code and DONE. > > i.e. you can just code > > (define_expa

Re: [PATCH] RISC-V: use fclass insns to implement isfinite and isnormal builtins

2024-06-30 Thread Vineet Gupta
On 6/30/24 06:59, Jeff Law wrote: >> Any ideas on how I can keep this and then adjust rest of patterns. > Yea. Drop the "SImode" references from the RTL template of the > expander. Then you'll need to verify the modes in the C fragment that > generates code. You'd want to test the mode of

[PATCH v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins

2024-06-30 Thread Vineet Gupta
Changes since v1: - Removed UNSPEC_{INFINITE,ISNORMAL} - Don't hardcode SI in patterns, try to keep X to avoid potential sign extension pitfalls. Implementation wise requires skipping :MODE specifier in match_operand which is flagged as missing mode warning. --- Currently isfinite

[PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3

2024-06-30 Thread pan2 . li
From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 3. Aka: Form 3: #define DEF_SAT_U_ADD_IMM_FMT_3(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_3 (T x) \

[PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2

2024-06-30 Thread pan2 . li
From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 2. Aka: Form 2: #define DEF_SAT_U_ADD_IMM_FMT_2(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_1 (T x) \ { \ retu

Re: [testsuite PATCH] Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c on RedHat.

2024-06-30 Thread Hongtao Liu
On Sun, Jun 30, 2024 at 7:29 PM Roger Sayle wrote: > > > This patch fixes the 4 FAILs of gcc.target/i386/pr192464-vrndscaleph.c > with --target_board='unix{-m32}' on RedHat 7.x. The issue is that this > AVX512 test includes the system math.h, and on older systems this provides > inline versions o

[PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

2024-06-30 Thread pan2 . li
From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 1. Aka: Form 1: #define DEF_SAT_U_ADD_IMM_FMT_1(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_1 (T x) \ {\

[PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4

2024-06-30 Thread pan2 . li
From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 4. Aka: Form 4: #define DEF_SAT_U_ADD_IMM_FMT_4(T)\ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_4 (T x)

Re: [x86 SSE PATCH] Remove legacy ternlog patterns from sse.md

2024-06-30 Thread Hongtao Liu
On Mon, Jul 1, 2024 at 6:14 AM Roger Sayle wrote: > > > As promised here's the final ternlog clean-up, that deletes the now > obsolete legacy patterns and mode iterators from sse.md. It also updates > the surviving ternlog patterns to consistently use decimal immediate > operands (instead of hexa

[PATCH] tree-optimization/115694 - ICE with complex store rewrite

2024-06-30 Thread Richard Biener
The following adds a missed check when forwprop attempts to rewrite a complex store. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/115694 * tree-ssa-forwprop.cc (pass_forwprop::execute): Check the store is complex before rewriting it.

Re: [x86 SSE PATCH] Remove legacy ternlog patterns from sse.md

2024-06-30 Thread Hongtao Liu
> > > > gcc/testsuite/ChangeLog > > * gcc.target/i386/pr100711-6.c: Update to check for decimal > > immediate operand in ternlog, not hexadecimal. > I got an ICE when bootstrapped with --enable-checking=yes,rtl,extra > The ICE can be walked around with 2 separate define_predicates,