>
> Then GCC emits the wrong trap instruction, wherever it comes from and
> whatever has caused it. The correct ones for integer division by zero
Thanks so much. It is not the bug of Linux kernel or GCC.
It is a bug of me ;) and qemu.
Qemu didn't pass the code of TEQ correctly; and I haven't ru
On Thu, 2024-06-20 at 14:34 +0100, Richard Sandiford wrote:
> *minus_plus_one had no constraints, which meant that it could be
> matched after RA with operands 0, 1 and 2 all being different.
> The associated split instead requires operand 0 to be tied to
> operand 1.
Thanks for spotting this.
On Thu, 2024-06-20 at 14:34 +0100, Richard Sandiford wrote:
>
> I tried compiling at least one target per CPU directory and comparing
> the assembly output for parts of the GCC testsuite. This is just a way
> of getting a flavour of how the pass performs; it obviously isn't a
> meaningful bench
Hi Segher,
on 2024/6/21 01:20, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jun 20, 2024 at 06:22:07PM +0800, Kewen.Lin wrote:
>> Following your review comments in [1], this patch is
>> separated from Xionghu's patch v4 [2] and mainly targetted
>> for 32-bit element size, it changes with the gener
Hi!
Gentle ping^2:
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653339.html
BR,
Kewen
on 2024/6/12 17:35, Kewen.Lin wrote:
> Hi,
>
> Gentle ping:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653339.html
>
> BR,
> Kewen
>
> on 2024/6/3 11:00, Kewen Lin wrote:
>> Joseph poin
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
Add 'Zvfbfmin' intrinsic in bases.
(class vfwcvtbf16_f): Ditto.
(class
Accroding to the BFloat16 spec, some vector iterators and new pattern
are added in md files.
All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
gcc/ChangeLog:
* config/riscv/riscv.md: Add new insn name for vector BFloat16.
* config/riscv/vector-iterators.m
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin and zvfwma need to be based
on this patch.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (bfloat16_type):
Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX.
When PAREN_EXPR tree code was added in r0-85884-gdedd42d511b6e4,
a simplified handling was added to complex lowering. Which means
we would get:
```
_9 = COMPLEX_EXPR <_15, _14>;
_11 = ((_9));
_19 = REALPART_EXPR <_11>;
_20 = IMAGPART_EXPR <_11>;
```
In many cases instead of just simply:
``
Hi,
Gentle ping.
BR,
Jeff(Jiufu) Guo
Jiufu Guo writes:
> Hi,
>
> For PR96866, when printing asm code for modifier "%a", an addressable
> operand is required. While the constraint "X" allow any kind of
> operand even which is hard to get the address directly. e.g. extern
> symbol whose addre
Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
and x < 0 ? 1 : 0 into (unsigned) x >> 31.
Move the optimization did in ix86_expand_int_vcond to match.pd
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, aarch64-linux-gnu.
Ok for trunk?
gcc/ChangeLog:
PR target/114189
Hi,
Gentle ping.
BR,
Jeff(Jiufu) Guo
Jiufu Guo writes:
> Hi,
>
> Gentle ping ...
>
> Jiufu Guo writes:
>
>> Hi,
>>
>> Gentle ping ...
>>
>> BR,
>> Jeff(Jiufu) Guo
>>
>> Jiufu Guo writes:
>>
>>> Hi,
>>>
>>> 'rlwinm' pattern is already well used for SImode. As this instruction
>>> can touch
On Thu, Jun 20, 2024 at 7:56 PM liuhongt wrote:
>
> Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
> and x < 0 ? 1 : 0 into (unsigned) x >> 31.
>
> Move the optimization did in ix86_expand_int_vcond to match.pd
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, aarch64-linux-gnu.
From: Pan Li
The zip benchmark of coremark-pro have one SAT_SUB like pattern but
truncated as below:
void test (uint16_t *x, unsigned b, unsigned n)
{
unsigned a = 0;
register uint16_t *p = x;
do {
a = *--p;
*p = (uint16_t)(a >= b ? a - b : 0); // Truncate the result of SAT_SUB
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 1/3] RISC-V: Add vector type of BFloat16 format
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin an
+ if (*group.shape == shapes::loadstore
+ || *group.shape == shapes::indexed_loadstore
+ || *group.shape == shapes::vundefined
+ || *group.shape == shapes::misc
+ || *group.shape == shapes::vset
+ || *group.shape == shapes::vget
+ || *group.shape == shapes::vcreate
+
On Wed, Oct 25, 2023 at 2:49 AM Richard Sandiford
wrote:
>
> This patch adds a combine pass that runs late in the pipeline.
> There are two instances: one between combine and split1, and one
> after postreload.
>
> The pass currently has a single objective: remove definitions by
> substituting int
> Am 21.06.2024 um 04:35 schrieb Andrew Pinski :
>
> When PAREN_EXPR tree code was added in r0-85884-gdedd42d511b6e4,
> a simplified handling was added to complex lowering. Which means
> we would get:
> ```
> _9 = COMPLEX_EXPR <_15, _14>;
> _11 = ((_9));
> _19 = REALPART_EXPR <_11>;
> _20
On Thu, Jun 20, 2024 at 3:37 PM Richard Sandiford
wrote:
>
> This patch adds a combine pass that runs late in the pipeline.
> There are two instances: one between combine and split1, and one
> after postreload.
>
> The pass currently has a single objective: remove definitions by
> substituting int
This applies some maintainance to passes.texi by removing references
to no longer existing passes. It also fixes a few minor things but
doesn't fill the gaps that meanwhile exist.
make pdf tested, pushed.
* doc/passes.texi: Remove references to no longer existing
passes.
---
gcc
LGTM
juzhe.zh...@rivai.ai 於 2024年6月21日 週五 12:25 寫道：
> LGTM
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Feng Wang
> *Date:* 2024-06-21 09:54
> *To:* gcc-patches
> *CC:* kito.cheng ; juzhe.zhong
> ; jinma.contrib ; Feng Wang
>
> *Subject:* [PATCH 1/3] RISC-V: Add vec
On Thu, Jun 20, 2024 at 11:08 PM Richard Biener wrote:
>
> This applies some maintainance to passes.texi by removing references
> to no longer existing passes. It also fixes a few minor things but
> doesn't fill the gaps that meanwhile exist.
Note this was recorded as https://gcc.gnu.org/bugzill
LGTM
On Fri, Jun 21, 2024 at 9:56 AM Feng Wang
wrote:
> Accroding to the BFloat16 spec, some vector iterators and new pattern
> are added in md files.
>
> All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add new in
On Fri, Jun 21, 2024 at 5:11 AM Andrew Pinski wrote:
>
> On Thu, Jun 20, 2024 at 7:56 PM liuhongt wrote:
> >
> > Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
> > and x < 0 ? 1 : 0 into (unsigned) x >> 31.
> >
> > Move the optimization did in ix86_expand_int_vcond to match.pd
> >
> > Boots
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