[v3: https://gcc.gnu.org/pipermail/gcc-patches/2024-May/653165.html
Changes from v3:
- Address typos, comment fixes and other minor nits pointed out by
Indu in patches 1-3 and 5.
- Rename option added in patch 4 from -fprune-btf to -gprune-btf.
- Reword commit message in patch 4 to better de
This commit makes some structural changes to the CTF/BTF debug info
emission. In particular:
a) CTF is new always fully generated and emitted before any
BTF-related procedures are run. This means that BTF-related
functions can change, even irreversibly, the shared in-memory
represen
This patch enables -gprune-btf by default in the BPF backend when
generating BTF information, and fixes BPF CO-RE generation when using
-gprune-btf.
When generating BPF CO-RE information, we must ensure that types used
in CO-RE relocations always have sufficient BTF information emited so
that the
This patch heavily refactors btfout.cc to take advantage of the
structural changes in the prior commits.
Now that inter-type references are internally stored as simply pointers,
all the painful, brittle, confusing infrastructure that was used in the
process of converting CTF type IDs to BTF type I
This patch adds a new option, -gprune-btf, to control BTF debug info
generation.
As the name implies, this option enables a kind of "pruning" of the BTF
information before it is emitted. When enabled, rather than emitting
all type information translated from DWARF, only information for types
dire
This patch replaces all inter-type references in the ctfc internal data
structures with pointers, rather than the references-by-ID which were
used previously.
A couple of small updates in the BPF backend are included to make it
compatible with the change.
This change is only to the in-memory repr
Previously it was not supported to generate both CTF and BTF debug info
in the same compiler run, as both formats made incompatible changes to
the same internal data structures.
With the structural change in the prior patches, in particular the
guarantee that CTF will always be fully emitted befor
Hello Richard:
On 11/06/24 9:41 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
Thanks a lot. Can I know what should we be doing with neg (fma)
correctness failures with load fusion.
>>>
>>> I think it would involve:
>>>
>>> - describing lxvp and stxvp as unspec patterns, as I menti
> I was looking at the code in more detail and just wanted to check.
> We have:
>
> int last_needs_comparison = -1;
>
> bool ok = noce_convert_multiple_sets_1
> (if_info, &need_no_cmov, &rewired_src, &targets, &temporaries,
> &unmodified_insns, &last_needs_comparison);
> if (!ok)
>
Just like r13-6662-g0e6f87835ccabf but this time for jit/jit-recording.cc.
Pushed as obvious after a quick build to make sure jit still builds.
gcc/jit/ChangeLog:
* jit-recording.cc: Define INCLUDE_SSTREAM before including
system.h and don't directly incldue sstream.
Signed-off-
On Tue, Jun 11, 2024 at 12:42 PM Andrew Pinski wrote:
>
> Just like r13-6662-g0e6f87835ccabf but this time for jit/jit-recording.cc.
>
> Pushed as obvious after a quick build to make sure jit still builds.
Backported also to GCC 14 and GCC 13.
Thanks,
Andrew
>
> gcc/jit/ChangeLog:
>
> *
On 6/5/24 00:45, Andi Kleen wrote:
Some programing styles use a lot of inline assembler, and it is common
to use very complex preprocessor macros to generate the assembler
strings for the asm statements. In C++ there would be a typesafe alternative
using templates and constexpr to generate the as
Robin Dapp writes:
>> I was looking at the code in more detail and just wanted to check.
>> We have:
>>
>> int last_needs_comparison = -1;
>>
>> bool ok = noce_convert_multiple_sets_1
>> (if_info, &need_no_cmov, &rewired_src, &targets, &temporaries,
>> &unmodified_insns, &last_needs
Ajit Agarwal writes:
> Hello Richard:
>
> On 11/06/24 9:41 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
> Thanks a lot. Can I know what should we be doing with neg (fma)
> correctness failures with load fusion.
I think it would involve:
- describing lxvp and st
Don't think it makes any difference, but:
Richard Biener writes:
> @@ -2151,7 +2151,16 @@ get_group_load_store_type (vec_info *vinfo,
> stmt_vec_info stmt_info,
>access excess elements.
>??? Enhancements include peeling multiple iterations
>
Richard Biener writes:
> This avoids falling back to elementwise accesses for strided SLP
> loads when the group size is not a multiple of the vector element
> size. Instead we can use a smaller vector or integer type for the load.
>
> For stores we can do the same though restrictions on stores w
The same sentence as in the x86_64-*-solaris2* section is in the
x86_64-*-* section directly above.
gcc:
PR target/69374
* doc/install.texi (Specific) : Remove
redundant introduction of x86-64.
---
gcc/doc/install.texi | 2 --
1 file changed, 2 deletions(-)
diff --git a/g
Hi!
What does "powerpc < 7" mean? Something before POWER ISA 2.06?
On Tue, Jun 11, 2024 at 04:22:54PM +0200, Rene Rebe wrote:
> Glibc uses .machine to determine assembler optimizations to use.
What does this mean?
.machine is an *output* for glibc; nothing in glibc reads source code.
Nothing
The following testcases have been failing on rv32 targets since
r15-953-gaf4bf422a69:
FAIL: gcc.target/riscv/rvv/autovec/binop/vwsll-1.c (internal compiler error: in
maybe_legitimize_operand, at optabs.cc:8056)
FAIL: gcc.target/riscv/rvv/autovec/binop/vwsll-1.c (test for excess errors)
Fix the b
On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog:
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode =
Hi!
> On Jun 12, 2024, at 00:15, Segher Boessenkool
> wrote:
>
> Hi!
>
> What does "powerpc < 7" mean? Something before POWER ISA 2.06?
PowerPC ISA level 7 or whatever you like to call it.
> On Tue, Jun 11, 2024 at 04:22:54PM +0200, Rene Rebe wrote:
>> Glibc uses .machine to determine assem
On Sat, May 25, 2024 at 11:42 AM Jeff Law wrote:
>
> This is a revamp of what started as a target specific patch.
>
> Basically xalan (corrected, I originally thought it was perlbench) has a
> bitset implementation with a bit of an oddity. Specifically setBit will
> clear the bit before it is set
The first new C2Y feature, _Generic where the controlling operand is a
type name rather than an expression (as defined in N3260), was voted
into C2Y today. (In particular, this form of _Generic allows
distinguishing qualified and unqualified versions of a type.) This
feature also includes allowin
Bitreverse rtl code was added with r14-1586-g6160572f8d243c. So let's
use it instead of an unspec. This is just a small cleanup but it does
have one small fix with respect to rtx costs which didn't handle vector modes
correctly for the UNSPEC and now it does.
This is part of the first step in addin
Tests involving float128_t were xfailed or otherwise worked around for
vxworks on aarch64. The same issue came up on rtems. This patch
adjusts them similarly.
Regstrapping on x86_64-linux-gnu. Also tested with gcc-13 on
aarch64-rtems6. Ok to install?
(I'd have expected the fast_float limita
Some c++23 tests fail on targets that don't satisfy dg-require-cmath,
because referenced math functions don't get declared in std. Add the
missing requirement.
Regstrapping on x86_64-linux-gnu. Already successfully tested with
gcc-13 on aarch64-rtems, where it avoids the errors that come up be
The D testsuite shows it was a mistake to assume that
dg-additional-sources are never to be used for compilation tests.
Even if an output file is specified for compilation, extra module
files can be named and used in the compilation without being flagged
as errors.
Introduce a 'linkonly' flag fo
We create a distinct type for each field in a packed record with a
gnu_size, but there is no distinct debug information for them. Use
the same unpacked type for debug information.
Regstrapped on x86_64-linux-gnu. Pre-approved by Eric. I'm checking it
in.
for gcc/ada/ChangeLog
* gc
Hi,
This patch replaces rtx_cost with insn_cost in forward propagation.
In the PR, one constant vector should be propagated and replace a
pseudo in a store insn if we know it's a duplicated constant vector.
It reduces the insn cost but not rtx cost. In this case, the cost is
determined by destina
On Tue, Jun 11, 2024 at 7:03 PM Alexandre Oliva wrote:
>
>
> The D testsuite shows it was a mistake to assume that
> dg-additional-sources are never to be used for compilation tests.
> Even if an output file is specified for compilation, extra module
> files can be named and used in the compilatio
Hi,
This patch creates an insn_and_split pattern which helps the duplicated
constant vector replace the source pseudo of store insn in fwprop pass.
Thus the store can be implemented by a single stxvd2x and it eliminates the
unnecessary byte swap insn on P8 LE. The test case shows the optimization
Missing CC to Jeff Law. Sorry.
在 2024/6/12 10:41, HAO CHEN GUI 写道:
> Hi,
> This patch replaces rtx_cost with insn_cost in forward propagation.
> In the PR, one constant vector should be propagated and replace a
> pseudo in a store insn if we know it's a duplicated constant vector.
> It reduces t
We were comparing a mode size with word_mode, but word_mode is an enum
value thus this does not really make any sense. (Un)luckily E_DImode
happens to be 8 so this seemed to work, but let's make it correct so it
won't blow up when we add LA32 support or add another machine mode...
gcc/ChangeLog:
Hi,
For CTEST, we don't have conditional AND so there's no optimization
opportunity to write a new ctest pattern. Emit ctest when ccmp did
comparison to const 0 to save bytes.
Bootstrapped & regtested under x86-64-pc-linux-gnu.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386.md (@ccmp)
Hi Segher,
Thanks a lot for your review!
Segher Boessenkool writes:
> Hi!
>
> On Tue, Jun 11, 2024 at 04:37:25PM +0800, Jiufu Guo wrote:
>> Sometimes, a complicated constant is built via 3(or more)
>> instructions. Generally speaking, it would not be as fast
>> as loading it from the constan
Hi Jason,
Sorry I must have misunderstood you. I thought the patch was already
approved earlier and I did commit. I can revert or do additional
changes.
On Tue, Jun 11, 2024 at 04:31:30PM -0400, Jason Merrill wrote:
> > + if (tok->type == CPP_OPEN_PAREN)
> > +{
> > + matching_parens p
As mentioned by Jeff in r15-831-g05daf617ea22e1d818295ed2d037456937e23530, we
don't handle
`(X | Y) & ~Y` -> `X & ~Y` on the gimple level when there are some different
signed
(but same precision) types dealing with matching `~Y` with the `Y` part. This
improves both gimple_bitwise_equal_p and gim
On Tue, 2024-06-11 at 20:53 -0700, Andi Kleen wrote:
> > > -Some assemblers allow semicolons as a line separator. However,
> > > -note that some assembler dialects use semicolons to start a comment.
> > > +Some assemblers allow semicolons as a line separator. However,
> > > +note that some assemble
On Jun 11, 2024, Andrew Pinski wrote:
> I think we should just fully revert the changes to
> dg-additional-sources and add an explicit `dg-do run` to pr95401.cc
I don't suppose an explicit "dg-do run" would make things work reliably,
after we've detected that hardware or runtime support for vect
Hi Haochen,
on 2024/6/12 10:47, HAO CHEN GUI wrote:
> Hi,
> This patch creates an insn_and_split pattern which helps the duplicated
> constant vector replace the source pseudo of store insn in fwprop pass.
> Thus the store can be implemented by a single stxvd2x and it eliminates the
> unnecessar
在 2024/6/12 上午11:06, Xi Ruoyao 写道:
We were comparing a mode size with word_mode, but word_mode is an enum
value thus this does not really make any sense. (Un)luckily E_DImode
happens to be 8 so this seemed to work, but let's make it correct so it
won't blow up when we add LA32 support or add a
Hi Mike,
on 2024/6/4 09:46, Michael Meissner wrote:
> This patch adds some simple tests for -mcpu=power11 support. In order to run
> these tests, you need an assembler that supports the appropriate option for
> supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
>
> I
On Tue, Jun 11, 2024 at 3:53 PM wrote:
>
> From: Pan Li
>
> We inserted the gcall of .SAT_ADD before the gsi_start_bb for avoiding
> the ssa def after use ICE issue. Unfortunately, there will be the
> potential ICE when the first stmt is label. We cannot insert the gcall
> before the label. T
On Tue, 11 Jun 2024, Jeff Law wrote:
>
>
> On 6/11/24 7:52 AM, Philipp Tomsich wrote:
> > On Tue, 11 Jun 2024 at 15:37, Jeff Law wrote:
> >>
> >>
> >>
> >> On 6/11/24 1:22 AM, Richard Biener wrote:
> >>
> Absolutely. But forwarding from a smaller store to a wider load is
> painful
>
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 12, 2024 2:41 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com
Subject: Re: [PATCH v1] Widening-Mul: Take gsi after_labels instead
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