Re: [PATCH] RISC-V: Remove useless modes

You could add [NFC] to the title for this kind of patch to declare its clean up or refactor patch without change any function or feature, that would be easier for reviewer, anyway LGTM as well On Wed, Dec 6, 2023 at 12:50 PM Li Xu wrote: > > From: xuli > > gcc/ChangeLog: > > * config/ris

Re: [PATCH 2/4] RISC-V: Add crypto vector builtin function.

+if (!((strcmp (instance.base_name, "vghsh") == 0 + || strcmp (instance.base_name, "vgmul") == 0 + || strcmp (instance.base_name, "vaesz") == 0 + || strcmp (instance.base_name, "vsha2ms") == 0 + || strcmp (instance.base_name, "vsha2ch") == 0 + || str

Re: [PATCH 3/4] RISC-V: Add crypto vector machine descriptions

Do vector crypto instruction demand RATIO ? If no, add them into: ;; It is valid for instruction that require sew/lmul ratio. (define_attr "ratio" "" (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\ vialu,vshift,vicmp,vimul,vidiv,vsalu,\ vext,viwalu,viwmul,vicalu,vn

Re: Re: [PATCH] RISC-V: Remove useless modes

Got it. Committed, thanks juzhe and kito. xu...@eswincomputing.com From: Kito Cheng Date: 2023-12-06 14:45 To: Li Xu CC: gcc-patches; palmer; juzhe.zhong Subject: Re: [PATCH] RISC-V: Remove useless modes You could add [NFC] to the title for this kind of patch to declare its clean up or refacto

Re: [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled

On Wed, Dec 6, 2023 at 2:31 AM Hongyu Wang wrote: > > Uros Bizjak 于2023年12月5日周二 18:46写道： > > > > > On Tue, Dec 5, 2023 at 3:29 AM Hongyu Wang wrote: > > > > > > Under APX NDD, previous TImode allocation will have issue that it was > > > originally allocated using continuous pair, like rax:rdi, r

[PATCH v3 0/5] Add support for approximate instructions and optimize divf/sqrtf/rsqrtf operations.

LoongArch V1.1 adds support for approximate instructions, which are utilized along with additional Newton-Raphson steps implement single precision floating-point division, square root and reciprocal square root operations for better throughput. The patches are modifications made based on the pat

[PATCH v3 1/5] LoongArch: Add support for LoongArch V1.1 approximate instructions.

This patch adds define_insn/builtins/intrinsics for these instructions, and add option -mfrecipe to control instruction generation. gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in (fecipe): Add. * config/loongarch/larchintrin.h (__frecipe_s): New intrinsic. (__

[PATCH v3 3/5] LoongArch: Redefine pattern for xvfrecip/vfrecip instructions.

Redefine pattern for [x]vfrecip instructions use rtx code instead of unspec, and enable [x]vfrecip instructions to be generated during auto-vectorization. gcc/ChangeLog: * config/loongarch/lasx.md (lasx_xvfrecip_): Renamed to .. (recip3): .. this. * config/loongarch/loong

[PATCH v3 5/5] LoongArch: Vectorized loop unrolling is disable for divf/sqrtf/rsqrtf when -mrecip is enabled.

Using -mrecip generates a sequence of instructions to replace divf, sqrtf and rsqrtf. The number of generated instructions is close to or exceeds the maximum issue instructions per cycle of the LoongArch, so vectorized loop unrolling is not performed on them. gcc/ChangeLog: * config/loo

[PATCH v3 2/5] LoongArch: Use standard pattern name for xvfrsqrt/vfrsqrt instructions.

Rename lasx_xvfrsqrt*/lsx_vfrsqrt* to rsqrt2 to align with standard pattern name. Define function use_rsqrt_p to decide when to use rsqrt optab. gcc/ChangeLog: * config/loongarch/lasx.md (lasx_xvfrsqrt_): Renamed to .. (rsqrt2): .. this. * config/loongarch/loongarch-builti

[PATCH v3 4/5] LoongArch: New options -mrecip and -mrecip= with ffast-math.

When both the -mrecip and -mfrecipe options are enabled, use approximate reciprocal instructions and approximate reciprocal square root instructions with additional Newton-Raphson steps to implement single precision floating-point division, square root and reciprocal square root operations, for a

Re: [PATCH] RISC-V: xtheadmemidx: Document inline asm issue with memory constraint

LGTM On Tue, Dec 5, 2023 at 11:16 PM Christoph Müllner wrote: > > The XTheadMemIdx support relies on the fact that memory operands that > can be expressed by XTheadMemIdx instructions, will only appear as > operands of such instructions. For internal instruction generation > this is guaranteed b

Re: [PATCH] lower-bitint: Fix arithmetics followed by extension by many bits [PR112809]

On Tue, 5 Dec 2023, Jakub Jelinek wrote: > Hi! > > A zero or sign extension from result of some upwards_2limb operation > is implemented in lower_mergeable_stmt as an extra loop which fills in > the extra bits with 0s or 1s. > If the delta of extended vs. unextended bit count is small, the code >

Re: [gcc15] nested functions in C

On Tue, Dec 5, 2023 at 10:16 PM Martin Uecker wrote: > > Am Dienstag, dem 05.12.2023 um 21:08 + schrieb Joseph Myers: > > On Mon, 4 Dec 2023, Martin Uecker wrote: > > > > > > The key feature of lambdas (which failed to make it into C23) for this > > > > purpose is that you can't convert them t

Re: [PATCH] i386: Mark Xeon Phi ISAs as deprecated

On Wed, Dec 6, 2023 at 3:33 AM Jiang, Haochen wrote: > > > -Original Message- > > From: Jiang, Haochen > > Sent: Friday, December 1, 2023 4:51 PM > > To: Richard Biener > > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > > ubiz...@gmail.com > > Subject: RE: [PATCH] i386: Mark Xeon Phi ISAs

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