libsanitizer/ChangeLog:
* configure.tgt: allow loongarch64-linux-*.
---
libsanitizer/configure.tgt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libsanitizer/configure.tgt b/libsanitizer/configure.tgt
index d24566a2343..5af524cb271 100644
--- a/libsanitizer/configure
Tested x86_64-linux. Pushed to trunk.
-- >8 --
We don't need any library concepts to define the constraints for rvalue
stream overloads, only compiler support. So change the test from using
__cpp_lib_concepts to __cpp_concepts >= 201907L.
libstdc++-v3/ChangeLog:
* include/std/istream (_
Tested x86_64-linux. Pushed to trunk.
-- >8 --
I noticed that our C++23 features were not being defined when using
Clang 16 with -std=c++2b, because it only defines __cplusplus=202101L
but uses 202302L since my r14-3252-g0c316669b092fb
change.
This changes to use 202100 instead of the final 20
Tested x86_64-linux. Pushed to trunk.
-- >8 --
This change moves the definitions of feature test macros (or strictly
speaking, the requests for to define them) so that only
standard headers define them. For example, will no
longer define macros related to std::shared_ptr, only and
will define
On Thu, Nov 16, 2023 at 04:01:13PM +0800, Yang Yujie wrote:
> libsanitizer/ChangeLog:
>
> * configure.tgt: allow loongarch64-linux-*.
${target} in there shouldn't be what user specified, but what config.sub
canonicalized it to.
And
./config.sub x86_64-linux; ./config.sub loongarch64-linux
x
Tested x86_64-linux. Pushed to trunk.
-- >8 --
Tests which check for feature test macros should use the no_pch option,
so that we're really testing for the definition being in the intended
header, and not just testing that it's present in (which
includes all the standard headers and so defines a
Tested x86_64-linux. Pushe to trunk.
-- >8 --
This implements that changes from P1132R8, including optimized paths for
std::shared_ptr and std::unique_ptr.
For std::shared_ptr we pre-allocate a new control block in the
std::out_ptr_t constructor so that the destructor is non-throwing. This
requi
Based on SPEC2017 performance evaluation results, it's better to make them equal
to the cost of unaligned store/load so as to avoid odd alignment peeling.
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_builtin_vectorization_cost): Adjust.
diff --git a/gcc/config/loonga
Based on SPEC2017 performance evaluation results, it's better to make them equal
to the cost of unaligned store/load so as to avoid odd alignment peeling.
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_builtin_vectorization_cost): Adjust.
diff --git a/gcc/config/loonga
On 16/11/2023 06:15, Philipp Tomsich wrote:
With the addition of CSSC (Common Short Sequence Compression)
instructions, a number of idioms match to single instructions (e.g.,
abs) that previously expanded to multi-instruction sequences.
This recognizes (some of) those idioms that are now misc
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, November 16, 2023 8:53 AM
> To: Philipp Tomsich ; gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] aarch64: costs: update for TARGET_CSSC
>
>
>
> On 16/11/2023 06:15, Philipp Tomsich wrote:
> > With th
On 15/11/2023 17:07, Tamar Christina wrote:
Hi All,
In anticipation of adding new generic turning values this removes the hardcoding
of the "generic" CPU and instead just specifies it as a normal CPU.
No change in behavior is expected.
Bootstrapped Regtested on aarch64-none-linux-gnu and no
On 15/11/2023 17:07, Tamar Christina wrote:
Hi All,
This patch adds a new generic scheduling model "generic-armv8-a" and makes it
the default for all Armv8 architectures.
-mcpu=generic and -mtune=generic is kept around for those that really want the
deprecated cost model.
Rather than refer
On 15/11/2023 17:08, Tamar Christina wrote:
Hi All,
This patch adds a new generic scheduling model "generic-armv9-a" and makes it
the default for all Armv9 architectures.
-mcpu=generic and -mtune=generic is kept around for those that really want the
deprecated cost model.
Bootstrapped Regte
Thanks for the quick turnaround on the review.
I'll send a v2 after the mcpu=ampere1b change has landed, as the
extra-costs change will have an interaction with that change (due to
the extra fields in the structure).
Philipp.
On Thu, 16 Nov 2023 at 15:12, Kyrylo Tkachov wrote:
>
>
>
> > -Or
On 15/11/2023 17:08, Tamar Christina wrote:
Hi All,
At the moment we emit a warning whenever you specify both -march and -mcpu
and the architecture of them differ. The idea originally was that the user may
not be aware of this change.
However this has a few problems:
1. Architecture revis
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, November 16, 2023 9:27 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: Re: [PATCH 6/6]AArch64: only emit mismatch error w
Hello Richard:
This patch does decision making in code sinking considers the following
decision.
High register pressure region is true if the following criteria
satisfied.
a) If liveout (early_bb) <= livein (early_bb).
b) if liveout (best_bb) <= liveout (early_bb).
c) !best_bb->count >= early_bb
On 16/11/2023 09:33, Tamar Christina wrote:
-Original Message-
From: Richard Earnshaw
Sent: Thursday, November 16, 2023 9:27 AM
To: Tamar Christina ; gcc-patches@gcc.gnu.org
Cc: nd ; Richard Earnshaw ;
Marcus Shawcroft ; Kyrylo Tkachov
; Richard Sandiford
Subject: Re: [PATCH 6/6]AArc
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, November 16, 2023 9:42 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: Re: [PATCH 6/6]AArch64: only emit mismatch error w
On Mon, Oct 30, 2023 at 1:10 PM Ajit Agarwal wrote:
>
> Hello Richard:
>
> Currently, code sinking will sink code at the use points with loop having same
> nesting depth. The following patch improves code sinking by placing the sunk
> code in immediate dominator with same loop nest depth.
>
> Revi
This is a temporary solution to
https://forum.dlang.org/thread/bug-1226...@https.d.puremagic.com%2Fissues%2F
libphobos/ChangeLog:
* libdruntime/gcc/sections/elf.d: Removes reference to __tls_get_addr
for
static libdruntime.
---
libphobos/libdruntime/gcc/sections/elf.d | 4 +++-
> ${target} in there shouldn't be what user specified, but what config.sub
> canonicalized it to.
> And
> ./config.sub x86_64-linux; ./config.sub loongarch64-linux
> x86_64-pc-linux-gnu
> loongarch64-unknown-linux-gnu
> so I really don't see why you want to change it.
OK, I see. Thanks.
Yujie
On 15/11/2023 17:08, Tamar Christina wrote:
Hi All,
At the moment we emit a warning whenever you specify both -march and -mcpu
and the architecture of them differ. The idea originally was that the user may
not be aware of this change.
However this has a few problems:
1. Architecture revis
Tamar Christina writes:
> Hi All,
>
> In testcases gcc.dg/tree-ssa/slsr-19.c and gcc.dg/tree-ssa/slsr-20.c we have
> a
> fairly simple computation. On the current generic costing we generate:
>
> f:
> add w0, w0, 2
> maddw1, w0, w1, w1
> lsl w0, w1, 1
>
On Wed, 15 Nov 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Wednesday, November 15, 2023 1:23 PM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> > Subject: RE: [PATCH 7/21]middle-end: update IV update code to
Update in V2:
1) Add some comments before the pattern.
2) Remove ? from view_convert.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
When I'm working on PR112443, I notice there's some misoptimizations:
after we fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend
fa
On Tue, Nov 7, 2023 at 10:53 AM Richard Biener wrote:
>
> On Mon, 6 Nov 2023, Tamar Christina wrote:
>
> > Hi All,
> >
> > This adds new test to check for all the early break functionality.
> > It includes a number of codegen and runtime tests checking the values at
> > different needles in the ar
Hi Florian!
Thanks for all your ongoing clean-up work!
On 2023-11-10T23:07:55+0100, Florian Weimer wrote:
> This change updates the gcc.c-torture/execute/ to avoid obsolete
> language constructs. In the changed tests, use of the features
> appears to be accidental, and updating allows the tests
On Thu, 2023-11-16 at 09:18 +0800, chenglulu wrote:
>
> 在 2023/11/15 下午7:38, Xi Ruoyao 写道:
> > Pushed r14-5486.
> >
> > /* snip */
> >
> > > > * gcc.target/loongarch/cas-acquire.c: New test.
> > This test fails with GCC 12/13 on LA664, and it indicates a
> > correctness
> > issue. May I
On Thu, Nov 16, 2023 at 11:58:42AM +0100, Thomas Schwinge wrote:
> > -main ()
> > +void
> > +main (int)
> > {
> >struct tiny x[3];
> >x[0].c = 10;
>
> The nvptx back end doesn't like that one:
>
> PASS: gcc.c-torture/execute/931004-13.c -O0 (test for excess errors)
> [-PASS:-]
> -Original Message-
> From: Richard Biener
> Sent: Thursday, November 16, 2023 10:40 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early
> breaks and arbitrary exits
>
> On Wed,
* Thomas Schwinge:
> Hi Florian!
>
> Thanks for all your ongoing clean-up work!
>
> On 2023-11-10T23:07:55+0100, Florian Weimer wrote:
>> This change updates the gcc.c-torture/execute/ to avoid obsolete
>> language constructs. In the changed tests, use of the features
>> appears to be accidental
On Wed, 15 Nov 2023, Tamar Christina wrote:
>
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Wednesday, November 15, 2023 1:42 PM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> > Subject: RE: [PATCH 8/21]middle-end: update vectorizabl
On Thu, 16 Nov 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, November 16, 2023 10:40 AM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> > Subject: RE: [PATCH 7/21]middle-end: update IV update code to
Pinging back to the top of reviewers' inboxes due to worry about Stage 1
End in a few days :)
See the last email for the latest version of the 2/2 patch. The 1/2
patch is A-Ok from Kyrill's earlier target-backend review.
On 10/11/2023 12:41, Stamatis Markianos-Wright wrote:
On 06/11/2023
Committed, thanks for the review and test :)
On Thu, Nov 16, 2023 at 7:19 AM Christoph Müllner
wrote:
>
> On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote:
> >
> > We set ra to fixed register now, but we still need to save/restore that at
> > prologue/epilogue if that has used.
>
> So before 71f
Committed with changelog update :P Thanks for the review.
On Thu, Nov 16, 2023 at 7:59 AM Christoph Müllner
wrote:
>
> On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote:
> >
> > The target attribute which proposed in [1], target attribute allow user
> > to specify a local setting per-function bas
* Jakub Jelinek:
> So, I guess void main (int) could be ok in some implementations, but I don't
> think that is the case of our. Florian, didn't you mean
> int
> main (void)
> or
> int
> main ()
> instead?
Exactly, it was a silly mistake.
> Note, I'm using
> int
> main ()
> {
> ...
> }
> in mos
> -Original Message-
> From: Richard Biener
> Sent: Thursday, November 16, 2023 11:28 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early
> breaks and arbitrary exits
>
> On Thu,
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-vcond-1.c: Adjust assembler
times.
* gcc.target/loongarch/vector/lasx/lasx-vcond-2.c: Ditto.
* gcc.target/loongarch/vector/lsx/lsx-vcond-1.c: Ditto.
* gcc.target/loongarch/vector/lsx/lsx-vcond-2.c: Di
The change should be OK, I've seen these test failures for a while. But
it would be better to provide some explanations in the commit message
(does these test fails since they were added first day or something has
changed after they were added?)
On Thu, 2023-11-16 at 20:08 +0800, Jiahao Xu wrote:
For the opaque NNP-data type prefer unsigned over signed integer types.
gcc/ChangeLog:
* config/s390/s390-builtin-types.def: Add/remove types.
* config/s390/s390-builtins.def
(s390_vclfnhs,s390_vclfnls,s390_vcrnfs,s390_vcfn,s390_vcnf):
Replace type V8HI with UV8HI.
The LoongArch has defined ctz and clz on the backend, but if we want GCC
do CTZ transformation optimization in forwprop2 pass, GCC need to know
the value of c[lt]z at zero, which may be beneficial for some test cases
(like spec2017 deepsjeng_r).
After implementing the macro, we test dynamic instru
On Thu, 16 Nov 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, November 16, 2023 11:28 AM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> > Subject: RE: [PATCH 7/21]middle-end: update IV update code to
Okay, thank you for your suggestion.
在 2023/11/16 下午8:11, Xi Ruoyao 写道:
The change should be OK, I've seen these test failures for a while. But
it would be better to provide some explanations in the commit message
(does these test fails since they were added first day or something has
changed a
These tests fail when they are first added,this patch adjusts the
scan-assembler-times
to fix them.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-vcond-1.c: Adjust assembler
times.
* gcc.target/loongarch/vector/lasx/lasx-vcond-2.c: Ditto.
* gcc.target/
On Thu, 2023-11-16 at 20:30 +0800, Li Wei wrote:
> The LoongArch has defined ctz and clz on the backend, but if we want GCC
> do CTZ transformation optimization in forwprop2 pass, GCC need to know
> the value of c[lt]z at zero, which may be beneficial for some test cases
> (like spec2017 deepsjeng_
Loongson 3A6000 processor will be shipped to general users in this month
and it features 4 cores with the new LA664 micro architecture. Here is
some changes from LA464:
1. The 32-bit division instruction now ignores the high 32 bits of the
input registers. This is enumerated via CPUCFG word 0
With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
of a 64-bit GPR even if it's not sign-extended.
gcc/ChangeLog:
* config/loongarch/loongarch.md (DIV): New mode iterator.
(3): Don't expand if TARGET_DIV32.
(di3_fake): Disable if TARGET_DIV32.
(
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other". Thus
we can omit the "load-load" barrier dbar 0x700.
This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports L
LoongArch v1.10 introduced the concept of ISA evolution. During ISA
evolution, many independent features can be added and enumerated via
CPUCFG.
Add a data file into genopts storing the CPUCFG word, bit, the name
of the command line option controlling if this feature should be used
for compilatio
We'll use HOST_WIDE_INT in LoongArch static properties in following
patches. Switch loongarch-def from C to C++ to make it possible.
To keep the same readability as C99 designated initializers, create a
std::array like data structure with position setter function, and add
field setter functions f
Allow using -march=la664 and -mtune=la664. -march=la664 implies -mdiv32
and -mld-seq-sa. -mtune=la664 is currently same as -mtune=la464 and it
may need an update later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Add la664 as
STR_CPU_LA664.
* config/loon
> > > > > >
> > > > > > Perhaps I'm missing something here?
> > > > >
> > > > > OK, so I refreshed my mind of what
> > > > > vect_update_ivs_after_vectorizer
> > > does.
> > > > >
> > > > > I still do not understand the (complexity of the) patch.
> > > > > Basically the function computes the new va
On Thu, 16 Nov 2023, Tamar Christina wrote:
> > > > > > >
> > > > > > > Perhaps I'm missing something here?
> > > > > >
> > > > > > OK, so I refreshed my mind of what
> > > > > > vect_update_ivs_after_vectorizer
> > > > does.
> > > > > >
> > > > > > I still do not understand the (complexity of the
No functional change intended.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-5530-g4547c271c455dc.
gcc/ChangeLog:
* diagnostic.cc (diagnostic_context::set_option_hooks): Add
"lang_mask" param.
* diagnostic.h (diagnostic_context::opti
From: Thomas Rodgers
Tested x86_64-linux, testing underway on powerpc-aix and sparc-solaris.
-- >8 --
This change splits the __wait_args data members to a new struct
__wait_args_base and then passes that type by const pointer to the low
level implementation functions.
libstdc++-v3/ChangeLog:
From: Thomas Rodgers
These two patches were written by Tom earlier this year, before he left
Red Hat. We should finish reviewing them for GCC 14 (and probably squash
them into one?)
Tom, you mentioned further work that changes the __platform_wait_t* to
uintptr_t, is that ready, or likely to be r
gcc/testsuite/
* gcc.c-torture/execute/931004-13.c (main): Fix mistakenly swapped
int/void types.
---
gcc/testsuite/gcc.c-torture/execute/931004-13.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.c-torture/execute/931004-13.c
b/gcc/tes
> -Original Message-
> From: Richard Biener
> Sent: Thursday, November 16, 2023 1:36 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early
> breaks and arbitrary exits
>
> On Thu, 1
On Thu, 16 Nov 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, November 16, 2023 1:36 PM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> > Subject: RE: [PATCH 7/21]middle-end: update IV update code to
On Wed, 2023-11-15 at 23:40 +, Joseph Myers wrote:
> On Wed, 15 Nov 2023, David Malcolm wrote:
>
> > As mentioned, I'm currently investigating capturing per-language
> > option
> > URLs (to address Iain's and Marc's comments about D and Ada); if I
> > get
> > that working, I may need to add a s
Changed in v2:
- added convenience targets to Makefile for regenerating the .opt.urls
files, and for running unit tests for the generation code
- parse gdc and gfortran documentation, and create LangUrlSuffix_{lang}
directives for language-specific URLs.
- add documentation to sourcebuild.texi
g
Changed in v2:
- split out from the code that generates options-urls.cc
- call the generated function, rather than use a generated array
- pass around lang_mask
gcc/ChangeLog:
* diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
param.
(diagnostic_context::make_opt
Changed in v2:
- split out from the code that uses this
- now handles lang-specific URLs, as well as generic URLs
- the generated options-urls.cc now contains a function with a
switch statement, rather than an array, to support
lang-specific URLs:
const char *
get_opt_url_suffix (int option_in
On 11/5/23 12:42, Jakub Jelinek wrote:
Hi!
check_field_decls for DECL_C_BIT_FIELD FIELD_DECLs with error_mark_node
TREE_TYPE continues early and doesn't call check_bitfield_decl which would
either set DECL_BIT_FIELD, or clear DECL_C_BIT_FIELD. So, the following
testcase ICEs after emitting tons
> -Original Message-
> From: Richard Biener
> Sent: Thursday, November 16, 2023 2:18 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early
> breaks and arbitrary exits
>
> On Thu, 1
Hi All,
This documents the behavior of the generic CPU options on AArch64.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* doc/invoke.texi (generic): Update defintion.
(generic-armv8-a, generic-armv9-a): Document.
So far we define arm_simd_types and scalar_types using type
definitions like intSI_type_node, etc...
This is causing problems with later patches which re-implement
load/store MVE intrinsics, leading to error messages such as:
error: passing argument 1 of 'vst1q_s32' from incompatible pointer typ
This patch adds the load and store shapes descriptions.
2023-11-16 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (load, store): New.
* config/arm/arm-mve-builtins-shapes.h (load, store): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 67 +++
This patch adds support for '_', 'al' and 'as' for void, load pointer
and store pointer argument/return value types in intrinsic signatures.
It also adds a mew memory_scalar_type() helper to function_instance,
which is used by 'al' and 'as'.
2023-11-16 Christophe Lyon
gcc/
* c
vst1q intrinsics return void, so we should not do 'return vst1q_f16 (base,
value);'
This was OK so far, but will trigger an error/warning with the new
implementation of these intrinsics.
This patch just removes the 'return' keyword.
2023-11-16 Christophe Lyon
gcc/testsuite/
This patch adds base support for load/store intrinsics to the
framework, starting with loads and stores for contiguous memory
elements, without extension nor truncation.
Compared to the aarch64/SVE implementation, there's no support for
gather/scatter loads/stores yet. This will be added later as
Implement vld1q, vst1q using the new MVE builtins framework.
2023-11-16 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q)
(vst1_impl, vst1q): New.
* config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New.
* config/arm/arm-mv
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 5/6] arm: [MVE intrinsics] fix vst1 tests
>
> vst1q intrinsics ret
On Thu, 16 Nov 2023 at 16:30, Kyrylo Tkachov wrote:
>
>
>
> > -Original Message-
> > From: Christophe Lyon
> > Sent: Thursday, November 16, 2023 3:26 PM
> > To: gcc-patches@gcc.gnu.org; Richard Sandiford
> > ; Richard Earnshaw
> > ; Kyrylo Tkachov
> > Cc: Christophe Lyon
> > Subject: [P
Tested on x86_64-pc-linux-gnu, pushed to trunk.
-- >8 --
Both of these PRs are fixed by r12-1403-gc4e50e500da7692a.
PR c++/98614
PR c++/104802
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/nontype-auto22.C: New test.
* g++.dg/cpp2a/concepts-partial-spec14.C: New test.
Bruno,
I have been able to tweak the environment and build gettext and libintl.
With the updated libintl and environment, GCC reliably does not use NLS.
The issue is that libintl utilizes pthreads. AIX does not provide no-op
pthread stubs in libc. pthreads is an explicit multilib on AIX.
It is
Also fix some indentitation inconsistencies.
PR target/112567
gcc/ChangeLog:
* config/i386/i386.md (*qi_ext_1_slp):
Fix generation of invalid RTX in split pattern.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/i386.md b/gcc/confi
Hi,
I have a related question. When I bootstrap gcc in maintainer mode on
x86_64-darwin, I get the following diff in the sources:
diff --git a/libstdc++-v3/config.h.in b/libstdc++-v3/config.h.in
index c0aa51af3f0..17da7bb9867 100644
--- a/libstdc++-v3/config.h.in
+++ b/libstdc++-v3/config.h.in
@
I configured gettext with --disable-pthreads and libintl.a still contains
references to pthread_mutex_lock and pthread_mutex_unlock, which causes NLS
configure to fail on AIX.
How can this be corrected?
Thanks, David
libintl.a[libgnu_la-mbrtowc.o]:
- U __lc_charmap
- U errno
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 1/6] arm: Fix arm_simd_types and MVE scalar_types
>
> So far we de
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 2/6] arm: [MVE intrinsics] Add support for void and
> load/store po
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 3/6] arm: [MVE intrinsics] Add support for contiguous loads
> and s
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 4/6] arm: [MVE intrinsics] add load and store shapes
>
> This patc
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, November 16, 2023 3:26 PM
> To: gcc-patches@gcc.gnu.org; Richard Sandiford
> ; Richard Earnshaw
> ; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 6/6] arm: [MVE intrinsics] rework vldq1 vst1q
>
> Implement vld1q,
Hello,
PR109849 shows that a loop that heavily pushes and pops from a stack
implemented by a C++ std::vec results in slow code, mainly because the
vector structure is not split by SRA and so we end up in many loads
and stores into it. This is because it is passed by reference
to (re)allocation me
Am 16.11.2023 um 17:00 schrieb David Edelsohn :Bruno,I have been able to tweak the environment and build gettext and libintl. With the updated libintl and environment, GCC reliably does not use NLS.The issue is that libintl utilizes pthreads. AIX does not provide no-op pthread stubs in libc. pt
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c43167d9a75..f0112f5d029 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -486,6 +486,7 @@ Fariborz Jahanian
Surya Kumari J
Tested x86_64-linux. Pushed to trunk.
-- >8 --
The formatter for std::thread::id should default to right-align, and the
formatter for std::stacktrace_entry should not just ignore the
fill-and-align and width from the format-spec!
libstdc++-v3/ChangeLog:
PR libstdc++/112564
* inc
This is PR ada/109881, a tree sharing issue for the internal return type
synthesized for a function returning a dynamically-sized type and taking an
Out or In/Out parameter passed by copy.
Tested on x86-64/Linux, applied on mainline, 13 and 12 branches.
2023-11-16 Eric Botcazou
PR
On Thu, Nov 16, 2023 at 11:58 AM Richard Biener
wrote:
>
>
> Am 16.11.2023 um 17:00 schrieb David Edelsohn :
>
>
> Bruno,
>
> I have been able to tweak the environment and build gettext and libintl.
> With the updated libintl and environment, GCC reliably does not use NLS.
>
> The issue is that
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
to trunk.
This patch works around problem compiling python3.11 by improving
REG+D address handling. The change results in smaller code and
reduced register pressure.
Dave
---
hppa: Revise REG+D address support to allow long di
Bruno,
The issue appears to be that intl/gnulib-lib/{mbrtowc.c,setlocale_null.c}
include pthread.h based on HAVE_PTHREAD_API, which is defined as 1 in
intl/config.h build directory despite requesting --disable-pthreads.
Thanks, David
On Thu, Nov 16, 2023 at 11:35 AM David Edelsohn wrote:
> I c
Hi,
This patch series reworks the load/store pair representation in the aarch64
backend and adds a new load/store pair fusion pass.
Patch 1/11 is just a rebased version of the patch from the previous version of
the series to add support to RTL-SSA for inserting new insns.
Patch 2/11 adds some RT
N.B. this is just a rebased (but otherwise unchanged) version of the
same patch already posted here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633348.html
this is the only unreviewed dependency from the previous series, so it
seemed easier just to re-post it (not least to appease the
This adds some helpers to access-utils.h for removing accesses from an
access_array. This is needed by the upcoming aarch64 load/store pair
fusion pass.
Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk?
gcc/ChangeLog:
* rtl-ssa/access-utils.h (filter_accesses): New.
The tests currently depending on memcpy lowering forming stps at -O0,
but we no longer want to form stps during memcpy lowering, but instead
in the load/store pair fusion pass.
This patch therefore tweaks affected tests to enable optimizations
(-O1), and adjusts the tests to avoid parts of the str
Later patches in the series allow ldp and stp to use SVE modes if
-msve-vector-bits=128 is provided. This patch therefore adjusts tests
that pass -msve-vector-bits=128 to allow ldp/stp to save/restore SVE
registers.
OK for trunk?
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pcs/sta
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