[PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Hi, this patch enhances the equality check for REG_EQUAL notes in the vsetvl pass. Currently, we assume that two such notes describe the same value when they have the same rtx representation. This is not true when either of the note's source operands is modified by an insn between the two notes.

Re: Fwd: [PATCH, expand] Call misaligned memory reference in expand_builtin_return [PR112417]

Sorry, forgot to cc gcc-patches. 在 2023/11/13 16:05, HAO CHEN GUI 写道: > Andrew, > Could you kindly inform us what's the functionality of __objc_forward? > Does it change the memory content pointed by args? Thanks a lot. > > Thanks > Gui Haochen > > > libobjc/sendmsg.c. > >void *args, *re

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Does this patch fixes exposed bugs in current tests? Or could you add test for it ? juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:06 To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai CC: rdapp.gcc Subject: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. Hi,

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

> Does this patch fixes exposed bugs in current tests? > Or could you add test for it ? Ah, yes forgot to mention. This fixes several tests when testing with -march=rv64gcv_zbb. Regards Robin

RE: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook.

Hi Roger, Looks good. Please proceed with your commit. Thank you, Claudiu -Original Message- From: Roger Sayle Sent: Friday, November 3, 2023 9:43 PM To: gcc-patches@gcc.gnu.org Cc: 'Claudiu Zissulescu' Subject: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook. This patch imple

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

I know the root cause is: (reg:DI 15 a5 [orig:175 _103 ] [175])(reg:DI 15 a5 [orig:174 _100 ] [174]) is considered as true on rtx_equal_p. I think return note1 == note2; will simplify your codes and fix this issue. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...

RE: [ARC PATCH] Improved DImode rotates and right shifts by one bit.

Looks good too. Please proceed with your commit. Thank you for your contribution, //Claudiu -Original Message- From: Roger Sayle Sent: Monday, November 6, 2023 7:30 PM To: gcc-patches@gcc.gnu.org Cc: 'Claudiu Zissulescu' Subject: [ARC PATCH] Improved DImode rotates and right shifts by

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Sorry. It should be return note1 && note2 && note1 == note2; juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. > Does this patch fixes

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Also, like kito previous remind me: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html I think you should add a dedicated test which with specifying -march=rv64gcv_zbb, then scan-assembler-check the correct vsetvl. So that we can allow people like me be able to avoid regressio

Re: [PATCH] Avoid generate vblendps with ymm16+

On Mon, Nov 13, 2023 at 02:27:35PM +0800, Hongtao Liu wrote: > > 1) if it isn't better to use separate alternative instead of > >x86_evex_reg_mentioned_p, like in the patch below > vblendps doesn't support gpr32 which is checked by x86_evex_reg_mentioned_p. > we need to use xjm for operands[1],

[committed] i386: Remove j constraint letter from list of unused letters

Hi! I've noticed the list of unused letters still list j, even when that constraint letter is now the first letter of jr, jR, jm, j<, j>, jo, jV, jp, ja, jb and jc constraints. Committed to trunk as obvious. 2023-11-13 Jakub Jelinek * config/i386/constraints.md: Remove j constraint l

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> FAIL: gcc.target/riscv/rvv/autovec/slp-mask-run-1.c -O3 -ftree-vectorize > (test for excess errors) > FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c -std=c99 -O3 > -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for > excess errors) > FAIL: gcc.target/riscv/

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

The FAIL is as follows: xgcc: fatal error: Cannot find suitable multilib set for '-march=rv32imafdcv_zicsr_zifencei_zfh_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b'/'-mabi=ilp32d'^M compilation terminated.^M compiler exited with status 1 FAIL: gcc.target/riscv/rvv/autovec/vmv-

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Also, I didn't enable multi-lib. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:52 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs. > FAIL: gcc.target/riscv/rvv/autovec/slp-mask-run-1.c -O3 -ftree-vectorize >

Re: [PATCH] Avoid generate vblendps with ymm16+

On Mon, Nov 13, 2023 at 4:45 PM Jakub Jelinek wrote: > > On Mon, Nov 13, 2023 at 02:27:35PM +0800, Hongtao Liu wrote: > > > 1) if it isn't better to use separate alternative instead of > > >x86_evex_reg_mentioned_p, like in the patch below > > vblendps doesn't support gpr32 which is checked by

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> xgcc: fatal error: Cannot find suitable multilib set for > '-march=rv32imafdcv_zicsr_zifencei_zfh_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b'/'-mabi=ilp32d'^M > compilation terminated.^M > compiler exited with status 1 > FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 09:25, juzhe.zh...@rivai.ai wrote: > Also, like kito previous remind me: > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html >   > > I think you should add a dedicated test which with specifying >

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

I just checked definition of REG_EQUAL and REG_EQUIV. As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on REG_EQUIV and skip REG_EQUAL. Could you check whether it does fix your issues ? juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 17:25 To: juzhe.zh...@rivai.ai

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> I'm going to configure with --with-arch=rv32gcv_zfh_zvfh --with-abi=ilp32d > to see if there is any difference. No change for me, how do you invoke the testsuite? I.e. Which target board? Regards Robin

[wwwdocs][committed] projects/gomp: Update for TR12, update impl. status

A new OpenMP 6.0 preview, Technical Report (TR) 12 has been released in time for Supercomputing 2023 (SC23), cf.https://www.openmp.org/specifications/ This commit links to the new spec (see bottom of change), it also updates the implementation status of some items for 'allocate', 'indirect' and

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:30, juzhe.zh...@rivai.ai wrote: > I just checked definition of REG_EQUAL and REG_EQUIV. > > As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on > REG_EQUIV and skip REG_EQUAL. > Could you check whether it does fix your issues ? Yes it would fix the issues. I

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Ok. Lehua is going to take care of this issue. He has reproduced it. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 17:31 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs. > I'm going to config

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout the entire function, and could validly be replaced in all its occurrences by @var{op}. (``Validly'' here refers to the data flow of the program; simple replacement may make some insns invalid.) For example, when a constant is

Re: Fwd: [PATCH, expand] Call misaligned memory reference in expand_builtin_return [PR112417]

On Mon, Nov 13, 2023 at 9:09 AM HAO CHEN GUI wrote: > > Sorry, forgot to cc gcc-patches. > > 在 2023/11/13 16:05, HAO CHEN GUI 写道: > > Andrew, > > Could you kindly inform us what's the functionality of __objc_forward? > > Does it change the memory content pointed by args? Thanks a lot. > > > > Th

Re: Principles of the C99 testsuite conversion

These changes are now in, for i686-linux-gnu, powerpc64le-linux-gnu, x86_64-linux-gnu. For aarch64-linux-gnu, there's one change that would benefit from maintainer review: [PATCH] aarch64: Call named function in gcc.target/aarch64/aapcs64/ice_1.c

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi Robin, Can you show me the compile command in gcc.log for the slp-mask-run-1.exe like bellow? I'd like to see the -march option on your side. Executing on host: /work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/build-gcc-newli

Re: [PATCH v5] C, ObjC: Add -Wunterminated-string-initialization

Hi, Gentle ping, just again a little before v14 stage 3. Do I need to do anything else with this patch? The CI seemed to say it's ok. Cheers, Alex On Sun, Oct 01, 2023 at 06:24:00PM +0200, Alejandro Colomar wrote: > Warn about the following: > > char s[3] = "foo"; > > Initializing a cha

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi Lehua, > Executing on host: > /work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/build-gcc-newlib-stage2/gcc/xgcc > > -B/work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-deb

Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach

Hi Juzhe, LGTM apart from: > + int64_t a = -1789089.23423; > + int64_t b = -8916156.45644; What's that? :) Doesn't really matter of course but please change to a proper integer. OK with that changed. Regards Robin

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

On 2023/11/13 17:59, Robin Dapp wrote: Hi Lehua, Executing on host: /work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_z

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> Looks like your configure is --with-march=rv32gcv_zvfh, can you change to > --with-march=rv32gcv_zvfh_zfh? >From config.log: $ ../configure --prefix=/home/rdapp/projects/builds/gcc --target=riscv32-unknown-linux-gnu --disable-nls --disable-multilib --disable-bootstrap --with-sysroot=/home

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

If there is a difference between them. I think we should fix riscv-common.cc. Since I think "zvfh_zfh" should not be different with "zfh_zvfh" juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 18:17 To: Lehua Ding; juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rd

Re: Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach

Thanks for noticing it. Will commit it with adjusting the testcase. Thanks. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 18:05 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw Subject: Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach H

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:38, juzhe.zh...@rivai.ai wrote: > For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout > the entire function, and could validly be replaced in all its > occurrences by @var{op}.  (``Validly'' here refers to the data flow of > the program; simple replacement may mak

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: If there is a difference between them. I think we should fix riscv-common.cc. Since I think "zvfh_zfh" should not be different with "zfh_zvfh" It's possible. Let me debug it and see if there's a problem. -- Best, Lehua (RiVAI) lehua.d...@riva

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: >> If there is a difference between them. I think we should fix riscv-common.cc. >> Since I think "zvfh_zfh" should not be different with "zfh_zvfh" > > It's possible. Let me debug it and see if there's a problem. I don't think it is different.

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

On 2023/11/13 18:33, Robin Dapp wrote: On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: If there is a difference between them. I think we should fix riscv-common.cc. Since I think "zvfh_zfh" should not be different with "zfh_zvfh" It's possible. Let me debug it and see if there's a problem.

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

--- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zbb --param riscv-autovec-preference=fixed-vlmax" } */ Could you add compile test (with asse

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

Hi! On 2023-11-09T17:00:11+0100, Tobias Burnus wrote: > On 09.11.23 13:24, Thomas Schwinge wrote: >> Also, assuming that the order of appearance of 'IND_FUNC_MAP' does matter >> as it does for 'FUNC_MAP', ... >> https://github.com/MentorEmbedded/nvptx-tools/pull/29 ... > > It should matter. Thus

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi Robin, On 2023/11/13 18:33, Robin Dapp wrote: On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: If there is a difference between them. I think we should fix riscv-common.cc. Since I think "zvfh_zfh" should not be different with "zfh_zvfh" It's possible. Let me debug it and see if there's a

[PATCH] gm2: Add missing declaration of m2pim_M2RTS_Terminate to test

Needed for C99 testsuite compatibility. gcc/testsuite/ * gm2/link/externalscaffold/pass/scaffold.c (m2pim_M2RTS_Terminate): Declare. --- gcc/testsuite/gm2/link/externalscaffold/pass/scaffold.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gm2/link/externalsca

Re: [PATCH v2 1/7] aarch64: Use br instead of ret for eh_return

The 11/13/2023 01:27, Hans-Peter Nilsson wrote: > > From: Szabolcs Nagy > > Date: Fri, 3 Nov 2023 15:36:08 + > > I don't see others commenting on this patch, and you're not > mentioning this aspect, so I wonder: > > > * config/aarch64/aarch64.h (EH_RETURN_TAKEN_RTX): Define. > > (EH_

Re: [RFC] Intel AVX10.1 Compiler Design and Support

On Mon, Nov 13, 2023 at 7:58 AM Hongtao Liu wrote: > > On Fri, Nov 10, 2023 at 6:15 PM Richard Biener > wrote: > > > > On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang > > wrote: > > > > > > Hi all, > > > > > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512 > > > support

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi Kito, On 2023/11/13 19:13, Lehua Ding wrote: Hi Robin, On 2023/11/13 18:33, Robin Dapp wrote: On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: If there is a difference between them. I think we should fix riscv-common.cc. Since I think "zvfh_zfh" should not be different with "zfh_zvfh" I

[PATCH v2 1/2] libatomic: atomic_16.S: Improve ENTRY, END and ALIAS macro interface

The introduction of further architectural-feature dependent ifuncs for AArch64 makes hard-coding ifunc `_i' suffixes to functions cumbersome to work with. It is awkward to remember which ifunc maps onto which arch feature and makes the code harder to maintain when new ifuncs are added and their su

[PATCH v2 0/2] Libatomic: Add LSE128 atomics support for AArch64

v2 updates: Move the previously unguarded definition of IFUNC_NCONDN(N) in `host-config.h' to within the scope of `#ifdef HWCAP_USCAP'. This is done so that its definition is not only contingent on the value of N but also on the definition of HWCAP_USCAP as it was found that building on systems wh

[PATCH v2 2/2] libatomic: Enable LSE128 128-bit atomics for armv9.4-a

The armv9.4-a architectural revision adds three new atomic operations associated with the LSE128 feature: * LDCLRP - Atomic AND NOT (bitclear) of a location with 128-bit value held in a pair of registers, with original data loaded into the same 2 registers. * LDSETP - Atomic OR (bitset) of

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

Hi Thomas, On 13.11.23 11:59, Thomas Schwinge wrote: - 'gcc/cp/pt.cc:tsubst_omp_clauses', - 'gcc/gimplify.cc:gimplify_scan_omp_clauses', 'gcc/gimplify.cc:gimplify_adjust_omp_clauses' - 'gcc/omp-low.cc:scan_sharing_clauses' (twice) - 'gcc/tree-nested.cc:convert_nonlocal_omp_

[PATCH] libatomic: Add rcpc3 128-bit atomic operations for AArch64

Continuing on from previously-proposed Libatomic enablement work [1], the introduction of the optional RCPC3 architectural extension for Armv8.2-A upwards provides additional support for the release consistency model, introducing both the Load-Acquire RCpc Pair Ordered, and Store-Release Pair Order

[PATCH] c++: Implement C++26 P2864R2 - Remove Deprecated Arithmetic Conversion on Enumerations From C++26

Hi! The following patch implements C++26 P2864R2 by emitting pedwarn enabled by the same options as the C++20 and later warnings (i.e. -Wenum-compare, -Wdeprecated-enum-enum-conversion and -Wdeprecated-enum-float-conversion which are all enabled by default). I think we still want to allow users s

Re: [V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

On Mon, Nov 13, 2023 at 8:50 AM Hongtao Liu wrote: > > On Fri, Nov 10, 2023 at 5:12 PM Richard Biener > wrote: > > > > On Wed, Nov 8, 2023 at 9:22 AM Hongtao Liu wrote: > > > > > > On Wed, Nov 8, 2023 at 3:53 PM Richard Biener > > > wrote: > > > > > > > > On Wed, Nov 8, 2023 at 2:18 AM Hongtao

[PATCH] c++/modules: Support lambdas in static template member initialisers [PR107398]

Bootstrapped and regtested on x86_64-pc-linux-gnu. I don't have write access. -- >8 -- The testcase noted in the PR fails because the context of the lambda is not in namespace scope, but rather in class scope. This patch removes the assertion that the context must be a namespace and ensures that

C++ patch ping^3

Hi! I'd like to ping a couple of C++ patches. - c++, v2: Implement C++26 P2169R4 - Placeholder variables with no name [PR110349] https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630802.html - c++, v2: Implement C++26 P2741R3 - user-generated static_assert messages [PR110348] https:

[Committed] RISC-V: Adapt VLS init tests

Realize that init tests are wrong by my previous mistakes. Fix them and committed. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Fix init test. * gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto.

Re: [RFC PATCH] Detecting lifetime-dse issues via Valgrind

On Tue, Oct 24, 2023 at 4:12 PM wrote: > > From: Daniil Frolov > > PR 66487 is asking to provide sanitizer-like detection for C++ object lifetime > violations that are worked around with -fno-lifetime-dse in Firefox, LLVM, > OpenJade. > > The discussion in the PR was centered around extending MSa

Re: [PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

On Mon, 13 Nov 2023, juzhe.zh...@rivai.ai wrote: > Hi. Ping this patch which is last optab pattern for RVV support. > > The mask_len_strided_load/mask_len_strided_store document has been approved: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635103.html > > Bootstrap on X86 and

[PATCH] tree-optimization/111792 - new testcase

This was fixed as part of the PR111000 fix. Tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/111792 PR tree-optimization/111000 * gcc.dg/torture/pr111792.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr111792.c | 39 + 1 file ch

Re: [PATCH v3 3/4] ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_sets

Hi Jeff, Indeed, that sounds like a good idea. I will make this separate and send it after the required testing. I'll see what can be done about a testcase. Best, Manolis On Sat, Nov 11, 2023 at 1:20 AM Jeff Law wrote: > > > > On 8/30/23 04:13, Manolis Tsamis wrote: > > The existing implementat

Re: [PATCH v3 4/4] ifcvt: Remove obsolete code for subreg handling in noce_convert_multiple_sets

Yes, my finding back then was that this is leftover code from the initial implementation, nothing to do with the rest of the changes. I will first re-evaluate this and test it separately from the other series. If all is good I'll let you know so we can proceed. Manolis On Sat, Nov 11, 2023 at 12:

Re: [PATCH v3 2/4] ifcvt: Allow more operations in multiple set if conversion

On Thu, Oct 19, 2023 at 10:46 PM Richard Sandiford wrote: > > Manolis Tsamis writes: > > Currently the operations allowed for if conversion of a basic block with > > multiple sets are few, namely REG, SUBREG and CONST_INT (as controlled by > > bb_ok_for_noce_convert_multiple_sets). > > > > This c

[PATCH 0/6] Turn some C warnings into errors by default

This patch series converts the following warnings into errors by default: -Wint-conversion -Wimplicit-function-declaration -Wimplicit-int -Wreturn-mismatch -Wincompatible-pointer-types As explained in the first commit, I decided not to use permerror_opt because it does not exhibit the e

[PATCH 1/6] c-family: Introduce pedpermerror

It turns out that permerror_opt is not directly usable for -fpermissive in the C front end. The front end uses pedwarn extensively, and pedwarns are not overridable by -Wno-* options, yet permerrors are. Add new pedpermerror helpers that turn into pedwarns if -pedantic-errors is active. Due to t

[PATCH 2/6] c: Turn int-conversion warnings into permerrors

gcc/ * doc/invoke.texi (Warning Options): Document changes. gcc/c/ * c-typeck.cc (build_conditional_expr): Use pedpermerror for pointer/integer type mismatches, based on -Wint-conversion. (pedwarn_pedpermerror_init, permerror_init): New function. (pedwarn_

[PATCH 3/6] c: Turn -Wimplicit-function-declaration into a pedpermerror

In the future, it may make sense to avoid cascading errors from the implicit declaration, especially its assumed int return type. This change here only changes the kind of the diagnostic, not its wording or consequences. gcc/c/ * doc/invoke.texi (Warning Options): Document changes. gcc/c

[PATCH 4/6] c: Turn -Wimplicit-int into a pedpermerror

There is a missed opportunity here to issue spelling diagnostics in prototype declarations (e.g., for “extern int foo (int32t);”). gcc/ * doc/invoke.texi (Warning Options): Document changes. gcc/c/ * c-decl.cc (warn_defaults_to): Call emit_diagnostic_valist instead of re

[PATCH 5/6] c: Turn -Wreturn-mismatch into a pedpermerror

gcc/ * doc/invoke.texi (Warning Options): Document changes. gcc/c/ * c-typeck.cc (c_finish_return): Issue a permerror for mismatching pointers to builtins. For mismatching other pointers, issue a pedpermerror. gcc/testsuite/ * gcc.dg/20030906-1.c: Compi

[PATCH 6/6] c: Turn -Wincompatible-pointer-types into a pedpermerror

gcc/ * doc/invoke.texi (Warning Options): Document changes. gcc/c/ * c-typeck.cc (build_conditional_expr): Use pedpermerror- equivalent for pointer type mismatches in conditional expression. (convert_for_assignment): Use pedpermerror and pedpermerr

Re: [PATCH 2/3] Add generated .opt.urls files

David Malcolm writes: > gcc/ada/ChangeLog: > * gcc-interface/lang.opt.urls: New file, autogenerated by > regenerate-opt-urls.py. > diff --git a/gcc/ada/gcc-interface/lang.opt.urls > b/gcc/ada/gcc-interface/lang.opt.urls > new file mode 100644 > index ..e24210bcb12a >

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 11:36, juzhe.zh...@rivai.ai wrote: > --- /dev/null > +++ > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c > @@ -0,0 +1,19 @@ > +/* { dg-do run { target { riscv_v } } } */ > +/* { dg-additional-options "-march=rv64gcv_zbb --param > riscv-autovec-prefer

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

I just checked your test. I won't be brittle in the future. Since it should be 4 vsetvls with e16m1 for SLP AVL/VL toggling. And also it is no scheduling. The middle-end MIN_EXPR SLP always produce 4 AVL/VL toggling as long as we don't schedule the instructions. So it won't be problem. So, LGTM

[PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

v1 -> v2: * Bring the MEM into the operand for cv.elw. The new predicate is move_operand. * Add comment to riscv.md detailing why corev.md must appear before the generic riscv instructions. This patch series presents the comprehensive implementation of the ELW and BI extension for CORE

[PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/

[PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors

gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 --- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/risc

[PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/

[PATCH] tree-optimization/112495 - alias versioning and address spaces

We are not correctly handling differing address spaces in dependence analysis runtime alias check generation so refuse to do that. Bootstrapped and tested on x86_64-unknown-linux-gnu. I'm double-checking hundreds of ACATS FAILs (segfaults), will push if those are latent. Richard. PR tre

[PATCH] middle-end/112487 - inline and parameter mismatch

When passing an aggregate to a implicitly declared function that's later declared as receiving a register type we can run into a sanity assert that cannot hold for such gross mismatches. Instead of asserting avoid emitting a debug temp that's invalid. Bootstrapped and tested on x86_64-unknown-lin

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 01:15, juzhe.zh...@rivai.ai wrote: I know the root cause is: (reg:DI 15 a5 [orig:175 _103 ] [175]) (reg:DI 15 a5 [orig:174 _100 ] [174]) is considered as true on rtx_equal_p. I think return note1 == note2; will simplify your codes and fix this issue. NOTEs are not shared (look

Re: [PATCH 2/3] Add generated .opt.urls files

On Mon, 2023-11-13 at 14:11 +0100, Marc Poulhiès wrote: > > David Malcolm writes: > > > gcc/ada/ChangeLog: > > * gcc-interface/lang.opt.urls: New file, autogenerated by > > regenerate-opt-urls.py. > > > > diff --git a/gcc/ada/gcc-interface/lang.opt.urls b/gcc/ada/gcc- > > inter

Re: [PATCH 2/3] Add generated .opt.urls files

On Sun, 2023-11-12 at 11:56 +0100, Iain Buclaw wrote: > Excerpts from David Malcolm's message of November 10, 2023 10:42 pm: > > gcc/d/ChangeLog: > > * lang.opt.urls: New file, autogenerated by > > regenerate-opt-urls.py. > > --- > >  gcc/d/lang.opt.urls  |  

[committed 00/22] arm: testsuite: clean up some architecture-specific tests

A lot of the arm-specific compiler tests require a specific CPU or architecture to be specified. This causes problems if the test suite run is set up to test a specific architecture or CPU that differs from the test's requirements. An exmple I use commonly is set target_list { "arm-qemu{

[committed 01/22] arm: testsuite: correctly detect armv6t2 hardware for acle execution tests

Some of the ACLE tests for Arm are executable, but we were only testing that the compiler could generate code for them, not that the hardware was capable of executing them. Fix this by adding an execution test for suitable hardware. gcc/testsuite: * lib/target-supports.exp (check_effect

[committed 02/22] arm: testsuite: correctly detect hard_float

Add an arm-specific test to check_effective_target_hard_float for Arm to handle cases where we only have single-precision FP in hardware. gcc/testsuite: * lib/target-supports.exp (check_effective_target_hard_float): Add arm-specific test. --- gcc/testsuite/lib/target-supports.ex

[committed 07/22] arm: testsuite: tidy up pre-run check for g2.c

gcc.target/arm/g2.c is an xscale-only test, but the test is quite old and we have improved the infrastructure for setting up such tests now. So make use of that to reduce the number of cases where this test fails to run. gcc/testsuite: * lib/target-supports.exp (check_effective_target_ar

[committed 10/22] arm: testsuite: improve compatibility of arm/pr78353-*.c

Again, use the infrastructure available to improve the compatibility of these tests. gcc/testsuite: * gcc.target/arm/pr78353-1.c: Use dg-add-options to manage target flags. * gcc.target/arm/pr78353-2.c: Likewise. --- gcc/testsuite/gcc.target/arm/pr78353-1.c | 3 ++- gcc/

[committed 04/22] arm: testsuite: avoid problems with -mfpu=auto in pacbti-m-predef-11.c

This test overrides the architecture, but fails to describe which floating-point features are needed. This causes problems if the ABI requires FP for parameter passing and -mfpu=auto is selected, so ensure that one is specified. gcc/testsuite: * gcc.target/arm/acle/pacbti-m-predef-11.c:

[committed 03/22] arm: testsuite: avoid hard-float ABI incompatibility with -march

A number of tests in the gcc testsuite, especially for arm-specific targets, add various flags to control the architecture. These run into problems when the compiler is configured with -mfpu=auto if the new architecture lacks an architectural feature that implies we have floating-point instructio

[committed 06/22] arm: testsuite: avoid problems with -mfpu=auto in attr_thumb-static2.c

This test overrides the architecture, but fails to describe which floating-point features are needed. This causes problems if the ABI requires FP for parameter passing and -mfpu=auto is selected, so ensure that one is specified. gcc/testsuite: * gcc.target/arm/attr_thumb-static2.c: Add

[committed 11/22] arm: testsuite: improve compatibility of pr88648-asm-syntax-unified.c

Fix another test that was trying to set the architecture directly rather than using the infrastructure as intended. gcc/testsuite: * gcc.target/arm/pr88648-asm-syntax-unified.c: It isn't necessary to try to override the architecture flags specified by arm_arch_v7a. --- gcc/tests

[committed 17/22] arm: testsuite: improve compatibility of gcc.target/arm/optional_thumb-*.c

These tests deliberately pass invalid option combinations to check that the compiler is generating the correct diagnostic. Nevertheless, we can improve their compatibility with other testsuite options. For optional_thumb-1.c we use a soft-float ABI, while for optional_thumb2.c we use arm_arch_v7

[committed 05/22] arm: testsuite: avoid problems with -mfpu=auto in attr-crypto.c

This test overrides the architecture, but fails to describe which floating-point features are needed. This causes problems if the ABI requires FP for parameter passing and -mfpu=auto is selected, so ensure that one is specified. gcc/testsuite: * gcc.target/arm/attr-crypto.c: Add +simd t

[committed 08/22] arm: testsuite: improve compatibility of arm/lto/pr96939_1.c

This test overrides the architecture, but fails to specify the floating point architecture. This causes problems if -mfpu=auto is used. gcc/testsuite: * gcc.target/arm/lto/pr96939_1.c: Add +simd to the architecture specification. --- gcc/testsuite/gcc.target/arm/lto/pr96939_1.c

[committed 12/22] arm: testsuite: improve compatibility of pragma_arch_attribute*.c

These tests use pragmas adn attributes to change the architecture. Sometimes they simply add a feature using "+crc", but other times they try to completely reset the architecture using "arch=armv8-a+crc". The latter fails on a hard-float ABI with -mfpu=auto because it also clears the FP capability

[committed 14/22] arm: testsuite: modernize framework usage for arm/scd42-2.c

Make this test more useful by using dg-require-effective-target/ dg-add-options. gcc/testsuite: * gcc.target/arm/scd42-2.c: Use modern dg- flags. --- gcc/testsuite/gcc.target/arm/scd42-2.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/gcc/testsuite/gcc.tar

[committed 13/22] arm: testsuite: improve compatibility of pragma_arch_switch_2.c

This test was explicitly setting the architecture on the command-line and in the body of the test. In both cases this causes problems with the auto FPU setting. Fix by using the testsuite infrastructure correctly and by adding +fp to the pragma. gcc/testsuite: * gcc.target/arm/pragma_a

[committed 09/22] arm: testsuite: tidy up pr65647-2.c pre-checks.

Another case where we can make better use of the infrastructure to improve the compatibility of this test. gcc/testsuite: * gcc.target/arm/pr65647-2.c: Use dg-add-options to manage target flags. --- gcc/testsuite/gcc.target/arm/pr65647-2.c | 3 ++- 1 file changed, 2 insertions(+

[committed 19/22] arm: testsuite: improve compatibility of gcc.target/arm/pr59575.c

Use dg-require-effective-target/dg-add-options to improve compatibility of this test with various compiler configurations. gcc/testsuite: * gcc.target/arm/pr59575.c: Use dg-require-effective-target and dg-add-options. --- gcc/testsuite/gcc.target/arm/pr59575.c | 4 +++- 1 file c

[committed 20/22] testsuite: arm: tighten up mode-specific ISA tests

Some of the standard Arm architecture tests require the test to use a specific instruction set (arm or thumb). But although the framework was checking that the flag was accepted, it wasn't checking that the flag wasn't somehow being override (eg by run-specific options). We can improve these tes

[committed 16/22] arm: testsuite: improve compatibility of gcc.target/arm/macro_defs*.c

Convert these tests to use dg-add-options for increased compatibilty. Since they also result in an empty translation unit, override the default testsuite options. gcc/testsuite: * gcc.target/arm/macro_defs0.c: Use dg-effective-target and dg-add-options. * gcc.target/arm/m

[committed 15/22] arm: testsuite: improve compatibility of ftest-armv7m-thumb.c

This test is specific to armv7m cores which do not support hardware floating-point. We can improve its compatibility by having the default options for this core specify -mfloat-abi=soft. gcc/testsuite: * lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok): Use soft

[committed 18/22] arm: testsuite: improve compatibility of gcc.target/arm/pr19599.c

Add +fp to the architecture specification, so that -mfpu=auto works with the hard-float ABI. gcc/testsuite: * gcc.target/arm/pr19599.c: Add +fp to the architecture. --- gcc/testsuite/gcc.target/arm/pr19599.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsui

  1   2   >