On Thu, 9 Nov 2023, Jakub Jelinek wrote:
> Hi!
>
> The following patch adds 6 new type-generic builtins,
> __builtin_clzg
> __builtin_ctzg
> __builtin_clrsbg
> __builtin_ffsg
> __builtin_parityg
> __builtin_popcountg
> The g at the end stands for generic because the unsuffixed variant
> of the bu
Hi Juzhe,
yes, that's reasonable. OK.
Regards
Robin
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint
2. llround
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec w
No test?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-10 16:14
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like to
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, November 10, 2023 4:12 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Robustify vec_init
This patch only add new modes to iterator, I failed to find a way to test it.
Maybe I can add underlying lrint autovec implment together, which is more
straightforward
to add test cases here.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, November 10, 2023 4:16 PM
To: Li, Pan2 ; gcc-patches
Cc:
Hi Dimitar,
Thanks for the tests.
This patch set breaks the build for at least three embedded targets. See
below.
For avr the GCC build fails with:
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira-lives.cc:149:39: error: call of overloaded
‘set_subreg_conflict_hard_regs(ira_allocno*&, int&)’ is am
Pushed to r14-5314.
在 2023/11/3 下午5:01, Chenghui Pan 写道:
gcc/ChangeLog:
* config/loongarch/lsx.md: Fix instruction name typo in
lsx_vreplgr2vr_ template.
---
gcc/config/loongarch/lsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/l
> > I had wanted to write about some of my frustrations with trying to
> > write a test for virtual specifiers and errors/warnings for
> > shadowing/overloading virtual functions, but I am a bit too tired at
> > the moment and I don't want to delay getting this up for another night.
> > In short, t
The divide by zero error above is interesting. I'm not sure why
ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in the
following rtx:
(debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168 [
encoding ])) -1
(nil))
I just cross compiled an arm-none-eabi compile
gcc/ChangeLog:
* gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
and LABEL_REF type.
(call_insn_operand): Support for CM_Large.
(pcrel_symbol_operand): New.
* gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
"__riscv_cmodel_large".
* gcc/config/riscv/riscv-op
On Fri, Nov 10, 2023 at 8:52 AM HAO CHEN GUI wrote:
>
> Hi Richard,
> Thanks so much for your comments.
>
> 在 2023/11/9 19:41, Richard Biener 写道:
> > I'm not sure if the testcase is valid though?
> >
> > @defbuiltin{{void} __builtin_return (void *@var{result})}
> > This built-in function returns
Hi,
more fallout from the COND_OP change was shown in PR112464.
It appears as if we "look through" a statement pattern in
vect_finish_replace_stmt but not before when we replace the newly
created vector statement's lhs. Then the lhs is the statement pattern's
lhs while in vect_finish_replace_stm
On Fri, Nov 10, 2023 at 08:09:26AM +, Richard Biener wrote:
> > The following patch adds 6 new type-generic builtins,
> > __builtin_clzg
> > __builtin_ctzg
> > __builtin_clrsbg
> > __builtin_ffsg
> > __builtin_parityg
> > __builtin_popcountg
> > The g at the end stands for generic because the u
Sorry. It missed a semicolon in the previos patch. Please find the new one
in the attachment. Thanks.
0001-RISC-V-Support-mcmodel-large.patch
Description: Binary data
On Wed, Nov 8, 2023 at 9:22 AM Hongtao Liu wrote:
>
> On Wed, Nov 8, 2023 at 3:53 PM Richard Biener
> wrote:
> >
> > On Wed, Nov 8, 2023 at 2:18 AM Hongtao Liu wrote:
> > >
> > > On Tue, Nov 7, 2023 at 10:34 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Nov 7, 2023 at 2:03 PM Hongtao L
On Fri, 10 Nov 2023, Jakub Jelinek wrote:
> On Fri, Nov 10, 2023 at 08:09:26AM +, Richard Biener wrote:
> > > The following patch adds 6 new type-generic builtins,
> > > __builtin_clzg
> > > __builtin_ctzg
> > > __builtin_clrsbg
> > > __builtin_ffsg
> > > __builtin_parityg
> > > __builtin_popc
Hi,
Originally 16-byte memory to memory is expanded via pattern.
expand_block_move does an optimization on P8 LE to leverage V2DI reversed
load/store for memory to memory move. Now it's done by 16-byte by pieces
move and the optimization is lost. This patch adds an insn_and_split
pattern to retak
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
There the dead code was introduced by init-regs, and there's a
debate about (a) whether init-regs should still be run
On 2023/11/8 11:55, juzhe.zh...@rivai.ai wrote:
Thanks Lehua.
Appreciate for supporting subreg liveness tracking with tons of work.
A nit comments, I think you should mention these following PRs:
106694
89967
106146
99161
No need send V2 now. You can send V2 after Richard and Vlad reviewed
On Wed, Nov 8, 2023 at 5:18 PM Robin Dapp wrote:
>
> Hi,
>
> as Tamar reported in PR112406 we still ICE on aarch64 in SPEC2017
> when creating COND_OPs in ifcvt.
>
> The problem is that we fail to deduce the mask's type from the statement
> vectype and then end up with a non-matching mask in expan
Hi Jeff,
On 2023/11/9 3:13, Jeff Law wrote:
The other thing to ponder. Jivan and I have been banging on Joern's
sub-object tracking bits for a totally different problem in the RISC-V
space. But there may be some overlap.
Essentially Joern's code tracks liveness for a few chunks in registers
On Fri, Nov 10, 2023 at 09:19:14AM +, Richard Biener wrote:
> > Only not promoting the argument will make it directly usable in the
> > stdc_leading_zeros, stdc_leading_ones, stdc_trailing_zeros,
> > stdc_trailing_ones,
> > stdc_first_leading_zero, ..., stdc_count_zeros, stdc_count_ones, ...
>
On Thu, 9 Nov 2023, ??? wrote:
> Hi, Richard.
>
> >> I think it would be better to split out building a tree from VF from both
> >> arms and avoid using 'vf' when LOOP_VINFO_USING_SELECT_VL_P.
>
> I am trying to split out building tree from both arms as you suggested..
> Could you take a look th
Hi Wilco,
> -Original Message-
> From: Wilco Dijkstra
> Sent: Monday, November 6, 2023 12:12 PM
> To: GCC Patches
> Cc: Richard Sandiford ; Richard Earnshaw
>
> Subject: Re: [PATCH] AArch64: Cleanup memset expansion
>
> ping
>
> Cleanup memset implementation. Similar to memcpy/memmov
Hi, Richard.
>> For nested_in_vect_loop we never have LOOP_VINFO_USING_SELECT_VL_P?
Could you give me an example of nested loop ?
For now, I can't produce a case.
Thanks a lot for the comments, I will try to refactor as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-10
Hi Wilco,
> -Original Message-
> From: Wilco Dijkstra
> Sent: Monday, November 6, 2023 12:13 PM
> To: GCC Patches ; Richard Sandiford
>
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] libatomic: Improve ifunc selection on AArch64
>
>
>
> ping
>
>
> From: Wilco Dijkstra
> Sent: 04 Augus
On Fri, Nov 10, 2023 at 10:06 AM Robin Dapp wrote:
>
> Hi,
>
> more fallout from the COND_OP change was shown in PR112464.
>
> It appears as if we "look through" a statement pattern in
> vect_finish_replace_stmt but not before when we replace the newly
> created vector statement's lhs. Then the l
Hi Richard,
在 2023/11/10 17:06, Richard Biener 写道:
> On Fri, Nov 10, 2023 at 8:52 AM HAO CHEN GUI wrote:
>>
>> Hi Richard,
>> Thanks so much for your comments.
>>
>> 在 2023/11/9 19:41, Richard Biener 写道:
>>> I'm not sure if the testcase is valid though?
>>>
>>> @defbuiltin{{void} __builtin_retu
Hi, Richard.
I am sorry for bothering you. I am trying to understand what you mean.
Is this following codes that you want ?
/* Create the vector that holds the step of the induction. */
if (nested_in_vect_loop)
{
/* iv_loop is nested in the loop to be vectorized. Generate:
On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang wrote:
>
> Hi all,
>
> This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
> support, it makes a lot easier to add them comparing to the August version.
> Detail for AVX10 is shown below:
>
> Intel Advanced Vector Extensions 10 (I
I've just committed this patch to fix pr112313 (oops, I forgot to write
the number in the commit message).
The problem was a missed case in the vector reduction expand code.
Andrewamdgcn: Fix vector min/max ICE
The DImode min/max instructions need a clobber that SImode does not, so
add the spe
Lehua Ding writes:
> Hi Richard,
>
> On 2023/11/8 17:40, Richard Sandiford wrote:
>> Tracking subreg liveness will sometimes expose dead code that
>> wasn't obvious without it. PR89606 has an example of this.
>> There the dead code was introduced by init-regs, and there's a
>> debate about (a) wh
Hi Kyrill,
> + /* Reduce the maximum size with -Os. */
> + if (optimize_function_for_size_p (cfun))
> + max_set_size = 96;
> +
> This is a new "magic" number in this code. It looks sensible, but how
> did you arrive at it?
We need 1 instruction to create the value to store (DUP or MO
On Fri, 10 Nov 2023, juzhe.zh...@rivai.ai wrote:
> Hi, Richard.
>
> I am sorry for bothering you. I am trying to understand what you mean.
>
> Is this following codes that you want ?
>
> /* Create the vector that holds the step of the induction. */
> if (nested_in_vect_loop)
> {
>
On Thu, 9 Nov 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, November 9, 2023 11:54 AM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: RE: [PATCH] tree-optimization/111950 - vectorizer loop copying
> >
> > On Thu, 9
Hi Kyrill,
> + if (!(hwcap & HWCAP_CPUID))
> + return false;
> +
> + unsigned long midr;
> + asm volatile ("mrs %0, midr_el1" : "=r" (midr));
> From what I recall that midr_el1 register is emulated by the kernel and so
> userspace software
> has to check that the kernel supports that emula
Thanks a lot. I think I finally understand what you mean now :).
Could you confirm this following codes:?
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 8abc1937d74..5615b16bdcd 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -10306,10 +10306,39 @@ vectorizable
On 2023/11/10 18:16, Richard Sandiford wrote:
Lehua Ding writes:
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
There the dead code was introduced by init-regs,
On Fri, 10 Nov 2023, juzhe.zh...@rivai.ai wrote:
> Thanks a lot. I think I finally understand what you mean now :).
>
> Could you confirm this following codes:?
>
> diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
> index 8abc1937d74..5615b16bdcd 100644
> --- a/gcc/tree-vect-loop.cc
>
Andrew Carlotti writes:
> The availability of tme intrinsics was previously gated at both
> initialisation time (using global target options) and usage time
> (accounting for function-specific target options). This patch removes
> the check at initialisation time, and also moves the intrinsics ou
On Thu, Nov 2, 2023 at 9:43 AM Arsen Arsenović wrote:
>
> Morning!
>
> This patch is a rebase and slight wording tweak of
> https://inbox.sourceware.org/20231006140501.3370874-1-ar...@aarsen.me
>
> Changes since v2:
> - Elaborate on the libintl requirement on non-glibc hosts, per Andrews
> reque
Lehua Ding writes:
> On 2023/11/10 18:16, Richard Sandiford wrote:
>> Lehua Ding writes:
>>> Hi Richard,
>>>
>>> On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
Th
The following avoids type inconsistencies in .COND_op generated by
simplifications of VEC_COND_EXPRs.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR middle-end/112469
* match.pd (cond ? op a : b -> .COND_op (cond, a, b)): Add
missing view_converts.
On Thu, 5 Oct 2023 at 00:00, Brendan Shanks wrote:
>
> Hi,
>
> This patch implements pex_unix_exec_child using posix_spawn when
> available.
>
> This should especially benefit recent macOS (where vfork just calls
> fork), but should have equivalent or faster performance on all
> platforms.
> In ad
Hi,
this teaches operand_compare to compare constant CONSTRUCTORs, which is quite
helpful for so-called fat pointers in Ada, i.e. objects that are semantically
pointers but are represented by structures made up of two pointers. This is
modeled on the implementation present in the ICF pass.
Boots
This test looks like it intends to pass a small struct argument
through both a non-variadic and variadic argument, but due to
the typo, it does not achieve that.
gcc/testsuite/
* gcc.target/aarch64/aapcs64/ice_1.c (foo): Call named.
---
gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c |
On Thu, 9 Nov 2023, Jeff Law wrote:
> > Yeah, I noticed that the scheduler takes care of DEBUG_INSNs as normal
> > operations. When I started to work on this issue, initially I wanted to try
> > something similar to your idea #2, but when checking the APIs, I realized
> > why not just skip the
On 10/11/2023 10:17, Wilco Dijkstra wrote:
Hi Kyrill,
+ /* Reduce the maximum size with -Os. */
+ if (optimize_function_for_size_p (cfun))
+ max_set_size = 96;
+
This is a new "magic" number in this code. It looks sensible, but how did
you arrive at it?
We need 1 instruction
On 23/10/2023 11:43, Richard Biener wrote:
On Fri, 20 Oct 2023, Andrew Stubbs wrote:
This patch fixes a wrong-code bug on amdgcn in which the excess "ones" in the
mask enable extra lanes that were supposed to be unused and are therefore
undefined.
Richi suggested an alternative approach involv
On Fri, 10 Nov 2023, Andrew Stubbs wrote:
> On 23/10/2023 11:43, Richard Biener wrote:
> > On Fri, 20 Oct 2023, Andrew Stubbs wrote:
> >
> >> This patch fixes a wrong-code bug on amdgcn in which the excess "ones" in
> >> the
> >> mask enable extra lanes that were supposed to be unused and are the
On Fri, Nov 10, 2023 at 10:34:29AM +, Richard Sandiford wrote:
> Andrew Carlotti writes:
> > The availability of tme intrinsics was previously gated at both
> > initialisation time (using global target options) and usage time
> > (accounting for function-specific target options). This patch r
PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438
1. Since SELECT_VL result is not necessary always VF in non-final iteration.
Current GIMPLE IR is wrong:
# vect_vec_iv_.8_22 = PHI <_21(4), { 0, 1, 2, ... }(3)>
...
_35 = .SELECT_VL (ivtmp_33, VF);
_21 = vect_vec_iv_.8_22 + { VF, ... };
E.
On Mon, 6 Nov 2023 at 15:50, Tamar Christina wrote:
>
> Hi All,
>
> This patch transforms fneg (fabs (x)) into copysign (x, -1) which is more
> canonical and allows a target to expand this sequence efficiently. Such
> sequences are common in scientific code working with gradients.
>
> There is an
> -Original Message-
> From: Wilco Dijkstra
> Sent: Friday, November 10, 2023 10:23 AM
> To: Kyrylo Tkachov ; GCC Patches patc...@gcc.gnu.org>; Richard Sandiford
> Subject: Re: [PATCH] libatomic: Improve ifunc selection on AArch64
>
> Hi Kyrill,
>
> > + if (!(hwcap & HWCAP_CPUID))
Hi Prathamesh,
Yes Arm requires SIMD for copysign. The testcases fail because they don't turn
on Neon.
I'll update them.
Regards,
Tamar
From: Prathamesh Kulkarni
Sent: Friday, November 10, 2023 12:24 PM
To: Tamar Christina
Cc: gcc-patches@gcc.gnu.org ; nd ;
Hi Juzhe,
LGTM. The test patterns are a bit unwieldy but not a blocker
IMHO. Could probably done shorter using macro magic?
Regards
Robin
Hi,
this patch fixes several more FAILs that would only show up in 32-bit runs.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Adjust.
* gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autov
On Fri, Nov 10, 2023 at 8:14 AM Jin Ma wrote:
>
> The t0 register is used as a temporary register for interrupts, so it needs
> special treatment. It is necessary to avoid using "th.ldd" in the interrupt
> program to stop the subsequent operation of the t0 register, so they need to
> exchange posi
On Fri, 10 Nov 2023, Tamar Christina wrote:
>
> Hi Prathamesh,
>
> Yes Arm requires SIMD for copysign. The testcases fail because they don't
> turn on Neon.
>
> I'll update them.
On x86_64 with -m32 I see
FAIL: gcc.dg/pr55152-2.c scan-tree-dump-times optimized ".COPYSIGN" 1
FAIL: gcc.dg/pr55
The following fixes the issue that when SLP stmts are internal defs
but appear invariant because they end up only using invariant defs
then they get scheduled outside of the loop. This nice optimization
breaks down when loop masks or lens are applied since those are not
explicitly tracked as depen
LGTM
Christoph Müllner 於 2023年11月10日 週五，20:55寫道：
> On Fri, Nov 10, 2023 at 8:14 AM Jin Ma wrote:
> >
> > The t0 register is used as a temporary register for interrupts, so it
> needs
> > special treatment. It is necessary to avoid using "th.ldd" in the
> interrupt
> > program to stop the subsequ
Thanks. Robin. Committed.
>> The test patterns are a bit unwieldy but not a blocker
>>IMHO. Could probably done shorter using macro magic?
I have no idea. But I think we can revisit it and refine tests when we have
time.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-10 20:47
To: Juzhe
On Fri, Nov 10, 2023 at 12:01 PM Prathamesh Kulkarni
wrote:
>
> On Thu, 5 Oct 2023 at 00:00, Brendan Shanks wrote:
> >
> > Hi,
> >
> > This patch implements pex_unix_exec_child using posix_spawn when
> > available.
> >
> > This should especially benefit recent macOS (where vfork just calls
> > fo
On Fri, Nov 10, 2023 at 2:20 PM Kito Cheng wrote:
>
> LGTM
Committed after shortening the commit message's heading.
>
> Christoph Müllner 於 2023年11月10日 週五，20:55寫道：
>>
>> On Fri, Nov 10, 2023 at 8:14 AM Jin Ma wrote:
>> >
>> > The t0 register is used as a temporary register for interrupts, so it
On Fri, Nov 10, 2023 at 12:17 PM Eric Botcazou wrote:
>
> Hi,
>
> this teaches operand_compare to compare constant CONSTRUCTORs, which is quite
> helpful for so-called fat pointers in Ada, i.e. objects that are semantically
> pointers but are represented by structures made up of two pointers. Thi
On Fri, Nov 10, 2023 at 12:25 PM Alexander Monakov wrote:
>
>
> On Thu, 9 Nov 2023, Jeff Law wrote:
>
> > > Yeah, I noticed that the scheduler takes care of DEBUG_INSNs as normal
> > > operations. When I started to work on this issue, initially I wanted to
> > > try
> > > something similar to yo
On Fri, 10 Nov 2023, Juzhe-Zhong wrote:
> PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438
>
> 1. Since SELECT_VL result is not necessary always VF in non-final iteration.
>
> Current GIMPLE IR is wrong:
>
> # vect_vec_iv_.8_22 = PHI <_21(4), { 0, 1, 2, ... }(3)>
> ...
> _35 = .SELECT_VL
On Fri, Nov 10, 2023 at 11:10 AM HAO CHEN GUI wrote:
>
> Hi Richard,
>
> 在 2023/11/10 17:06, Richard Biener 写道:
> > On Fri, Nov 10, 2023 at 8:52 AM HAO CHEN GUI wrote:
> >>
> >> Hi Richard,
> >> Thanks so much for your comments.
> >>
> >> 在 2023/11/9 19:41, Richard Biener 写道:
> >>> I'm not sure
On Fri, Nov 10, 2023 at 2:52 AM liuhongt wrote:
>
> When I'm working on PR112443, I notice there's some misoptimizations: after we
> fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine it
> back to v{,p}blendv{v,ps,pd} since the pattern is too complicated, so I think
> maybe
The t0 register is used as a temporary register for interrupts, so it needs
special treatment. It is necessary to avoid using "th.ldd" in the interrupt
program to stop the subsequent operation of the t0 register, so they need to
exchange positions in the function "riscv_for_each_saved_reg".
gcc/Ch
On Fri, Nov 10, 2023 at 7:42 AM Ajit Agarwal wrote:
>
> Hello Richard:
>
>
> On 09/11/23 6:21 pm, Richard Biener wrote:
> > On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote:
> >>
> >> tree-ssa-loop-ivopts : Add live analysis in regs used in decision making.
> >>
> >> Add live anaysis in regs use
I thought Christoph was already committed? Do you mind describing the
difference between v1 and v2?
On Fri, Nov 10, 2023 at 9:55 PM Jin Ma wrote:
> The t0 register is used as a temporary register for interrupts, so it needs
> special treatment. It is necessary to avoid using "th.ldd" in the inte
On Fri, 10 Nov 2023, Richard Biener wrote:
> > I'm afraid ignoring debug-only BBs goes contrary to overall var-tracking
> > design:
> > DEBUG_INSNs participate in dependency graph so that schedulers can remove or
> > mutate them as needed when moving real insns across them.
>
> Note that debug
I'm very sorry, I misunderstood. There's no difference between them, please
ignore it.
马进
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On Fri, Nov 10, 2023 at 3:18 PM Alexander Monakov wrote:
>
>
> On Fri, 10 Nov 2023, Richard Biener wrote:
>
> > > I'm afraid ignoring debug-only BBs goes contrary to overall var-tracking
> > > design:
> > > DEBUG_INSNs participate in dependency graph so that schedulers can remove
> > > or
> > >
On 11/10/23 03:39, Richard Sandiford wrote:
Lehua Ding writes:
On 2023/11/10 18:16, Richard Sandiford wrote:
Lehua Ding writes:
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has
Hello Richard:
On 10/11/23 7:29 pm, Richard Biener wrote:
> On Fri, Nov 10, 2023 at 7:42 AM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>>
>> On 09/11/23 6:21 pm, Richard Biener wrote:
>>> On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote:
tree-ssa-loop-ivopts : Add live analysis in re
On Fri, 10 Nov 2023, Richard Biener wrote:
> On Fri, Nov 10, 2023 at 3:18 PM Alexander Monakov wrote:
> >
> >
> > On Fri, 10 Nov 2023, Richard Biener wrote:
> >
> > > > I'm afraid ignoring debug-only BBs goes contrary to overall
> > > > var-tracking design:
> > > > DEBUG_INSNs participate in de
> -Original Message-
> From: Richard Earnshaw
> Sent: Friday, November 10, 2023 11:31 AM
> To: Wilco Dijkstra ; Kyrylo Tkachov
> ; GCC Patches
> Cc: Richard Sandiford ; Richard Earnshaw
>
> Subject: Re: [PATCH] AArch64: Cleanup memset expansion
>
>
>
> On 10/11/2023 10:17, Wilco Dij
On Wed, 1 Nov 2023, Patrick Palka wrote:
> On Tue, 31 Oct 2023, Patrick Palka wrote:
>
> > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> > trunk? Does it look OK for release branches as well for sake of PR111703?
Ping.
> >
> > -- >8 --
> >
> > potential_constant_
On Tue, Nov 7, 2023 at 4:04 AM Jin Ma wrote:
>
> The XTheadInt ISA extension provides acceleration interruption
> instructions as defined in T-Head-specific:
>
> * th.ipush
> * th.ipop
Overall, it looks ok to me.
There are just a few small issues to clean up (see below).
>
> gcc/ChangeLog:
>
>
On Thu, 9 Nov 2023, Jason Merrill wrote:
> On 11/8/23 16:59, Patrick Palka wrote:
> > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> > trunk?
> >
> > -- >8 --
> >
> > Here when building up the non-dependent .* expression, we crash from
> > fold_convert on 'b.a' due to
On 10/11/2023 14:46, Kyrylo Tkachov wrote:
-Original Message-
From: Richard Earnshaw
Sent: Friday, November 10, 2023 11:31 AM
To: Wilco Dijkstra ; Kyrylo Tkachov
; GCC Patches
Cc: Richard Sandiford ; Richard Earnshaw
Subject: Re: [PATCH] AArch64: Cleanup memset expansion
On 10
On Fri, 10 Nov 2023, Patrick Palka wrote:
> On Thu, 9 Nov 2023, Jason Merrill wrote:
>
> > On 11/8/23 16:59, Patrick Palka wrote:
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> > > trunk?
> > >
> > > -- >8 --
> > >
> > > Here when building up the non-dependent
Use unrelated register initializations using zero/sign-extend instructions
to clear stack protector scratch register.
Handle only SI -> DImode extensions for 64-bit targets, as this is the
only extension that triggers the peephole in a non-negligible number.
Also use explicit check for word_mode
This patch allows an .md iterator to include the contents of
previous iterators, possibly with an extra condition attached.
Too much indirection might become hard to follow, so for the
AArch64 changes I tried to stick to things that seemed likely
to be uncontroversial:
(a) structure iterators tha
On Fri, Nov 10, 2023 at 04:53:57PM +0800, Lehua Ding wrote:
> > > The divide by zero error above is interesting. I'm not sure why
> > > ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in
> > > the following rtx:
> > > (debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168
Hi.
This patch fixes the segfault when using -flto with libgccjit (bug
111396).
You mentioned in bugzilla that this didn't fix the reproducer for you,
but it does for me.
At first, the test case would not pass, but running "make install" made
it pass.
Not sure if this is normal.
Could you please
Andris Pavēnis writes:
> Fixing these errors (attached patch for master branch) was not sufficient for
> building Ada cross-compiler, but it fixed compiler errors.
>
> This would perhaps qualify for trivial change, but it seems that I no more
> have
> write access (I got it in 2015, but have n
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
The patch was successfully bootstrapped an tested on x86-64, ppc64le,
and aarch64.
commit b3d1d30eeed67c78e223c146a464d2fdd1dde894
Author: Vladimir N. Makarov
Date: Fri Nov 10 11:14:46 2023 -0500
[IRA]: Check
On Thu, 9 Nov 2023, Jason Merrill wrote:
> On 11/7/23 10:08, Patrick Palka wrote:
> > bootstrapped and regtested on x86_64-pc-linxu-gnu, does this look OK for
> > trunk?
> >
> > -- >8 --
> >
> > In the COMPOUND_EXPR case of tsubst_expr, we were redundantly clearing
> > the tf_decltype flag when
On 11/9/23 17:34, Jeff Law wrote:
On 11/3/23 00:18, Patrick O'Neill wrote:
On non-vector targets dejagnu attempts dg-do compile for pr95401.cc.
This produces a command like this:
g++ pr95401.cc pr95401a.cc -S -o pr95401.s
which isn't valid (gcc does not accept multiple input files when using
* config/aarch64/linux-unwind.h
(aarch64_fallback_frame_state): Add cast to the expected type
in sc assignment.
(Almost a v2, but the other issue was already fixed via in r14-4183.)
---
libgcc/config/aarch64/linux-unwind.h | 5 -
1 file changed, 4 insertions(+), 1 del
On 11/9/23 17:20, Jeff Law wrote:
On 11/2/23 17:45, Patrick O'Neill wrote:
Testcases in g++.dg/vect rely on check_vect_support_and_set_flags
to set dg-do-what-default and avoid running vector tests on non-vector
targets. The three testcases in this patch overwrite the default with
dg-do run.
On 11/10/23 12:25, Patrick Palka wrote:
On Thu, 9 Nov 2023, Jason Merrill wrote:
On 11/7/23 10:08, Patrick Palka wrote:
bootstrapped and regtested on x86_64-pc-linxu-gnu, does this look OK for
trunk?
-- >8 --
In the COMPOUND_EXPR case of tsubst_expr, we were redundantly clearing
the tf_declt
On Thu, Nov 09, 2023 at 03:27:11PM +0800, Hongtao Liu wrote:
> On Thu, Nov 9, 2023 at 3:15 PM Hu, Lin1 wrote:
> >
> > This patch aims to avoid generate vblendps with ymm16+, And have
> > bootstrapped and tested on x86_64-pc-linux-gnu{-m32,-m64}. Ok for trunk?
> >
> > gcc/ChangeLog:
> >
> >
On Fri, 10 Nov 2023, Jason Merrill wrote:
> On 11/10/23 12:25, Patrick Palka wrote:
> > On Thu, 9 Nov 2023, Jason Merrill wrote:
> >
> > > On 11/7/23 10:08, Patrick Palka wrote:
> > > > bootstrapped and regtested on x86_64-pc-linxu-gnu, does this look OK for
> > > > trunk?
> > > >
> > > > -- >8
On 11/8/23 04:09, Mary Bennett wrote:
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
Hel
On 11/6/23 05:24, Richard Sandiford wrote:
attribute_ignored_p already used a namespace-aware query
to find the attribute_spec for an existing attribute:
const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr));
This patch does the same for other callers in the file.
Te
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