Here is a patch that adds the missing cases for vla size instrumentation.
This now includes all cases where a type with size < 0 is created,
which is already UB and not just cases where a VLA is allocated. But
a VLA can be allocated based on an typedef, which is also now
indirectly protected in
Improve stack protector patterns and peephole2s to substitute stack
protector scratch register clear with unrelated subsequent register
initialization in several ways:
a. Explicitly generate scratch register as named pseudo. This allows
optimizers to eventually reuse the zero value in the registe
On Mon, Oct 30, 2023 at 6:27 PM Roger Sayle wrote:
>
>
> This patch is a follow-up to my previous PR target/110551 patch, this
> time to address the additional move after mulx, seen on TARGET_BMI2
> architectures (such as -march=haswell). The complication here is
> that the flexible multiple-set
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
Ready push to trunk.
gcc/ChangeLog:
* config/i386/mmx.md (cmlav4hf4): New expander.
(cmla_conjv4hf4): Ditto.
(cmulv4hf3): Ditto.
(cmul_conjv4hf3): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/p
> >
> > Hi Lipeng,
> >
> > >>> Sure, as your comments, in the patch V6, I added 3 test cases with
> > >>> OpenMP to test different cases in concurrency respectively:
> > >>> 1. find and create unit very frequently to stress read lock and write
> > >>> lock.
> > >>> 2. only access the unit which ex
Hi Uros,
> From: Uros Bizjak
> Sent: 01 November 2023 10:05
> Subject: Re: [x86_64 PATCH] PR target/110551: Tweak mulx register allocation
> using peephole2.
>
> On Mon, Oct 30, 2023 at 6:27 PM Roger Sayle
> wrote:
> >
> >
> > This patch is a follow-up to my previous PR target/110551 patch, t
Hi, I'd like to ping the following patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633191.html
On Mon, Oct 16, 2023 at 8:50 PM Eric Gallager wrote:
>
> On Mon, Oct 16, 2023 at 7:58 PM Andrew Pinski wrote:
> >
> > On Mon, Oct 16, 2023, 16:39 Eric Gallager wrote:
> >>
> >> Currentl
> On Oct 31, 2023, at 6:14 PM, Joseph Myers wrote:
>
> On Tue, 31 Oct 2023, Qing Zhao wrote:
>
>> 2.3 A new semantic requirement in the user documentation of "counted_by"
>>
>> For the following structure including a FAM with a counted_by attribute:
>>
>> struct A
>> {
>> size_t size;
>>
Am Mittwoch, dem 01.11.2023 um 14:47 + schrieb Qing Zhao:
>
> > On Oct 31, 2023, at 6:14 PM, Joseph Myers wrote:
> >
> > On Tue, 31 Oct 2023, Qing Zhao wrote:
> >
> > > 2.3 A new semantic requirement in the user documentation of "counted_by"
> > >
> > > For the following structure includin
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);
however ge
On Tue, 31 Oct 2023, Patrick Palka wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> trunk? Does it look OK for release branches as well for sake of PR111703?
>
> -- >8 --
>
> potential_constant_expression was incorrectly treating most local
> variables from a
On 11/1/23 08:11, Eric Gallager wrote:
Hi, I'd like to ping the following patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633191.html
OK for the trunk.
jeff
Am Dienstag, dem 31.10.2023 um 22:19 + schrieb Joseph Myers:
> On Tue, 31 Oct 2023, Martin Uecker wrote:
>
> > > + if (TREE_CODE (arg) == INTEGER_CST
> > > + && tree_int_cst_lt (arg, TYPE_SIZE_UNIT (ttl)))
>
> What if TYPE_SIZE_UNIT (ttl) is not an INTEGER_CST? I don't see an
> On Nov 1, 2023, at 11:00 AM, Martin Uecker wrote:
>
> Am Mittwoch, dem 01.11.2023 um 14:47 + schrieb Qing Zhao:
>>
>>> On Oct 31, 2023, at 6:14 PM, Joseph Myers wrote:
>>>
>>> On Tue, 31 Oct 2023, Qing Zhao wrote:
>>>
2.3 A new semantic requirement in the user documentation of "c
Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subword_address.
gcc/ChangeLog:
* config
> Am 31.10.2023 um 16:10 schrieb pan2...@intel.com:
>
> From: Pan Li
>
> Update in v4:
>
> * Append the check to vectorizable_internal_function.
>
> Update in v3:
>
> * Add func to predicate type size is legal or not for vectorizer call.
>
> Update in v2:
>
> * Fix one ICE of type asser
On 11/1/2023 8:07 AM, Vladimir Makarov wrote:
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_h
The interpretation request came in a long time ago but I only just got
around to implementing it.
The updated text from the standard is in the comment. Now I am writing
this, I think that I should perhaps use switch(op)/case rather than using
if/else if and depending on the order of the gfc_intrin
Joseph and Martin,
For the task to replace every reference to a FAM field with an call to
.ACCESS_WITH_SIZE,
Where in the C FE I should look at?
Thanks a lot for the help.
Qing
Polite ping on this.
> On Oct 4, 2023, at 11:28 AM, Brendan Shanks wrote:
>
> Hi,
>
> This patch implements pex_unix_exec_child using posix_spawn when
> available.
>
> This should especially benefit recent macOS (where vfork just calls
> fork), but should have equivalent or faster performance
Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled
assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 6 ++
1 file changed
Am Mittwoch, dem 01.11.2023 um 18:14 + schrieb Qing Zhao:
> Joseph and Martin,
>
> For the task to replace every reference to a FAM field with an call to
> .ACCESS_WITH_SIZE,
> Where in the C FE I should look at?
>
> Thanks a lot for the help.
>
>
build_component_ref in c_decl.cc
Martin
On 11/1/23 12:17, Edwin Lu wrote:
Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled
assert
OK. Really interested to see how often this
On 11/1/23 10:14, Patrick O'Neill wrote:
Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subw
On 11/1/23 00:56, Juzhe-Zhong wrote:
Consider this following intrinsic code:
void rvv_dot_prod(int16_t *pSrcA, int16_t *pSrcB, uint32_t n, int64_t *result)
{
size_t vl;
vint16m4_t vSrcA, vSrcB;
vint64m1_t vSum = __riscv_vmv_s_x_i64m1(0, 1);
while (n > 0) {
vl = _
On 10/31/23 17:25, Patrick O'Neill wrote:
This patch transitions the ztso testcases to use the testsuite infrastructure,
enabling the tests on both rv64 and rv32 targets.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to
dg-options
On 10/31/23 12:35, Vineet Gupta wrote:
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't work, but stepping thru the
debugger shows old code didn't and fixed do
On 11/1/23 12:11, Jeff Law wrote:
On 10/31/23 12:35, Vineet Gupta wrote:
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't work, but stepping thru the
debugg
On Wed, Nov 1, 2023 at 1:58 PM Roger Sayle wrote:
>
>
> Hi Uros,
>
> > From: Uros Bizjak
> > Sent: 01 November 2023 10:05
> > Subject: Re: [x86_64 PATCH] PR target/110551: Tweak mulx register allocation
> > using peephole2.
> >
> > On Mon, Oct 30, 2023 at 6:27 PM Roger Sayle
> > wrote:
> > >
> >
Hi Paul,
Am 01.11.23 um 19:02 schrieb Paul Richard Thomas:
The interpretation request came in a long time ago but I only just got
around to implementing it.
The updated text from the standard is in the comment. Now I am writing
this, I think that I should perhaps use switch(op)/case rather than
On Wed, 1 Nov 2023, Martin Uecker wrote:
> Am Dienstag, dem 31.10.2023 um 22:19 + schrieb Joseph Myers:
> > On Tue, 31 Oct 2023, Martin Uecker wrote:
> >
> > > > + if (TREE_CODE (arg) == INTEGER_CST
> > > > + && tree_int_cst_lt (arg, TYPE_SIZE_UNIT (ttl)))
> >
> >
On 11/1/23 12:19, Vineet Gupta wrote:
On 11/1/23 12:11, Jeff Law wrote:
On 10/31/23 12:35, Vineet Gupta wrote:
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code d
Fixes: 3496ca4e6566 ("RISC-V: Add runtime invariant support")
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case. It intends to do that however the code is broken (regression).
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old c
Hello-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112319
This is a one-line patch to fix the GCC 14 regression noted in the
PR. Bootstrap + regtest all languages on x86-64 looks good. Is it OK please?
Thanks!
-Lewis
-- >8 --
Since r14-2893, the frontend parser object needs to exist when runn
On 11/1/23 12:03, Jeff Law wrote:
On 10/31/23 17:25, Patrick O'Neill wrote:
This patch transitions the ztso testcases to use the testsuite
infrastructure,
enabling the tests on both rv64 and rv32 targets.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add
On 11/1/23 12:00, Jeff Law wrote:
On 11/1/23 10:14, Patrick O'Neill wrote:
Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all su
Dear all,
I've dusted off and cleaned up a previous attempt to fix the handling
of allocatable or pointer actual arguments to OPTIONAL+VALUE dummies.
The standard says that a non-allocated / non-associated actual argument
in that case shall be treated as non-present.
However, gfortran's calling c
On Mon, 18 Sep 2023, Jonathan Wakely via Gcc-patches wrote:
> @@ -103,8 +103,10 @@ ln -s libiconv-1.16 libiconv
>
> If GCC 3.1.0 or later on is being used on GNU/Linux, an attempt
> will be made to use "C" library functionality necessary for
> - C++ named locale support
Just want to quickly check, when is the cutoff for GCC14 exactly? I
want to know how much time I have left to try to tackle this bug with
subscript. I'm going to be crunching out final stuff this week and I'll
try to get a (probably non-final) patch for you to review today.
Alex
On Wed, Nov 1, 2023 at 11:31 AM Jeff Law wrote:
>
>
>
> On 11/1/23 08:11, Eric Gallager wrote:
> > Hi, I'd like to ping the following patch:
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633191.html
> OK for the trunk.
>
Thanks, committed as r14-5064-g2b9778c8d9d331:
https://gcc.
On Wed, Nov 1, 2023 at 7:25 PM Eric Gallager wrote:
>
> On Wed, Nov 1, 2023 at 11:31 AM Jeff Law wrote:
> >
> >
> >
> > On 11/1/23 08:11, Eric Gallager wrote:
> > > Hi, I'd like to ping the following patch:
> > >
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633191.html
> > OK for
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, November 2, 2023 3:02 AM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Allow dest operand and accumulator operand o
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, November 2, 2023 12:43 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; Liu, Hongtao
Subject: Re: [PATCH v4] VECT: Refine the type size res
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple
intrinsics.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Define
non-tuple intrinsics.
* config/riscv/r
This patch fixes following FAILs for RVV:
FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects scan-tree-dump vect
"Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP
stmts"
Bootstrap on X86 and regtest passed.
Tested on aarch64 pas
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-02 08:54
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
*
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-11-02 09:00
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11
> -Original Message-
> From: Uros Bizjak
> Sent: Thursday, November 2, 2023 3:23 AM
> To: Roger Sayle
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [x86_64 PATCH] PR target/110551: Tweak mulx register allocation
> using peephole2.
>
> On Wed, Nov 1, 2023 at 1:58 PM Roger Sayle
> wrote:
>
Notice that there are some reundant 'vimov' codes in attribute.
Committed as it is obvious.
gcc/ChangeLog:
* config/riscv/vector.md: Fix redundant codes in attributes.
---
gcc/config/riscv/vector.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/risc
With compile option --param=riscv-autovec-preference=fixed-vlmax, we have
redundant AVL/VL toggling:
vsetvli a5,a3,e8,mf4,ta,ma -> should be changed into e32m1
vle32.v v1,0(a1)
vle32.v v2,0(a0)
vsetivlizero,4,e32,m1,ta,ma -> redundant
sllia2,a5,2
From: Pan Li
The extract_low_bits only try the scalar mode if the bitsize of
the mode and src_mode is not equal. When vector mode is given
from get_stored_val in DSE, it will always fail and return NULL_RTX.
This patch would like to allow the vector mode in the extract_low_bits
if and only if th
With compile option --param=riscv-autovec-preference=fixed-vlmax, we have
redundant AVL/VL toggling:
vsetvli a5,a3,e8,mf4,ta,ma -> should be changed into e32m1
vle32.v v1,0(a1)
vle32.v v2,0(a0)
vsetivlizero,4,e32,m1,ta,ma -> redundant
sllia2,a5,2
update with more dump information in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/634950.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-02 11:06
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix redundant vs
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