[pushed] testsuite, X86, Darwin: Skip tests with incompatible output.

Tested on x86_64-darwin, pushed to trunk, thanks Iain --- 8< --- Darwin platforms do not currently emit .cfi_xxx instructions so that these tests do not work there. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-interrupt-1.c: Skip for Darwin. * gcc.target/i386/apx-push2pop2-1.c

[pushed] testsuite, X86, Darwin: Skip a test for mcmodel=large.

Tested on x86_64-darwin, pushed to trunk, thanks Iain --- 8< --- The large model is not implemented so far for Darwin (and the codegen will be different when it is). gcc/testsuite/ChangeLog: * gcc.target/i386/large-data.c: Skip for Darwin. Signed-off-by: Iain Sandoe --- gcc/testsuite

[PATCH] testsuite, x86: Handle a broken assembler.

Tested on x86_64-darwin and x86_64-linux, OK for trunk? thanks Iain --- 8< --- Earlier assembler support for complex fp16 on x86_64 Darin is broken. This adds an additional test to the existing target-supports that fails for the broken assemblers but works for the newer, fixed, ones. gcc/testsui

[ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs.

This patch overhauls the ARC backend's insn_cost target hook, and makes some related improvements to rtx_costs, BRANCH_COST, etc. The primary goal is to allow the backend to indicate that shifts and rotates are slow (discouraged) when the CPU doesn't have a barrel shifter. I should also acknowled

[PATCH V15 4/4] ree: Improve ree pass using defined abi interfaces

Hello Vineet, Jeff and Bernhard: This version 15 of the patch uses abi interfaces to remove zero and sign extension elimination. Bootstrapped and regtested on powerpc-linux-gnu. In this version (version 15) of the patch following review comments are incorporated. a) Removal of hard code zero_e

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

On 28/10/23 3:55 pm, Ajit Agarwal wrote: > > > On 27/10/23 10:46 pm, Bernhard Reutner-Fischer wrote: >> On Wed, 25 Oct 2023 16:41:07 +0530 >> Ajit Agarwal wrote: >> >>> On 25/10/23 2:19 am, Vineet Gupta wrote: On 10/24/23 13:36, rep.dot@gmail.com wrote: > As said, I don't s

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

On 28/10/23 3:56 pm, Ajit Agarwal wrote: > > > On 28/10/23 4:09 am, Vineet Gupta wrote: >> >> >> On 10/27/23 10:16, Bernhard Reutner-Fischer wrote: >>> On Wed, 25 Oct 2023 16:41:07 +0530 >>> Ajit Agarwal wrote: >>> On 25/10/23 2:19 am, Vineet Gupta wrote: > On 10/24/23 13:36, rep.dot

[PATCH] Fix PR ada/111909 On Darwin, determine filesystem case sensitivity at runtime

This change affects only Ada. In gcc/ada/adaint.c(__gnat_get_file_names_case_sensitive), the assumption for __APPLE__ is that file names are case-insensitive unless __arm__ or __arm64__ are defined, in which case file names are declared case-sensitive. The associated comment is "By default, we

RE: [Ready to commit V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

Should be fixed by the below PATCH, feel free to ping me if any issues. https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634616.html Pan -Original Message- From: Andreas Schwab Sent: Saturday, October 28, 2023 4:16 PM To: 钟居哲 Cc: patrick ; gcc-patches ; kito.cheng ; rdapp.gcc

Re: [PATCH] tree-optimization/109334: Improve computation for access attribute

On 2023-10-28 16:29, Martin Uecker wrote: Isn't this testcase h() in builtin-dynamic-object-size-20.c? If you're referring to testcase i(), then maybe "where the size is given by a non-trivial function of a function parameter, e.g. fn (size_t n, char buf[dummy(n)])." h() is supported. For i()

[Patch, fortran] PR104555 - ICE in gfc_compare_derived_types, at fortran/interface.cc:628 since r10-2912-g70570ec192745095

Bizarrely, since the fix for pr101625, the testcase compiles and runs correctly with s/select type (y => x)/select type (y => (x))/ ! The fix is straightforward and appears to be one of those wrinkles arising from the use of associate variables as a selector. The fault is reasonable since the expr

Re: [PING][PATCH] Include safe-ctype.h after C++ standard headers, to avoid over-poisoning

Dimitry Andric writes: > Ping. It would be nice to get this QoL fix in. > Yes please - we've been using this in Gentoo since around when it was first posted. No complaints. I cannot approve but it looks good to me. > -Dimitry > >> On 28 Sep 2023, at 18:37, Dimitry Andric wrote: >> >> Ref:

[committed] d: Merge upstream dmd, druntime e48bc0987d, phobos 2458e8f82.

Hi, This patch merges the D front-end and runtime library with upstream dmd e48bc0987d, and standard library with phobos 2458e8f82. Synchronizing with the v2.106.0-beta.1 release. D front-end changes: - Import dmd v2.106.0-beta.1. D runtime changes: - Import druntime v2.106.0-beta.1.

[PATCH 0/3] start of moving value replacement from phiopt to match

This set of 3 patches, copy what is being done in value replacement and puts it into match-and-simplify form. I will be rewriting value_replacement in phiopt to use match and simplify directly in the next few months but I thought getting these into match form earlier on can help improve code genera

[PATCH 2/3] MATCH: Move jump_function_from_stmt support to match.pd

This moves the value_replacement support for jump_function_from_stmt to match pattern. This allows us to optimize things earlier in phiopt1 rather than waiting to phiopt2. Which means phiopt1 needs to be disable for vrp03.c testcase. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog:

[PATCH 3/3] MATCH: Add some more value_replacement simplifications to match

This moves a few more value_replacements simplifications to match. /* a == 1 ? b : a * b -> a * b */ /* a == 1 ? b : b / a -> b / a */ /* a == -1 ? b : a & b -> a & b */ Also adds a testcase to show can we catch these where value_replacement would not (but other passes would). Bootstrapped and

[PATCH 1/3] MATCH: first of the value replacement moving from phiopt

This moves a few simple patterns that are done in value replacement in phiopt over to match.pd. Just the simple ones which might show up in other code. This allows some optimizations to happen even without depending on sinking from happening and in some cases where phiopt is not invoked (cond-1.c

Re: [Patch, fortran] PR104555 - ICE in gfc_compare_derived_types, at fortran/interface.cc:628 since r10-2912-g70570ec192745095

Hi Paul, code->expr1->symtree->n.sym->ts = code->expr2->ts; + /* Sometimes the selector expression is given the typespec of the +'_data' field, which is logical enough but inappropraite here. */ s/inappropraite/inappropriate/ + if (code->expr2->ts.type ==

[committed] d: Fix ICE: verify_gimple_failed (conversion of register to a different size in 'view_convert_expr') [PR110712]

Hi, This patch fixes an ICE cause by the way the D front-end generates its codegen around va_list types. Static arrays in D are passed around by value, rather than decaying to a pointer. On x86_64 __builtin_va_list is an exception to this rule, but semantically it's still treated as a static arr

[committed][_GLIBCXX_INLINE_VERSION] Fix constract violation

This fixes handle_contract_violation under versioned namespace mode. Tested under Linux x64 and confirmed to also fix Darwin build. libstdc++: [_GLIBCXX_INLINE_VERSION] Provide handle_contract_violation symbol libstdc++-v3/ChangeLog:     * src/experimental/contract.cc     [_GLIBCXX_I

[committed][_GLIBCXX_INLINE_VERSION] Add emul TLS symbol exports

libstdc++: [_GLIBCXX_INLINE_VERSION] Add emul TLS symbols libstdc++-v3/ChangeLog:     * config/abi/pre/gnu-versioned-namespace.ver: Add missing emul TLS     symbols. François diff --git a/libstdc++-v3/config/abi/pre/gnu-versioned-namespace.ver b/libstdc++-v3/config/abi/pre/gnu-versioned-namespa

Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension

On 10/20/23 03:53, Christoph Muellner wrote: From: Christoph Müllner The XTheadMemIdx ISA extension provides a additional load and store instructions with new addressing modes. The following memory accesses types are supported: * load: b,bu,h,hu,w,wu,d * store: b,h,w,d The following addres

Re: [PATCH v2 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension

On 10/20/23 03:53, Christoph Muellner wrote: From: Christoph Müllner The XTheadFMemIdx ISA extension provides additional load and store instructions for floating-point registers with new addressing modes. The following memory accesses types are supported: * load/store: [w,d] (single-precisi

Re: [PATCH v4 1/1] gcc: config: microblaze: fix cpu version check

On 10/26/23 13:37, Neal Frager wrote: The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previ

Re: Enable top-level recursive 'autoreconf'

> From: Thomas Schwinge > Date: Thu, 19 Oct 2023 12:42:26 +0200 > It's just GCC and Binutils/GDB, or are the top-level files also shared > with additional projects? Not sure if that counts as "shared", but I regularly drop in* newlib to build simulator targets (*-elf, *-newabi). That's git://sou

[PATCH v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. And subsequently REE fails to eliminate them a

Re: [ARC PATCH] Convert (signed<<31)>>31 to -(signed&1) without barrel shifter.

On 10/28/23 10:47, Roger Sayle wrote: This patch optimizes PR middle-end/101955 for the ARC backend. On ARC CPUs with a barrel shifter, using two shifts is (probably) optimal as: asl_s r0,r0,31 asr_s r0,r0,31 but without a barrel shifter, GCC -O2 -mcpu=em currently ge

Re: [PATCH, expand] Checking available optabs for scalar modes in by pieces operations

Committed as r14-5001. Thanks Gui Haochen 在 2023/10/27 17:29, Richard Sandiford 写道: > HAO CHEN GUI writes: >> Hi, >> This patch checks available optabs for scalar modes used in by >> pieces operations. It fixes the regression cases caused by previous >> patch. Now both scalar and vector modes

Re: [PATCH v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/29/23 19:04, Vineet Gupta wrote: RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. An

[PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. And subsequently REE fails to eliminate them a

RE: [x86 PATCH] PR target/110551: Fix reg allocation for widening multiplications.

Hi Roger, It seems that your patch caused some regression on x86_64: https://gcc.gnu.org/pipermail/gcc-regression/2023-October/078390.html https://gcc.gnu.org/pipermail/gcc-regression/2023-October/078391.html Could you help verify that? A simple reproducer under build folder will be: make chec

[PATCH v5 1/1] gcc: config: microblaze: fix cpu version check

The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previous versions. Signed-off-by: Neal Frage

[PATCH] rs6000: Consider inline asm as safe if no assembler complains [PR111828]

Hi, As discussed in PR111828, rs6000_update_ipa_fn_target_info is much conservative, currently for any non-empty inline asm, without any parsing, it would take inline asm could have HTM insns. It means for one function attributed with power8 having inline asm, even if it has no HTM insns, we don'