Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

I saw RVC has MASK_RVC and TARGET_RVC in options.h? On Wed, Sep 6, 2023 at 2:39 PM Feng Wang wrote: > > According to the doc, take“Mask(VECTOR_ELEN_32) > Var(riscv_vector_elen_flags)”as example, > it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate > MASK_VECTOR_ELEN_32 > and

Re: Re: [PATCH 2/2] [RISC-V] Enalble zcmp for -Os

On Wed, Sep 6, 2023 at 9:47 AM Fei Gao wrote: > > On 2023-09-05 20:02 Kito Cheng wrote: > > > >> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct > >> riscv_frame_info *frame) > >> { > >>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed > >>|| cfun->machin

Re: [PATCH] RISC-V: Add conditional sqrt autovec pattern

Got failed on the trunk, could you take a look? === gcc: Unexpected fails for rv32imafdc ilp32d medlow === FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sq

Re: [PATCH] RISC-V: Add conditional sqrt autovec pattern

Okay, I'll take a look at it right away. Thanks reporting. On 2023/9/6 16:17, Kito Cheng via Gcc-patches wrote: Got failed on the trunk, could you take a look? === gcc: Unexpected fails for rv32imafdc ilp32d medlow === FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-

Re: [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention

Pushed to trunk with few testcase modifications, e.g. adding { target { riscv_vector } } to dg-run and adding -march / -mabi for compile tests. On Tue, Sep 5, 2023 at 4:18 PM Kito Cheng wrote: > > Thanks for fixing the issue! I guess I could find time tonight to do > the final round review and te

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

Thanks for explaining, LGTM :) On Mon, Sep 4, 2023 at 11:39 PM Lehua Ding wrote: > > Hi Kito, > > > Can those intermediate patterns be used for intrinsic? I would prefer > > to keep those stuff *IF* possible used for intrinsics. > > I think we don't need those patterns for intrinisc. First, the

[PATCH 1/5] OpenMP, NVPTX: memcpy[23]D bias correction

This patch works around behaviour of the 2D and 3D memcpy operations in the CUDA driver runtime. Particularly in Fortran, the "base pointer" of an array (used for either source or destination of a host/device copy) may lie outside of data that is actually stored on the device. The fix is to make

[PATCH 0/5] OpenMP: Array-shaping operator and strided/rectangular 'target update' support

This patch series provides support for the OpenMP 5.0+ array-shaping operator and for strided/rectangular updates for 'target update' directives. Each of C, C++ and Fortran is supported (using existing base language syntax for the last). This series applies on top of the "infrastructure" support

[PATCH 2/5] OpenMP: Allow complete replacement of clause during map/to/from expansion

At present, map/to/from clauses on OpenMP "target" directives may be expanded into several mapping nodes if they describe array sections with pointer or reference bases, or similar. This patch allows the original clause to be replaced during that expansion, mostly by passing the list pointer to th

[PATCH 5/5] OpenMP: Noncontiguous "target update" for Fortran

This patch implements noncontiguous "target update" for Fortran. The existing middle end/runtime bits relating to C and C++ support are reused, with some small adjustments, e.g.: 1. The node used to map the OMP "array descriptor" (from omp-low.cc onwards) now uses the OMP_CLAUSE_SIZE field

[PATCH 4/5] OpenMP: Array shaping operator and strided "target update" for C

Following the similar support for C++, here is the C implementation for the OpenMP 5.0 array-shaping operator, and for strided and rectangular updates for "target update". Much of the implementation is shared with the C++ support added by the previous patch. Some details of parsing necessarily di

[PATCH 1/2] allow targets to check shrink-wrap-separate enabled or not

No functional changes but restructure and expose use_shrink_wrapping_separate to the TARGETs. gcc/ChangeLog: * shrink-wrap.cc (try_shrink_wrapping_separate):call use_shrink_wrapping_separate. (use_shrink_wrapping_separate): wrap the condition check in use_shrin

[PATCH 0/2] resolve confilct between zcmp multi push/pop and shrink-wrap-separate

Enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective. Fei Gao (2): allow targets to check shrink-wrap-separate enabled or not [V2][RISC-V] enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective gcc/config/riscv/riscv.cc | 21

[PATCH 2/2] [V2][RISC-V] enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective

So that zcmp can be enabled in -Os where shrink-wrap-separate is not effective. To force enabling zcmp multi push/pop in speed perfered case, fno-shrink-wrap-separate has to be explictly given. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_avoid_shrink_wrapping_separate): wrap t

Re: [PATCH v3] RISC-V: Add autovec FP binary operations.

Hi Robin, +# Return 1 if the we can build a vector example with proper -march flags +# and the current target can execute it, 0 otherwise. Cache the result. + +proc check_effective_target_riscv_vector_hw { } { + +return [check_runtime riscv_vector_hw32 { +int main (void) +{

[PATCH] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

This patch fix incorrect mode tieable between DI and V2SI which cause ICE in RA. PR target/111296 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: New test. --- gcc/config/riscv/r

[PATCH] OpenMP: Enable 'declare mapper' mappers for 'target update' directives

This patch enables use of 'declare mapper' for 'target update' directives, for each of C, C++ and Fortran. There are some implementation choices here and some "read-between-the-lines" consequences regarding this functionality, as follows: * It is possible to invoke a mapper which contains clause

[PATCH] LoongArch: Fix unintentional bash-ism in r14-3665.

gcc/ChangeLog: * config.gcc: remove non-POSIX syntax "<<<". --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index b2fe7c7ceef..6d4c8becd28 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -5189,7 +5189,7 @@ case "${

[PATCH] riscv: xtheadbb: Fix xtheadbb-li-rotr test for rv32

From: Christoph Müllner The test was introduced recently and tests a RV64-only feature. However, when testing an RV32 compiler, the test gets executed as well and fails with "cc1: error: ABI requires '-march=rv32'". This patch fixes this by adding '-mabi=lp64' (like it is done for other RV64-only

[PATCH] LoongArch: Link c++ header directory in the default ABI to the toplevel.

When multilib is enabled, the c++ header directory of the default multilib variant needs to be linked to the toplevel since g++ does not search the toplevel in this case. libstdc++-v3/ChangeLog: * configure.host: Register t-loongarch in tmake_file. * config/cpu/loongarch/t-loongar

Re: [PATCH] riscv: xtheadbb: Fix xtheadbb-li-rotr test for rv32

Committed as "obvious" to master. --Philipp. On Wed, 6 Sept 2023 at 12:04, Christoph Muellner < christoph.muell...@vrull.eu> wrote: > From: Christoph Müllner > > The test was introduced recently and tests a RV64-only feature. > However, when testing an RV32 compiler, the test gets executed as we

Re: [PATCH v5] c++: extend cold, hot attributes to classes

reminder: ready for commit? - Javier On Wed 23. Aug 2023 at 15:02, Javier Martinez < javier.martinez.bugzi...@gmail.com> wrote: > On Tue, Aug 22, 2023 at 7:50 PM Jason Merrill wrote: > > You still need an update to doc/extend.texi for this additional use of > > the attribute. Sorry I didn't th

Re: [PATCH] xtensa: Optimize boolean evaluation when SImode EQ/NE to zero if TARGET_MINMAX

On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa wrote: > On 2023/09/06 8:01, Max Filippov wrote: > > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa > > wrote: > >> ;; after (prereq. TARGET_MINMAX) > >> test0: > >> movi.n a9, 1 > >> minua2, a2,

Re: [PATCH] xtensa: Optimize boolean evaluation when SImode EQ/NE to zero if TARGET_MINMAX

On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa wrote: > > This patch optimizes the boolean evaluation for equality to 0 in SImode > using the MINU (Minimum Value Unsigned) machine instruction available > when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1) > and (x ==

Re: [PATCH] LoongArch: Link c++ header directory in the default ABI to the toplevel.

On Wed, 2023-09-06 at 18:06 +0800, Yang Yujie wrote: > When multilib is enabled, the c++ header directory of the default multilib > variant needs to be linked to the toplevel since g++ does not search the > toplevel in this case. > > libstdc++-v3/ChangeLog: > > * configure.host: Register

[PATCH v1 0/4] Add Loongson SX/ASX instruction support to LoongArch

In order to better test the function of the vector instruction, the 128 and 256 bit test cases are further split according to the function of the instruction. Xiaolong Chen (4): LoongArch: Add tests of -mstrict-align option. LoongArch: Add testsuite framework for Loongson SX/ASX. LoongArch:

[PATCH v1 1/4] LoongArch: Add tests of -mstrict-align option.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/strict-align.c: New test. --- gcc/testsuite/gcc.target/loongarch/strict-align.c | 13 + 1 file changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c diff --git a/gcc/testsuite/gcc.target

[PATCH v1 2/4] LoongArch: Add testsuite framework for Loongson SX/ASX.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/loongarch-vector.exp: New test. * gcc.target/loongarch/vector/simd_correctness_check.h: New test. --- .../loongarch/vector/loongarch-vector.exp | 42 +++ .../loongarch/vector/simd_correctness_check.h | 39 +

[PATCH v1 3/4] LoongArch: Add tests for Loongson SX builtin functions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test. --- .../loongarch/vector/lsx/lsx-builtin.c| 1461 + 1 file changed, 1461 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c diff --git a/

[PATCH] LoongArch: Use bstrins instruction for (a & ~mask) and (a & mask) | (b & ~mask) [PR111252]

If mask is a constant with value ((1 << N) - 1) << M we can perform this optimization. gcc/ChangeLog: PR target/111252 * config/loongarch/loongarch-protos.h (loongarch_pre_reload_split): Declare new function. (loongarch_use_bstrins_for_ior_with_mask): Likewise.

Re: [PATCH v1 4/4] LoongArch: Add tests for Loongson SX floating-point conversion instructions.

On Wed, 2023-09-06 at 18:45 +0800, Xiaolong Chen wrote: > +  *((int*)& __m128_op0[3]) = 0x004200a0; > +  *((int*)& __m128_op0[2]) = 0x; > +  *((int*)& __m128_op0[1]) = 0x004200a0; > +  *((int*)& __m128_op0[0]) = 0x0021; These are aliasing rule violation and they will suddenly blow up w

Re: [PATCH] LoongArch: Use bstrins instruction for (a & ~mask) and (a & mask) | (b & ~mask) [PR111252]

Forgot to mention: I've bootstrapped and regtested this patch on loongarch64-linux-gnu (with PR110939 patch applied to unbreak the bootstrapping). Ok for trunk? On Wed, 2023-09-06 at 18:46 +0800, Xi Ruoyao wrote: > If mask is a constant with value ((1 << N) - 1) << M we can perform this > optimi

Re: [PATCH] LoongArch: Fix unintentional bash-ism in r14-3665.

Yang Yujie writes: > gcc/ChangeLog: > > * config.gcc: remove non-POSIX syntax "<<<". > --- Thanks, I was just about to report this. > gcc/config.gcc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config.gcc b/gcc/config.gcc > index b2fe7c7ceef..6d4c8becd28

Re: [PATCH v1 1/4] LoongArch: Add tests of -mstrict-align option.

On Wed, 2023-09-06 at 18:43 +0800, Xiaolong Chen wrote: > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/strict-align.c: New test. A question: is there really a CPU model with LSX/LASX but without unaligned access support? If not I think we'd just reject -mstrict- align -mlsx. Curr

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

Committed, thanks Kito. -- Best, Lehua

Re: [PATCH] fwprop: Allow UNARY_P and check register pressure.

Hi Richard, I did some testing with the attached v2 that does not restrict to UNARY anymore. As feared ;) there is some more fallout that I'm detailing below. On Power there is one guality fail (pr43051-1.c) that I would take the liberty of ignoring for now. On x86 there are four fails: - con

Re: [RFC] GCC Security policy

Hello folks, Here's v3 of the top part of the security policy. Hopefully this addresses all concerns raised so far. Thanks, Sid What is a GCC security bug? === A security bug is one that threatens the security of a system or network, or might compromise the

[PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

Previously, I add TARGET_64BIT condtion to block VLS modes with size = 64bit in RV32 system E.g. V8QI Since I realized such modes may cause inferior codegen for some situations in RV32 system. However, this is really quite ugly and it cause ICE for some cases in RV32: FAIL: gcc.target/riscv/r

Re: [PATCH] LoongArch: Fix unintentional bash-ism in r14-3665.

Yang Yujie writes: > gcc/ChangeLog: > > * config.gcc: remove non-POSIX syntax "<<<". OK. Thanks for the quick fix. Richard. > --- > gcc/config.gcc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config.gcc b/gcc/config.gcc > index b2fe7c7ceef..6d4c8becd28 10

[PATCH] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]

Fix bugzilla: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295 PR target/111295 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (insert_vsetvl): gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr111295.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc

[PATCH 1/2] ARC: Use intrinsics for __builtin_add_overflow*()

This patch covers signed and unsigned additions. The generated code would be something along these lines: signed: add.f r0, r1, r2 b.v @label unsigned: add.f r0, r1, r2 b.c @label gcc/ChangeLog: * config/arc/arc-modes.def: Add CC_V mode. * config/arc/predica

[PATCH 2/2] ARC: Use intrinsics for __builtin_sub_overflow*()

This patch covers signed and unsigned subtractions. The generated code would be something along these lines: signed: sub.f r0, r1, r2 b.v @label unsigned: sub.f r0, r1, r2 b.c @label gcc/ChangeLog: * config/arc/arc.md (subsi3_v): New insn. (subvsi4): New exp

[PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case

From: Pan Li Put the test file to the incorrect folder, this patch would like to fix it. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: Moved to... * gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: ...here. Signed-off-by: Pan Li --- .../gcc.targ

RE: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case

Committed, thanks Juzhe and sorry for my silly mistake. Pan From: juzhe.zhong Sent: Wednesday, September 6, 2023 8:53 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case lg

Re: [PATCH V2] RISC-V: Support Dynamic LMUL Cost model

Hi Juzhe, general remark upfront: Please add function-level comments for all functions. This makes reading and reviewing much easier. I had to sweep back and forth quite a bit. > + > +static int > +get_last_live_range (const vec &live_ranges, tree var) > +{ > + unsigned int ix; > + var_live_

Re: [PATCH v3] RISC-V: Add autovec FP binary operations.

Hi Lehua, > May I ask if the compiler options "-march=rv64gcv_zvfh -mabi=lp64d" > should be removed? Because we don't specify -march and -mabi when we > run testcase (so but why we need to specify the -march and -mabi in > this target check?), we run it with the default values. Assuming that > t

Re: [PATCH] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]

OK. Regards Robin

Re: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

LGTM. Regards Robin

[PATCH] ggc, jit: forcibly clear GTY roots in jit

As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he noticed an ICE inside libgccjit when compiling certain rust files. Debugging libgccjit showed that outdated information from a previous in-memory compile was referring to ad-hoc locations in the previous compile's line_table. The

[pushed] analyzer: add ctxt to fill_region/zero_fill_region

I noticed that region_model's fill_region/zero_fill_region member functions weren't checking that the write to the region was valid. Fixed thusly. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3739-gb923978a6ec447. gcc/analyzer/ChangeLog: * kf.cc (

[pushed] analyzer: implement kf_strncpy [PR105899]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3740-gb51cde34d4e750. gcc/analyzer/ChangeLog: PR analyzer/105899 * kf.cc (class kf_strncpy): New. (kf_strncpy::impl_call_post): New. (register_known_functions): Register it.

[pushed] analyzer: implement kf_strstr [PR105899]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3741-gf2d7a4001a3388. gcc/analyzer/ChangeLog: PR analyzer/105899 * kf.cc (class kf_strstr): New. (kf_strstr::impl_call_post): New. (register_known_functions): Register it. gcc/tes

[PATCHSET] Add error metadata to diagnostics

This short patchset from David Malcolm enables errors to contain extra metadata - this is particularly useful for the Rust frontend, which will rely on that implementation to emit standard Rust error codes [1]. This series of patches is necessary for much of our more recent additions to the fronte

[PATCH 1/2] diagnostics: add error_meta

From: David Malcolm --- gcc/diagnostic-core.h | 3 +++ gcc/diagnostic.cc | 15 +++ 2 files changed, 18 insertions(+) diff --git a/gcc/diagnostic-core.h b/gcc/diagnostic-core.h index 7334c79e8e6..c9e27fd2e6e 100644 --- a/gcc/diagnostic-core.h +++ b/gcc/diagnostic-core.h @@ -92,6

[PATCH 2/2] Experiment with adding an error code to an error

From: David Malcolm --- gcc/rust/rust-diagnostics.cc | 11 +++ gcc/rust/rust-diagnostics.h | 18 ++ gcc/rust/rust-gcc-diagnostics.cc | 33 +++ gcc/rust/typecheck/rust-casts.cc | 2 +- .../rust/compile/bad_a

Re: [PATCH] analyzer: Move gcc.dg/analyzer tests to c-c++-common (2) [PR96395]

Hi David, Thanks for the review. On Tue, Sep 5, 2023 at 1:53 PM David Malcolm wrote: > On Mon, 2023-09-04 at 20:00 +0200, priour...@gmail.com wrote: > > [...snip...] > All of these "new" tests (apart from the "-noexcept" ones) look like > they're meant to be existing tests that were moved, b

Re: [PATCH] ggc, jit: forcibly clear GTY roots in jit

Hi. I'll do another test to make sure this is enough since I tested with a few more finalize functions. Thanks a lot for finding this! On Wed, 2023-09-06 at 09:40 -0400, David Malcolm via Jit wrote: > As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he > noticed an ICE inside libgc

RE: [PATCH] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Wednesday, September 6, 2023 9:38 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS AVL

RE: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Wednesday, September 6, 2023 9:39 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Remove unreasonable

Re: [PATCH] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

On 9/6/23 03:47, Juzhe-Zhong wrote: This patch fix incorrect mode tieable between DI and V2SI which cause ICE in RA. PR target/111296 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111

Re: [PATCH v4 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

On 9/5/23 23:47, Tsukasa OI wrote: From: Tsukasa OI 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard

Re: [PATCH 1/2] diagnostics: add error_meta

On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote: > From: David Malcolm I guess I can review this patch :) Needs a ChangeLog entry, so here's one: gcc/ChangeLog * diagnostic-core.h (error_meta): New decl. * diagnostic.cc (error_meta): New. Also, needs a signed-off-by, so h

Re: [PATCH 2/2] Experiment with adding an error code to an error

On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote: > From: David Malcolm This is probably something for the gcc-rust maintainers to review (rather than me self-reviewing with my "diagnostics maintainer" hat on). Doesn't have a ChangeLog entry, FWIW. Doesn't have a signed-off-by, so here's on

Re: [PATCH 1/2] diagnostics: add error_meta

On 9/6/23 16:12, David Malcolm wrote: On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote: From: David Malcolm I guess I can review this patch :) Needs a ChangeLog entry, so here's one: gcc/ChangeLog * diagnostic-core.h (error_meta): New decl. * diagnostic.cc (error_meta):

[Committed V2] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

This patch fix incorrect mode tieable between DI and V2SI which cause ICE in RA. PR target/111296 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode tieable for RVV modes. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C:

Re: [PATCH] core: Support heap-based trampolines

Hi, ping**2 on the revised patch, for Richard or another global reviewer. So far all review feedback is that it’s a step forward, and it’s been widely used for both aarch64-darwin and x86_64-darwin distributions for almost three years now. OK to commit? FX > Le 5 août 2023 à 16:20, FX Couder

[committed 10/12 v2] C _BitInt support [PR102989]

Hi! Thanks for the patch reviews (and to Richi and Uros as well) and everyone who participated in discussions. Here is the updated version of the C _BitInt support [PR102989] patch I've committed to trunk in addition to the rest of the series (except the _BitInt a ? ~b : b match.pd fix patch, whi

[PATCH v2 0/2] riscv: Introduce strlen/strcmp/strncmp inline expansion

From: Christoph Müllner This series introduces strlen/strcmp/strncmp inline expansion for Zbb/XTheadBb. In the last months, glibc as well as the Linux kernel merged changes for optimized string processing for RISC-V. The instruction, which enables optimized string routines is Zbb's orc.b (or T-H

[PATCH v2 2/2] riscv: Add support for str(n)cmp inline expansion

From: Christoph Müllner This patch implements expansions for the cmpstrsi and cmpstrnsi builtins for RV32/RV64 for xlen-aligned strings if Zbb or XTheadBb instructions are available. The expansion basically emits a comparison sequence which compares XLEN bits per step if possible. This allows t

[PATCH v2 1/2] riscv: Add support for strlen inline expansion

From: Christoph Müllner This patch implements the expansion of the strlen builtin for RV32/RV64 for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available. The inserted sequences are: rv32gc_zbb (RV64 is similar): add a3,a0,4 li a4,-1 .L1: lw a5,0(a

[committed 19/12] Additional _BitInt test coverage [PR102989]

On Tue, Sep 05, 2023 at 10:40:26PM +, Joseph Myers wrote: > Additional tests I think should be added (for things I expect should > already work): > > * Tests for BITINT_MAXWIDTH in . Test that it's defined for > C2x, but not defined for C11/C17 (the latter independent of whether the > targ

Re: [PATCH v2 1/2] riscv: Add support for strlen inline expansion

On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu wrote: From: Christoph Müllner This patch implements the expansion of the strlen builtin for RV32/RV64 for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available. The inserted sequences are: rv32gc_zbb (R

Re: [PATCH v2 1/2] riscv: Add support for strlen inline expansion

On 9/6/23 10:22, Palmer Dabbelt wrote: On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu wrote: From: Christoph Müllner This patch implements the expansion of the strlen builtin for RV32/RV64 for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available

[PATCH 0/5] RISC-V: Add Types to Untyped Instructions

This series adds types to the remaining untyped instructions. Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ Also enables assert which checks to make sure every instruction has a type All patches were tested with rv32/rv64 linux/newli

[PATCH 1/5] RISC-V: Update Types for Vector Instructions

This patch adds types to vector instructions that were added after or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html gcc/ChangeLog: * config/riscv/autovec-opt.md: Update types * config/riscv/autovec.md: likewise Signed-off-by:

[PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

This patch adds types to the untyped zc instructions. Creates a new type "csr" for these instructions for now. gcc/ChangeLog: * config/riscv/riscv.md: Add "csr" type * config/riscv/zc.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 3 +- gcc/config/ri

[PATCH 4/5] RISC-V: Update Types for RISC-V Instructions

This patch adds types to riscv instructions that were added or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html gcc/ChangeLog: * config/riscv/riscv.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 3 +++ 1 file

[PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions

This patch creates a new "zicond" type and updates all zicond instructions with that type. gcc/ChangeLog: * config/riscv/riscv.md: Add "zicond" type * config/riscv/zicond.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 5 +++-- gcc/config/riscv/zicond.

[PATCH 5/5] RISC-V: Remove Assert Protecting Types

This patch turns on the assert which ensures every instruction has type that is not TYPE_UNKNOWN. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.cc | 2 -- 1 file changed, 2 deletions(-) diff --git

libgo patch committed: permit $AR to include options

This libgo patch changes the go tool to permit the AR environment variable to include options. This mirrors the way it already handles the CC environment variable. This ports https://go.dev/cl/526275 to the gofrontend repo. This is needed for gccgo testing because the top-level GCC Makefile now

Re: [PATCH v2 1/2] riscv: Add support for strlen inline expansion

On Wed, 06 Sep 2023 09:47:05 PDT (-0700), jeffreya...@gmail.com wrote: On 9/6/23 10:22, Palmer Dabbelt wrote: On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu wrote: From: Christoph Müllner This patch implements the expansion of the strlen builtin for RV32/RV64 for xlen

[PATCH v2] analyzer: Call off a superseding when diagnostics are unrelated [PR110830]

From: benjamin priour Hi, Second version of this patch after David's suggestions. Thanks David for pointing out how I could implement it using sedges. I hadn't thought of them being independent of the exploded path taken, and unique for a conditional block's outcome. I had mistaken them with eed

Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class

On 9/1/23 05:07, Hongyu Wang wrote: Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道： On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add insn argument to base_reg_class for

Re: [PATCH] analyzer: Move gcc.dg/analyzer tests to c-c++-common (2) [PR96395]

On Wed, 2023-09-06 at 15:50 +0200, Benjamin Priour wrote: > Hi David, > Thanks for the review. > > > > On Tue, Sep 5, 2023 at 1:53 PM David Malcolm > wrote: > > > On Mon, 2023-09-04 at 20:00 +0200, priour...@gmail.com wrote: > > > > > [...snip...] > > > > All of these "new" tests (apart fr

Re: [PATCH v2] analyzer: Call off a superseding when diagnostics are unrelated [PR110830]

On Wed, 2023-09-06 at 21:16 +0200, priour...@gmail.com wrote: [...snip...] > Signed-off-by: benjamin priour > Co-authored-by: david malcolm Please also add: Signed-off-by: David Malcolm [...snip...] > > +static bool > +compatible_epath_p (const exploded_path *lhs_path, > +  

Re: [PATCH] fwprop: Allow UNARY_P and check register pressure.

Robin Dapp writes: > Hi Richard, > > I did some testing with the attached v2 that does not restrict to UNARY > anymore. As feared ;) there is some more fallout that I'm detailing below. > > On Power there is one guality fail (pr43051-1.c) that I would take > the liberty of ignoring for now. > > O

Re: [C PATCH 1/6] c: reorganize recursive type checking

On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote: > -static int > +static bool > comp_target_types (location_t location, tree ttl, tree ttr) The comment above this function should be updated to refer to returning true, not to returning 1. And other comments on common_pointer_type and

Re: [PATCH] c++: refine CWG 2369 satisfaction vs non-dep convs [PR99599]

On Mon, 28 Aug 2023, Jason Merrill wrote: > On 8/24/23 09:31, Patrick Palka wrote: > > On Wed, 23 Aug 2023, Jason Merrill wrote: > > > > > On 8/21/23 21:51, Patrick Palka wrote: > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like > > > > a reasonable approach? I did

[PATCH] c++: cache conversion function lookup

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? This cache apparently has a 98% hit rate for TYPE_HAS_CONVERSION types on some test files. -- >8 -- gcc/cp/ChangeLog: * config-lang.in (gtfiles): Add search.cc. * search.cc (lookup_conversions_cache)

Re: [PATCH] c++: refine CWG 2369 satisfaction vs non-dep convs [PR99599]

On Mon, 28 Aug 2023, Jason Merrill wrote: > On 8/24/23 09:31, Patrick Palka wrote: > > On Wed, 23 Aug 2023, Jason Merrill wrote: > > > > > On 8/21/23 21:51, Patrick Palka wrote: > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like > > > > a reasonable approach? I didn't

[committed] libstdc++: Disable support by default for freestanding

Tested x86_64-linux and x86_64-elf. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ENABLE_BACKTRACE): Disable by default for freestanding. * configure: Regenerate. --- libstdc++-v3/acinclude.m4 | 2 +- libstdc++-v3/configure| 2 +- 2 files

Re: [RFC] libstdc++: Make --enable-libstdcxx-backtrace=auto default to yes

On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote: > > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++ > wrote: > > > > > Date: Fri, 1 Sep 2023 12:16:40 +0100 > > > Reply-To: Jonathan Wakely > > > > > > On Wed, 23 Aug 2023 at 17:03, Jonathan Wakely via Libstdc++ > > > wrote: >

godump.cc patch committed: Handle _BitInt

This patch to godump.cc adds support for BITINT_TYPE. Bootstrapped and ran godump and Go tests on x86_64-pc-linux-gnu. Committed to mainline. Ian gcc/ PR go/111310 * godump.cc (go_format_type): Handle BITINT_TYPE. gcc/testsuite/ PR go/111310 * gcc

Re: [RFC] libstdc++: Make --enable-libstdcxx-backtrace=auto default to yes

> From: Jonathan Wakely > Date: Wed, 6 Sep 2023 23:30:08 +0100 > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote: > > > > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++ > > wrote: > > > > > > > Date: Fri, 1 Sep 2023 12:16:40 +0100 > > > > Reply-To: Jonathan Wakely > > > > >

Re: [RFC] libstdc++: Make --enable-libstdcxx-backtrace=auto default to yes

On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote: > > > From: Jonathan Wakely > > Date: Wed, 6 Sep 2023 23:30:08 +0100 > > > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote: > > > > > > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++ > > > wrote: > > > > > > > > > Date:

Re: [RFC] libstdc++: Make --enable-libstdcxx-backtrace=auto default to yes

On Thu, 7 Sept 2023 at 00:10, Jonathan Wakely wrote: > > On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote: > > > > > From: Jonathan Wakely > > > Date: Wed, 6 Sep 2023 23:30:08 +0100 > > > > > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely > > > wrote: > > > > > > > > On Mon, 4 Sept 2023 a

Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions

LGTM Edwin Lu 於 2023年9月7日 週四 01:53 寫道： > This patch creates a new "zicond" type and updates all zicond instructions > with that type. > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add "zicond" type > * config/riscv/zicond.md: Update types > > Signed-off-by: Edwin Lu > --- > g

Re: [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions

LGTM Edwin Lu 於 2023年9月7日 週四 01:52 寫道： > This patch adds types to riscv instructions that were added or were > missed by the original patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html > > gcc/ChangeLog: > > * config/riscv/riscv.md: Update types > > Signed-off-by:

Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions

LGTM Edwin Lu 於 2023年9月7日 週四 01:51 寫道： > This patch adds types to vector instructions that were added after or were > missed by the original patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Update types >

Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

csr is kind of confusing, I would suggest something like `pushpop` and `mvpair`. Edwin Lu 於 2023年9月7日 週四 01:51 寫道： > This patch adds types to the untyped zc instructions. Creates a new > type "csr" for these instructions for now. > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add "csr"

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