Brief version history of patch set:
v1 -> v2:
According to the GNU code specification, adjust the format of the
function implementation with "q" as the suffix function.
v2 - >v3:
1.On the LoongArch architecture, refer to the functionality of 64-bit
functions
and modify the underlying impl
On Thu, 31 Aug 2023, Jiang, Haochen wrote:
> On Linux/x86_64,
>
> caa7a99a052929d5970677c5b639e1fa5166e334 is the first bad commit
> commit caa7a99a052929d5970677c5b639e1fa5166e334
> Author: Richard Biener
> Date: Wed Aug 30 11:57:47 2023 +0200
>
> tree-optimization/111228 - combine two V
Hi!
As the following testcase shows, while check_local_shadow diagnoses most of
the [basic.scope.block]/2 violations, it doesn't diagnose when parameter's
name is redeclared inside of the compound-stmt of a function-try-block.
There is in that case an extra scope (sk_try with parent artificial
sk
On Thu, Aug 31, 2023 at 11:14:13AM +0800, Yujie Yang wrote:
> On Wed, Aug 30, 2023 at 09:36:22PM +, Joseph Myers wrote:
> > On Wed, 30 Aug 2023, Yang Yujie wrote:
> >
> > > +A suffix @code{[/ARCH][/OPTION]...]} may follow immediately after the ABI
> > > +identifier to customize the compiler op
Thanks for the cleanup, the new interface is really much simpler than before!
Only few minor comment, you can go ahead to commit that after address
those comment.
(OK, I don't want to review whole patch again, it's really huge change :P
>
> - void set_rounding_mode (enum floating_point_rounding
On Thu, 2023-08-31 at 15:02 +0800, chenxiaolong wrote:
> +;; Implement __builtin_copysignf128 function.
> +
> +(define_insn_and_split "copysigntf3"
> + [(set (match_operand:TF 0 "register_operand" "=&r")
> + (unspec:TF [(match_operand:TF 1 "register_operand" "r")
> + (match
On Wed, Aug 30, 2023 at 8:18 PM Richard Biener via Gcc-patches
wrote:
>
> On Wed, Aug 30, 2023 at 12:38 PM liuhongt via Gcc-patches
> wrote:
> >
> > r14-332-g24905a4bd1375c adjusts costing of emulated vectorized
> > gather/scatter.
> >
> > commit 24905a4bd1375ccd99c02510b9f9529015a48315
> >
Hi!
C++17 had in [basic.block.scope]/2
"A parameter name shall not be redeclared in the outermost block of the function
definition nor in the outermost block of any handler associated with a
function-try-block."
and in [basic.block.scope]/4 similar rule for selection/iteration
statements. My read
Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
* doc/tm.texi: Document INSN_INDEX_REG_CLASS.
Intel Advanced performance extension (APX) has been released in [1].
It contains several extensions such as extended 16 general purpose registers
(EGPRs), push2/pop2, new data destination (NDD), conditional compare
(CCMP/CTEST) combined with suppress flags write version of common instructions
(NF).
From: Kong Lingling
In inline asm, we do not know if the insn can use EGPR, so disable EGPR
usage by default from mapping the common reg/mem constraint to non-EGPR
constraints. Use a flag mapx-inline-asm-use-gpr32 to enable EGPR usage
for inline asm.
gcc/ChangeLog:
* config/i386/i386.cc
From: Kong Lingling
Add -mapx-features= enumeration to separate subfeatures of APX_F.
-mapxf is treated same as previous ISA flag, while it sets
-mapx-features=apx_all that enables all subfeatures.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.
(XCR_APX
For vector move insns like vmovdqa/vmovdqu, their evex counterparts
requrire explicit suffix 64/32/16/8. The usage of these instruction
are prohibited under AVX10_1 or AVX512F, so for AVX2+APX_F we select
vmovaps/vmovups for vector load/store insns that contains EGPR.
gcc/ChangeLog:
* con
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add insn argument to base_reg_class for
lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argument.
Pass to MODE_CODE_BASE_REG_CLASS.
(r
From: Kong Lingling
For APX, as we extended the GENERAL_REG_CLASS, new constraints are
needed to restrict insns that cannot adopt EGPR either in its reg or
memory operands.
gcc/ChangeLog:
* config/i386/constraints.md (h): New register constraint
for GENERAL_GPR16.
(Bt):
From: Kong Lingling
Add backend helper functions to verify if a rtx_insn can adopt EGPR to
its base/index reg of memory operand. The verification rule goes like
1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32.
2. Disable EGPR for unrecognized insn.
3. If which_alternat
From: Kong Lingling
Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
but no evex counterpart.
insn list:
1. phminposuw/vphminposuw
2. ptest/vptest
3. roundps/vroundps, roundpd/vroundpd,
roundss/vroundss, roundsd/vroundsd
4. pcmpestri/vpcmpestri, pcmpestrm/vpcmpestrm
5.
From: Kong Lingling
Extend GENERAL_REGS with extra r16-r31 registers like REX registers,
named as REX2 registers. They will only be enabled under
TARGET_APX_EGPR.
gcc/ChangeLog:
* config/i386/i386-protos.h (x86_extended_rex2reg_mentioned_p):
New function prototype.
* con
From: Kong Lingling
These legacy insn in opcode map0/1 only support GPR16,
and do not have vex/evex counterpart, directly adjust constraints and
add gpr32 attr to patterns.
insn list:
1. xsave/xsave64, xrstor/xrstor64
2. xsaves/xsaves64, xrstors/xrstors64
3. xsavec/xsavec64
4. xsaveopt/xsaveopt6
From: Kong Lingling
These legacy insns in opcode map2/3 have vex but no evex
counterpart, disable EGPR for them by adjusting alternatives and
attr_gpr32.
insn list:
1. phaddw/vphaddw, phaddd/vphaddd, phaddsw/vphaddsw
2. phsubw/vphsubw, phsubd/vphsubd, phsubsw/vphsubsw
3. psignb/vpsginb, psignw/v
From: Kong Lingling
The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns
with evex counterpart, we assume auto promotion to EGPR under APX_F if the
insn uses GPR32. So for below insns, we disabled EGPR usage for their sse
mnenomics, while allowing egpr generation of their
From: Kong Lingling
These vex insn may have legacy counterpart that could support EGPR,
but they do not have evex counterpart. Split out its vex part from
patterns and set the vex part to non-EGPR supported by adjusting
constraints and attr_gpr32.
insn list:
1. vmovmskpd/vmovmskps
2. vpmovmskb
3
在 2023-08-31四的 15:57 +0800，Xi Ruoyao写道：
> On Thu, 2023-08-31 at 15:02 +0800, chenxiaolong wrote:
> > +;; Implement __builtin_copysignf128 function.
> > +
> > +(define_insn_and_split "copysigntf3"
> > + [(set (match_operand:TF 0 "register_operand" "=&r")
> > + (unspec:TF [(match_operand:TF 1
On Thu, Aug 31, 2023 at 06:02:36AM +, waffl3x via Gcc-patches wrote:
> From e485a79ec5656e72ba46053618843c3d69331eab Mon Sep 17 00:00:00 2001
> From: Waffl3x
> Date: Thu, 31 Aug 2023 01:05:25 -0400
> Subject: [PATCH] P0847R7 (deducing this) Initial support
>
> Most things should be functiona
On Thu, Aug 31, 2023 at 10:06 AM Hongtao Liu wrote:
>
> On Wed, Aug 30, 2023 at 8:18 PM Richard Biener via Gcc-patches
> wrote:
> >
> > On Wed, Aug 30, 2023 at 12:38 PM liuhongt via Gcc-patches
> > wrote:
> > >
> > > r14-332-g24905a4bd1375c adjusts costing of emulated vectorized
> > > gather/sca
Committed after addressing these comments.
Many thanks to Kito for taking the time to review such a large patch :)
On 2023/8/31 15:51, Kito Cheng wrote:
Thanks for the cleanup, the new interface is really much simpler than before!
Only few minor comment, you can go ahead to commit that after ad
We only emit that on linux target before, that not problem before,
however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
that will cause problem when we test baremetal with qemu.
So the straightforward is enable that as well for non-linux toolchian,
the price is that will increa
This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now returned, allowing change to agnostic
or undisturbed. In the future, users may be able to control the default
policy, such as keeping agnosti
This is an update of:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628303.html
Changes since last version of patch set:
- "dg-skip-if"-related Changes of the g++.dg/torture/vshuf* testcases are
reverted.
(Replaced by __builtin_shuffle fix)
- Add fix of __builtin_shuffle() for Loongson
Hi Tsukasa:
I guess you might did something wrong during commit this patch and
"RISC-V: Add stub support for existing extensions"
https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
On Tue, Aug 29, 2023 at 4:55 PM Tsukasa OI via Gcc-patches
wrote:
>
> On 2023/08/29
On 2023/08/31 18:10, Kito Cheng wrote:
> Hi Tsukasa:
>
> I guess you might did something wrong during commit this patch and
> "RISC-V: Add stub support for existing extensions"
>
> https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
>
It's fine. That patch was a p
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
>
> This patch change the vsetvl policy to default policy
> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
> fixed policy. Any policy is now returned, allowing change to agnostic
> or undisturbed. In the future, users
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some high-level comments.
One thing I noticed is the overloading of "MASK_OP", we use it as
Ok, I just went through the patchlist and found this patch seems
not committed yet, anyway I will mark this as commit now :)
On Thu, Aug 31, 2023 at 5:14 PM Tsukasa OI via Gcc-patches
wrote:
>
> On 2023/08/31 18:10, Kito Cheng wrote:
> > Hi Tsukasa:
> >
> > I guess you might did something wrong
On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> From: Kong Lingling
>
> In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> usage by default from mapping the common reg/mem constraint to non-EGPR
> constraints. Use a flag mapx-inline-asm-use-gp
On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches
wrote:
>
> Intel Advanced performance extension (APX) has been released in [1].
> It contains several extensions such as extended 16 general purpose registers
> (EGPRs), push2/pop2, new data destination (NDD), conditional compare
> (CCMP
On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
wrote:
>
> From: Kong Lingling
>
> Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> but no evex counterpart.
>
> insn list:
> 1. phminposuw/vphminposuw
> 2. ptest/vptest
> 3. roundps/vroundps, roundpd/vroundpd,
On Thu, Aug 31, 2023 at 11:26 AM Richard Biener
wrote:
>
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> > 1. phm
On Thu, Aug 31, 2023 at 11:26:26AM +0200, Richard Biener wrote:
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> >
On Thu, 2023-08-31 at 17:08 +0800, Chenghui Pan wrote:
> This is an update of:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628303.html
>
> Changes since last version of patch set:
> - "dg-skip-if"-related Changes of the g++.dg/torture/vshuf* testcases are
> reverted.
> (Replaced by
On Thu, Aug 31, 2023 at 04:20:19PM +0800, Hongyu Wang via Gcc-patches wrote:
> For vector move insns like vmovdqa/vmovdqu, their evex counterparts
> requrire explicit suffix 64/32/16/8. The usage of these instruction
> are prohibited under AVX10_1 or AVX512F, so for AVX2+APX_F we select
> vmovaps/v
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
>
> Because functions which follow vector calling convention variant has
> callee-saved vector reigsters but functions which follow stand
Hi Robin,
Thanks for these comments.
On 2023/8/31 17:16, Robin Dapp wrote:
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some high-level
On Thu, Aug 31, 2023 at 11:18 AM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> > From: Kong Lingling
> >
> > In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> > usage by default from mapping the comm
Hi,
on some targets we fail to vectorize with the first type the vectorizer
tries but succeed with the second. This patch changes several regex
patterns to reflect that behavior.
Before we would look for a single occurrence of e.g.
"vect_recog_dot_prod_pattern" but would possible find two (one f
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> These legacy insn in opcode map0/1 only support GPR16,
> and do not have vex/evex counterpart, directly adjust constraints and
> add gpr32 attr to patterns.
>
> insn list:
> 1. xsave/xsave64, xrstor/xrstor64
> 2. xsav
Thanks for the testing work! I will continue to try to find and resolve
some subtle issues too (Such as use compiler to compile some large
project). I'm also curious about the partly saved register problem and
will take some learning and investigation in the future.
On Thu, 2023-08-31 at 17:41 +08
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> Current reload infrastructure does not support selective base_reg_class
> for backend insn. Add insn argument to base_reg_class for
> lra/reload usage.
I don't think this is the correct approach. Ideally, a memory
co
The testcase requires hardware support for V2DImode vectors because
otherwise we do not rewrite inserts via BIT_FIELD_REF to
BIT_INSERT_EXPR. There's no effective target for this so the
following makes the testcase x86 specific, requiring and enabling SSE2.
Pushed.
* gcc.dg/tree-ssa/forw
Committed, thanks Kito.
On 2023/8/31 17:13, Kito Cheng via Gcc-patches wrote:
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now r
This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It is
not a global replacement though, and each use was audited.
- When referring to specific versions that used the “OS X” or “Mac OS” as their
Before optimization, the operation of taking fixed-point numbers from memory
and then forcing type conversion needs to be loaded into fixed-point registers
before conversion. After the optimization is completed, the fixed-point value
is directly transferred to the floating-point register for type c
On Thu, 31 Aug 2023, Robin Dapp wrote:
> Hi,
>
> on some targets we fail to vectorize with the first type the vectorizer
> tries but succeed with the second. This patch changes several regex
> patterns to reflect that behavior.
>
> Before we would look for a single occurrence of e.g.
> "vect_re
> The most obvious places would be right after SSA construction and before RTL
> expansion.
> Can you provide measurements for those positions?
The algorithm should only remove PHIs that break SSA form minimality. Since
GCC's SSA construction already produces minimal SSA form, the algorithm isn't
Hi FX,
+Sandra
> On 31 Aug 2023, at 12:13, FX Coudert wrote:
>
> This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
> OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It
> is not a global replacement though, and each use was audited.
>
> -
This patch removes zero extension from vctzlsbb as it already zero extends.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
al
This patch removes zero extension from vctzlsbb as it already zero extends.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
alre
On Thu, Aug 31, 2023 at 01:26:37PM +0200, Filip Kastl wrote:
> Regarding debug info coverage: I didn't notice any additional guality
> testcases
> failing after I applied the patch. *Is there any other way how I should check
> debug info coverage?*
I'm usually using https://github.com/pmachata/dw
On Thu, 31 Aug 2023, Filip Kastl wrote:
> > The most obvious places would be right after SSA construction and before
> > RTL expansion.
> > Can you provide measurements for those positions?
>
> The algorithm should only remove PHIs that break SSA form minimality. Since
> GCC's SSA construction a
On Thu, Aug 31, 2023 at 12:27 AM Andrew Pinski via Gcc-patches
wrote:
>
> This simple patch extends the min_value/max_value match to vector integer
> types.
> Using uniform_integer_cst_p makes this easy.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
>
> The testcases pr
Hi, currently RVV vectorization only support picking LMUL according to
compile option --param=riscv-autovec-lmul= which is no ideal.
Compiler should be able to pick optimal LMUL/vectorization factor to
vectorize the loop according to the loop_vec_info and SSA-based register
pressure analysis.
Now
On Wed, Aug 30, 2023 at 11:33 AM Di Zhao OS
wrote:
>
> Hello Richard,
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Tuesday, August 29, 2023 7:11 PM
> > To: Di Zhao OS
> > Cc: Jeff Law ; Martin Jambor ; gcc-
> > patc...@gcc.gnu.org
> > Subject: Re: [PATCH] [tree-optimizatio
V4 change: Rebasing.
Hi RISC-V folks,
This patch implement the proposal of RISC-V vector calling convention[1] and
this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
all vector type arguments and return values are pass by reference. With this
patch, these arguments and r
I post the vector register calling convention rules from in the proposal[1]
directly here:
v0 is used to pass the first vector mask argument to a function, and to return
vector mask result from a function. v8-v23 are used to pass vector data
arguments, vector tuple arguments and the rest vector ma
Because functions which follow vector calling convention variant has
callee-saved vector reigsters but functions which follow standard calling
convention don't have. We need to distinguish which function callee is so that
we can tell GCC exactly which vector registers callee will clobber. So I enco
Functions which follow vector calling convention variant need be annotated by
.variant_cc directive according the RISC-V Assembly Programmer's Manual[1] and
RISC-V ELF Specification[2].
[1]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
[2]
https://github.c
Sorry for that, rebased and send V4 patch, thanks.
On 2023/8/31 17:50, Kito Cheng via Gcc-patches wrote:
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
Because functions which fol
On Tue, Aug 8, 2023 at 1:23 PM Jonathan Wakely wrote:
>
>
>
> On Wed, 19 Jul 2023 at 20:33, Ken Matsui via Libstdc++
> wrote:
>>
>> This patch defines _GLIBCXX_HAS_BUILTIN_TRAIT macro, which will be used
>> as a flag to toggle the use of built-in traits in the type_traits header
>> through _GLIB
OK. As it doesn't do anything and we'll be needing it anyway no harm
in adding it.
Regards
Robin
The following keeps dumping SSA def stmt RHS during diagnostic
reporting only for gimple_assign_single_p defs which means
memory loads. This avoids diagnostics containing PHI nodes
like
warning: 'realloc' called on pointer '*_42 = PHI .t_mem_caches' with nonzero offset 40
instead getting back
LGTM, Awesome!! It seems a sign of the next big move for RISC-V vectorization!
On Thu, Aug 31, 2023 at 8:36 PM Robin Dapp wrote:
>
> OK. As it doesn't do anything and we'll be needing it anyway no harm
> in adding it.
>
> Regards
> Robin
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Thursday, August 31, 2023 8:39 PM
To: Robin Dapp
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; Juzhe-Zhong
Subject: Re: [PATCH] RISC-V: Add Vector cost model framework
On Thu, Aug 31, 2023 at 12:37:59PM +, Richard Biener via Gcc-patches wrote:
> The following keeps dumping SSA def stmt RHS during diagnostic
> reporting only for gimple_assign_single_p defs which means
> memory loads. This avoids diagnostics containing PHI nodes
> like
>
> warning: 'realloc
LoongArch processors may not support memory accesses without natural
alignments. Building libraries with -mstrict-align may help with
toolchain binary compatiblity and performance on these implementations
(e.g. Loongson 2K1000LA).
No significant performance degredation is observed on current main
gcc/ChangeLog:
* config.gcc: add loongarch*-elf target.
* config/loongarch/elf.h: New file.
Link against newlib by default.
libgcc/ChangeLog:
* config.host: add loongarch*-elf target.
---
gcc/config.gcc | 15 ++-
gcc/config/loongarch/elf.h | 5
The configure script and the GCC driver are updated so that
it is easier to customize and control GCC builds for targeting
different LoongArch implementations.
* Make --with-abi obsolete, since it might cause different default ABI
under the same target triplet, which is undesirable. The default
This is an update of
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628772.html
Changes since the last patchset:
1. Fix texinfo format of the install.texi document.
2. Add documentation for --with-strict-align-lib.
v1 -> v2:
1. Add new configure option --with-strict-align-lib to control
These are exported according to the LoongArch Toolchain Conventions[1]
as a replacement of the obsolete "_LOONGARCH_{ARCH,TUNE}" macros,
which are expanded to strings representing the actual architecture
and microarchitecture of the target.
[1] currently relased at https://github.com/loongson/Loon
LGTM
On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfmsub <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode,
LGTM
On Thu, Aug 24, 2023 at 12:49 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination
>
> vfadd RTZ <- intrinisc static rounding
> vfmadd <- autovec/autovec-opt
>
> The autovec generated vfmadd should take DYN mode,
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, August 31, 2023 9:10 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec
LGTM
On Thu, Aug 24
Yang Yujie writes:
Hello Yujie,
> gcc/ChangeLog:
>
> * ada/Makefile.rtl: Add LoongArch support.
> * ada/libgnarl/s-linux__loongarch.ads: New.
> * ada/libgnat/system-linux-loongarch.ads: New.
> * config/loongarch/loongarch.h: mark normalized options
> passed from d
On Tue, Aug 8, 2023 at 1:14 PM Jonathan Wakely wrote:
>
>
>
> On Tue, 18 Jul 2023 at 07:28, Ken Matsui via Libstdc++
> wrote:
>>
>> I will eventually work on disjunction to somehow optimize, but in the
>> meantime, this might be a better implementation. Of course, my
>> benchmark could be wrong.
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code snippet:
if (a == 0)
return 0;
else
return x;
}
which is equiva
On Tue, Aug 8, 2023 at 1:19 PM Jonathan Wakely wrote:
>
>
>
> On Tue, 18 Jul 2023 at 07:25, Ken Matsui via Libstdc++
> wrote:
>>
>> Hi,
>>
>> I took a benchmark for this.
>>
>> https://github.com/ken-matsui/gcc-benches/blob/main/is_fundamental-disjunction.md#mon-jul-17-105937-pm-pdt-2023
>>
>> t
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, August 31, 2023 9:09 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
LGTM
On Thu, Aug 24
On Wed, 30 Aug 2023 at 19:20, David Malcolm wrote:
>
> On Wed, 2023-08-30 at 11:52 +0530, Prathamesh Kulkarni wrote:
> > On Wed, 30 Aug 2023 at 04:21, David Malcolm
> > wrote:
> > >
> > > On Tue, 2023-08-29 at 11:01 +0530, Prathamesh Kulkarni wrote:
> > > > On Fri, 25 Aug 2023 at 18:15, David Mal
On Thu, Aug 31, 2023 at 6:57 AM Ken Matsui wrote:
>
> On Tue, Aug 8, 2023 at 1:19 PM Jonathan Wakely wrote:
> >
> >
> >
> > On Tue, 18 Jul 2023 at 07:25, Ken Matsui via Libstdc++
> > wrote:
> >>
> >> Hi,
> >>
> >> I took a benchmark for this.
> >>
> >> https://github.com/ken-matsui/gcc-benches/
While working on another patch, I hit a problem with the aarch64
expansion of untyped_call. The expander emits the usual:
(set (mem ...) (reg resN))
instructions to store the result registers to memory, but it didn't
say in RTL where those resN results came from. This eventually led
to a fail
While backporting another patch to an earlier release, I hit a
situation in which lra_eliminate_regs_1 would eliminate an address to:
(plus (reg:P R) (const_int 0))
This address compared not-equal to plain:
(reg:P R)
which caused an ICE in a later peephole2. (The ICE showed up in
gfort
As discussed in PR104167 (comments #8 and below), and PR111238, using
-Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
(cross-toolchain) avoids link failures for a few tests:
27_io/filesystem/path/108636.cc
std/time/clock/gps/1.cc
std/time/clock/gps/io.cc
std/time/clock/tai/1.cc
std/time/c
On 8/31/23 05:27, Iain Sandoe wrote:
Hi FX,
+Sandra
On 31 Aug 2023, at 12:13, FX Coudert wrote:
This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It is
not a global replacement though, and
Hi,
Thanks Sandra and Iain.
Patch pushed.
FX
On Wed, 2023-08-30 at 18:15 -0400, Eric Feng wrote:
> On Tue, Aug 29, 2023 at 5:14 PM David Malcolm
> wrote:
> >
> > On Tue, 2023-08-29 at 13:28 -0400, Eric Feng wrote:
> > > Additionally, by using the old model and the pointer per your
> > > suggestion,
> > > we are able to find the representati
> Date: Thu, 31 Aug 2023 17:25:45 +0200
> From: Christophe Lyon via Gcc-patches
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
> 27_io/filesystem/path/1
On 8/28/23 09:58, Jakub Jelinek wrote:
Hi!
On Thu, Aug 24, 2023 at 06:39:10PM +0200, Jakub Jelinek via Gcc-patches wrote:
Maybe do this in mangle_decomp, based on the actual mangling in process
instead of this pseudo-mangling?
Not sure that is possible, for 2 reasons:
1) determine_local_discr
This patch adds the following match patterns to optimize these:
/* (a != b) ? (a - b) : 0 -> (a - b) */
/* (a != b) ? (a ^ b) : 0 -> (a ^ b) */
/* (a != b) ? (a & b) : a -> (a & b) */
/* (a != b) ? (a | b) : a -> (a | b) */
/* (a != b) ? min(a,b) : a -> min(a,b) */
/* (a != b) ? max(a,b) : a
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added new types: "trap" (self explanatory) and "cbo"
(for cache related instructions)
Te
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib for linux/newlib.
gcc/Changelog:
On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
wrote:
>
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
> 27_io/filesystem/path/108636.cc
I think this one
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