[PATCH V3 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function

Functions which follow vector calling convention variant need be annotated by .variant_cc directive according the RISC-V Assembly Programmer's Manual[1] and RISC-V ELF Specification[2]. [1] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops [2] https://github.c

[PATCH V3 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed

Because functions which follow vector calling convention variant has callee-saved vector reigsters but functions which follow standard calling convention don't have. We need to distinguish which function callee is so that we can tell GCC exactly which vector registers callee will clobber. So I enco

[PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

LoongArch processors may not support memory accesses without natural alignments. Building libraries with -mstrict-align may help with toolchain binary compatiblity and performance on these implementations (e.g. Loongson 2K1000LA). No significant performance degredation is observed on current main

[PATCH v2 2/4] LoongArch: define preprocessing macros "__loongarch_{arch, tune}"

These are exported according to the LoongArch Toolchain Conventions[1] as a replacement of the obsolete "_LOONGARCH_{ARCH,TUNE}" macros, which are expanded to strings representing the actual architecture and microarchitecture of the target. [1] currently relased at https://github.com/loongson/Loon

[PATCH v2 1/4] LoongArch: improved target configuration interface

The configure script and the GCC driver are updated so that it is easier to customize and control GCC builds for targeting different LoongArch implementations. * Make --with-abi obsolete, since it might cause different default ABI under the same target triplet, which is undesirable. The default

[PATCH v2 4/4] LoongArch: support loongarch*-elf target

gcc/ChangeLog: * config.gcc: add loongarch*-elf target. * config/loongarch/elf.h: New file. Link against newlib by default. libgcc/ChangeLog: * config.host: add loongarch*-elf target. --- gcc/config.gcc | 15 ++- gcc/config/loongarch/elf.h | 5

[PATCH 0/4] LoongArch: target configuration interface update

This is an update of https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627275.html Changes since the last patchset: 1. Add new configure option --with-strict-align-lib to control whether -mstrict-align should be used when building libraries. This facilitates building toolchains targetin

[PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

Fix ICE in "vect" testsuite: FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record, at df-scan.cc:2958) FAIL: gcc.dg/vect/pr64495.c (test for excess errors After this patch, all current found VSETVL PASS related bugs in "vect" are fixed. gcc/ChangeLog: * config/riscv

Re: RFC: Top level configure: Require a minimum version 6.8 texinfo

On Tue, Aug 29, 2023 at 11:23 AM Nick Clifton via Gcc-patches wrote: > > Hi Guys, > > Currently the top level configure.ac file sets the minimum required > version of texinfo to be 4.7. I would like to propose changing this > to 6.8. > > The reason for the change is that the bfd documenta

Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

Lgtm Juzhe-Zhong 於 2023年8月30日 週三，10:22寫道： > Fix ICE in "vect" testsuite: > > FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record, > at df-scan.cc:2958) > FAIL: gcc.dg/vect/pr64495.c (test for excess errors > > After this patch, all current found VSETVL PASS related bugs in "ve

RE: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Wednesday, August 30, 2023 10:57 AM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com Subject: Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX v

[PATCH] middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias

Like MASK_LOAD_LANES/MASK_STORE_LANES, add MASK_LEN_ variant. Bootstrap and Regression on X86 passed. Ok for trunk? gcc/ChangeLog: * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Add MASK_LEN_ variant. (call_may_clobber_ref_p_1): Ditto. * tree-ssa-loop-ivopts.cc (get_m

Re: [PATCH] RISC-V: Make arch-24.c to test "success" case

On 8/28/23 21:31, Tsukasa OI wrote: From: Tsukasa OI arch-24.c and arch-25.c are exactly the same and redundant. The author suspects that the original author intended to test two base ISAs (RV32I and RV64I) so this commit changes arch-24.c to test that RV32I+Zcf does not cause any errors.

[PATCH] RISC-V: Document some -march special cases

Vineet just got bit by the autovec params, and a bunch of us forgot about the second one. gcc/ChangeLog: * doc/invoke.texi (RISC-V Options): Add some -march special cases. --- gcc/doc/invoke.texi | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --

Re: [PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

On Wed, 2023-08-30 at 09:58 +0800, Yang Yujie wrote: > LoongArch processors may not support memory accesses without natural > alignments.  Building libraries with -mstrict-align may help with > toolchain binary compatiblity and performance on these implementations > (e.g. Loongson 2K1000LA). > > N

Re: [PATCH] RISC-V: Document some -march special cases

I would prefer NOT to expose those --param on user manual since generally those options are used for internal only, we should add -m option and enable `--param=riscv-autovec-preference=scalable` by default once we think it's stable enough. On Wed, Aug 30, 2023 at 1:04 PM Palmer Dabbelt wrote: > >

Re: [PATCH V1 1/2] light expander sra v0

Hi Richard, Thanks so much for your great review! Richard Biener writes: > On Wed, 23 Aug 2023, Jiufu Guo wrote: > >> >> Hi, >> >> I just updated the patch. We could review this one. >> >> Compare with previous patch: >> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627287.html >>

Re: [pushed] analyzer: fix ICE in text art strings support

On Wed, 30 Aug 2023 at 04:21, David Malcolm wrote: > > On Tue, 2023-08-29 at 11:01 +0530, Prathamesh Kulkarni wrote: > > On Fri, 25 Aug 2023 at 18:15, David Malcolm via Gcc-patches > > wrote: > > > > > > Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. > > > Pushed to trunk as r14-3

[RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

From: Tsukasa OI 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard 'Zicond' extension are functionally equ

Re: [PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

> > LoongArch processors may not support memory accesses without natural > > alignments.  Building libraries with -mstrict-align may help with > > toolchain binary compatiblity and performance on these implementations > > (e.g. Loongson 2K1000LA). > > > > No significant performance degredation is

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