Re: [committed] i386: Fix grammar typo in diagnostic

On Tue, Aug 8, 2023 at 5:22 AM Marek Polacek via Libstdc++ wrote: > > On Mon, Aug 07, 2023 at 10:12:35PM +0100, Jonathan Wakely via Gcc-patches > wrote: > > Committed as obvious. > > > > Less obvious (to me) is whether it's correct to say "GCC V13" here. I > > don't think we refer to a version th

Re: [PATCH] Fortran: implement vector sections in DATA statements [PR49588]

Hi Paul, Am 22.08.23 um 08:32 schrieb Paul Richard Thomas via Gcc-patches: Hi Harald, It all looks good to me and does indeed make the code clearer. OK for trunk. Thanks for the patch. thanks for the review! I was shocked to find that there are 217 older bugs than 49588. Does anybody test

[PATCH] RISC-V: Adapt live-1.c testcase

Commited. Fix failures: FAIL: gcc.target/riscv/rvv/autovec/partial/live-1.c scan-tree-dump-times optimized ".VEC_EXTRACT" 10 FAIL: gcc.target/riscv/rvv/autovec/partial/live-1.c scan-tree-dump-times optimized ".VEC_EXTRACT" 10 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/par

Re: Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

>> This seems relax the compatiblitly check to allow optimize more case, >> if so this should be a sperated patch. This is not a optimization fix, It's an bug fix. Since fusion for these 2 demands: 1. demand SEW and GE_SEW (meaning demand a SEW larger than a specific SEW). 2. demand SEW and GE_SEW

RE: Intel AVX10.1 Compiler Design and Support

> -Original Message- > From: Jakub Jelinek > Sent: Tuesday, August 22, 2023 11:02 PM > To: Hongtao Liu > Cc: Richard Biener ; Jiang, Haochen > ; ZiNgA BuRgA ; gcc- > patc...@gcc.gnu.org > Subject: Re: Intel AVX10.1 Compiler Design and Support > > On Tue, Aug 22, 2023 at 10:35:55PM +0800,

Ping^^ [PATCH V5 2/2] Optimize '(X - N * M) / N' to 'X / N - M' if valid

Hi, I would like to have a gentle ping... BR, Jeff (Jiufu Guo) On 2023-08-07 10:45, guojiufu via Gcc-patches wrote: Hi, Gentle ping... On 2023-07-18 22:05, Jiufu Guo wrote: Hi, Integer expression "(X - N * M) / N" can be optimized to "X / N - M" if there is no wrap/overflow/underflow and "

Re: [PATCH] vect: Replace DR_GROUP_STORE_COUNT with DR_GROUP_LAST_ELEMENT

Hi Richi, on 2023/8/22 20:17, Richard Biener wrote: > On Tue, Aug 22, 2023 at 10:44 AM Kewen.Lin wrote: >> >> Hi, >> >> Now we use DR_GROUP_STORE_COUNT to record how many stores >> in a group have been transformed and only do the actual >> transform when encountering the last one. I'm making >>

[PATCH] RISC-V: Add attribute to vtype change only vsetvl

This patch is prepare patch for VSETVL PASS. Commited. gcc/ChangeLog: * config/riscv/vector.md: Add attribute. --- gcc/config/riscv/vector.md | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e772e7905

[PATCH] libgcc/m68k: Fixes for soft float

Check for non-zero denorm in __adddf3. Need to check both the upper and lower 32-bit chunks of a 64-bit float for a non-zero value when checking to see if the value is -0. Fix __addsf3 when the sum exponent is exactly 0xff to ensure that produces infinity and not nan. Handle converting NaN/inf va

Re: Intel AVX10.1 Compiler Design and Support

On Wed, Aug 23, 2023 at 9:58 AM Jiang, Haochen wrote: > > > -Original Message- > > From: Jakub Jelinek > > Sent: Tuesday, August 22, 2023 11:02 PM > > To: Hongtao Liu > > Cc: Richard Biener ; Jiang, Haochen > > ; ZiNgA BuRgA ; gcc- > > patc...@gcc.gnu.org > > Subject: Re: Intel AVX10.1 C

[PATCH] RISC-V: Fix gather_load_run-12.c test

FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Add vsetvli asm. --- .../riscv/rvv/autovec/gather-scatter/gather_load_run-12.c | 6 ++ 1 file changed, 6 insertions(

[PATCH] RISC-V: Fix VTYPE fuse rule bug

This bug is exposed after refactor patch. Separate it and commited. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (ge_sew_ratio_unavailable_p): Fix fuse rule bug. * config/riscv/riscv-vsetvl.def (DEF_SEW_LMUL_FUSE_RULE): Ditto. --- gcc/config/riscv/riscv-vsetvl.cc | 10 +++

[PATCH] RISC-V: Fix potential ICE of global vsetvl elimination

Committed for following VSETVL refactor patch to make V2 patch easier to review. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Fix potential ICE. --- gcc/config/riscv/riscv-vsetvl.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-

[PATCH v2] libffi: Backport of LoongArch support for libffi.

v1 -> v2: Modify the changelog information and add PR libffi/108682. This is a backport of , and contains modifications to commit 5a4774cd4d, as well as the LoongArch schema portion of commit ee22ecbd11. This is needed for libgo. libffi

[PATCH V2] RISC-V: Add conditional unary neg/abs/not autovec patterns

V2 changes: 1. remove xfail 2. testcase files naming harmonized with existing --- Hi, This patch add conditional unary neg/abs/not autovec patterns to RISC-V backend. For this C code: void test_3 (float *__restrict a, float *__restrict b, int *__restrict pred, int n) { for (int i = 0; i < n;

Re: [PATCH] RISC-V: Add conditional unary neg/abs/not autovec patterns

Hi Robin, Thanks for these nice comments! - emit_insn (gen_vcond_mask (vmode, vmode, d->target, d->op0, d->op1, mask)); + /* swap op0 and op1 since the order is opposite to pred_merge. */ + rtx ops2[] = {d->target, d->op1, d->op0, mask}; + emit_vlmax_merge_insn (code_for_pred_merge (vmode)

[PATCH] Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")

Both "graniterapid-d" and "graniterapids" are attached with PROCESSOR_GRANITERAPID in processor_alias_table but mapped to different __cpu_subtype in get_intel_cpu. And get_builtin_code_for_version will try to match the first PROCESSOR_GRANITERAPIDS in processor_alias_table which maps to "granitepr

[PATCH V1 1/2] light expander sra v0

Hi, I just updated the patch. We could review this one. Compare with previous patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627287.html This version: * Supports bitfield access from one register. * Allow return scalar registers cleaned via contructor. Bootstrapped and regtested

Re: [PATCH 1/3] vect: Remove some manual release in vectorizable_store

on 2023/8/22 20:32, Richard Biener wrote: > On Tue, Aug 22, 2023 at 10:45 AM Kewen.Lin wrote: >> >> Hi, >> >> To avoid some duplicates in some follow-up patches on >> function vectorizable_store, this patch is to adjust some >> existing vec with auto_vec and remove some manual release >> invocatio

Re: [committed] i386: Fix grammar typo in diagnostic

On Wed, Aug 23, 2023 at 7:28 AM Hongtao Liu wrote: > > On Tue, Aug 8, 2023 at 5:22 AM Marek Polacek via Libstdc++ > wrote: > > > > On Mon, Aug 07, 2023 at 10:12:35PM +0100, Jonathan Wakely via Gcc-patches > > wrote: > > > Committed as obvious. > > > > > > Less obvious (to me) is whether it's cor

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

Thanks Jeff for comments, and sorry for late response. The background comes from the CALL insn. For the RISC-V dynamic rounding mode we need to 1. restore the frm BEFORE call, to avoid the static rounding mode pollute the call. 2. Backup the frm AFTER call, to ensure the frm value after call is

Re: [pushed][PATCH v2] libffi: Backport of LoongArch support for libffi.

Pushed to r14-3405. 在 2023/8/23 上午10:56, Lulu Cheng 写道: v1 -> v2: Modify the changelog information and add PR libffi/108682. This is a backport of , and contains modifications to commit 5a4774cd4d, as well as the LoongArch schema p

RE: Intel AVX10.1 Compiler Design and Support

> -Original Message- > From: Hongtao Liu > Sent: Wednesday, August 23, 2023 10:19 AM > To: Jiang, Haochen > Cc: Jakub Jelinek ; Richard Biener > ; ZiNgA BuRgA ; > gcc-patches@gcc.gnu.org > Subject: Re: Intel AVX10.1 Compiler Design and Support > > On Wed, Aug 23, 2023 at 9:58 AM Jiang, H

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