Convert be sinked into a vec_cond if both sides
fold. Unlike other unary operations, we need to check that we still can handle
this vec_cond's first operand is the same as the new truth type.
I tried a few different versions of this patch:
view_convert to the new truth_type but that does not work
Thanks Kito, will commit it after the VFNCVT.X.F.W one, aka the signed integer
cvt.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, August 17, 2023 9:30 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.F.{X|XU|F}.W as the below samples.
* __riscv_vfncvt_f_x_w_f32m1_rm
* __riscv_vfncvt_f_x_w_f32m1_rm_m
* __riscv_vfncvt_f_xu_w_f32m1_rm
* __riscv_vfncvt_f_xu_w_f32m1_rm_m
* __riscv_vfncvt_f_f_w_f32m1_rm
* __riscv_vf
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDUSUM.VS as the below samples.
* __riscv_vfredusum_vs_f32m1_f32m1_rm
* __riscv_vfredusum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(cla
On 8/16/23 7:19 PM, Carl Love wrote:
> +(define_insn "dfp_dquan_"
> + [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
> +(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
> + (match_operand:DDTD 2 "gpc_reg_operand" "d")
> + (match_operand:QI
On 8/16/23 13:10, Alexander Monakov wrote:
On Tue, 15 Aug 2023, Jeff Law wrote:
Because if the compiler can optimize it automatically, then the projects have
to do literally nothing to take advantage of it. They just compile normally
and their bitwise CRC gets optimized down to either a ta
Lgtm
Pan Li via Gcc-patches 於 2023年8月17日 週四，10:19寫道：
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFNCVT.F.{X|XU|F}.W as the below samples.
>
> * __riscv_vfncvt_f_x_w_f32m1_rm
> * __riscv_vfncvt_f_x_w_f32m1_rm_m
> * __riscv_vfncvt_f_xu_w_f32m1_rm
> * __risc
Lgtm
Pan Li via Gcc-patches 於 2023年8月17日 週四，11:09寫道：
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFREDUSUM.VS as the below samples.
>
> * __riscv_vfredusum_vs_f32m1_f32m1_rm
> * __riscv_vfredusum_vs_f32m1_f32m1_rm_m
>
> Signed-off-by: Pan Li
>
> gcc/Chang
On Tue, 2023-08-15 at 20:03 +, Joseph Myers wrote:
> On Tue, 15 Aug 2023, chenxiaolong wrote:
>
> > In the implementation process, the "q" suffix function is
> > Re-register and associate the "__float128" type with the
> > "long double" type so that the compiler can han
On 8/16/23 02:40, yanzhang.wang--- via Gcc-patches wrote:
From: Yanzhang Wang
The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2
On 8/16/23 19:17, Patrick O'Neill wrote:
This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-08.c: New test.
* gcc.target/riscv/zbb-rol-ror-09.c: New test.
Co
on 2023/8/17 11:11, Peter Bergner wrote:
> On 8/16/23 7:19 PM, Carl Love wrote:
>> +(define_insn "dfp_dquan_"
>> + [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
>> +(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
>> + (match_operand:DDTD 2 "gpc_reg_operand
On Fri, Aug 04, 2023 at 07:44:28PM +, Qing Zhao wrote:
> This is the 2nd version of the patch, per our discussion based on the
> review comments for the 1st version, the major changes in this version
I've been using Coccinelle to find and annotate[1] structures (193 so
far...), and I've encoun
void foo(_Float16 y, int64_t *i64p)
{
vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
}
zve64f:
foo:
vsetivlizero,1,e16,mf4,ta,ma
LGTM, thanks :)
On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong wrote:
>
> void foo(_Float16 y, int64_t *i64p)
> {
> vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
> vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
> vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
> asm volatile ("# use %0 %1" : : "v
Hi Carl,
on 2023/8/17 08:19, Carl Love wrote:
>
> GCC maintainers:
>
> Version 2, renamed the built-in instances. Changed the name of the
> overloaded built-in. Added the missing documentation for the new
> built-ins. Fixed typos. Changed name of the test. Updated the
> effective target for
Hi,
As PR111021 shows, the below ${port}-protos.h include tree.h
for code_helper and tree_code:
arm/arm-protos.h:#include "tree.h"
cris/cris-protos.h:#include "tree.h" (H-P removed this in r14-3218)
microblaze/microblaze-protos.h:#include "tree.h"
rl78/rl78-protos.h:#include "tree.h"
st
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Thursday, August 17, 2023 2:08 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V:
Hi,
Similar to the existing function vect_build_gather_load_calls,
this patch is to factor out the handling on scatter store
having gs_info.decl to vect_build_scatter_store_calls which
is a new function. It also does some minor refactoring like
moving some variables' declarations close to their u
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDOSUM.VS as the below samples.
* __riscv_vfredosum_vs_f32m1_f32m1_rm
* __riscv_vfredosum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfr
Hi Jeff,
Thank you so much for the note and testing :D.
I'll attach the test result next time.
Thanks,
Yanzhang
> -Original Message-
> From: Jeff Law
> Sent: Thursday, August 17, 2023 12:33 PM
> To: Wang, Yanzhang ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.c
On Wed, Aug 16, 2023 at 10:31:30PM -0700, Kees Cook wrote:
> On Fri, Aug 04, 2023 at 07:44:28PM +, Qing Zhao wrote:
> > This is the 2nd version of the patch, per our discussion based on the
> > review comments for the 1st version, the major changes in this version
>
> I've been using Coccinell
Okay, thanks for the heads up! I'll try to format the code according to
the GNU Coding Standards. I'll double-check every line of the submitted
patch to make sure that I don't have such a low-level formatting
problem in every future patch, so that I can comply with the code
specification.
在 2023-0
Hi all,
I have just checked in the first nine patches for AVX10.1 after
one day waiting since Hongtao said ok.
These two patches aimed to add AVX512DQ scalar intrins to AVX10.1.
Regtested on on x86_64-pc-linux-gnu. Ok for trunk?
Also, We proposed to commit the patches step by step in the follow
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_1-kaddb-1.c: New test.
* gcc.target/i386/avx10_1-kaddw-1.c: Ditto.
* gcc.target/i386/avx10_1-kandb-1.c: Ditto.
* gcc.target/i386/avx10_1-kandnb-1.c: Ditto.
* gcc.target/i386/avx10_1-kmovb-1.c: Ditto.
*
gcc/ChangeLog:
* config.gcc: Add avx512dqavx10_1intrin.h.
* config/i386/avx512dqintrin.h: Move avx10_1 related intrins
to new intrin file.
* config/i386/i386-builtin.def (BDESC):
Add OPTION_MASK_ISA2_AVX10_1.
* config/i386/i386.md (x64_avx512dq): Ren
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