Re: [PATCH V5 1/2] Add overflow API for plus minus mult on range

Hi, I would like to have a ping on this patch. BR, Jeff (Jiufu Guo) Jiufu Guo writes: > Hi, > > As discussed in previous reviews, adding overflow APIs to range-op > would be useful. Those APIs could help to check if overflow happens > when operating between two 'range's, like: plus, minus,

[PATCH] Fix `~X & X` and `~X | X` patterns

cc.c-torture/execute/20230802-1.c: New test. --- gcc/match.pd | 6 +- .../gcc.c-torture/execute/20230802-1.c| 68 +++ 2 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/20230802-1.c

[PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API

From: Pan Li Update in v2: * Sync with upstream for the vfmul duplicated declaration. Original log: This patch would like to support the rounding mode API for the VFMUL for the below samples. * __riscv_vfmul_vv_f32m1_rm * __riscv_vfmul_vv_f32m1_rm_m * __riscv_vfmul_vf_f32m1_rm * __riscv_vfmul

[PATCH] Fix PR 110874: infinite loop in gimple_bitwise_inverted_equal_p with fre

So I didn't expect valueization to cause calling gimple_nop_convert to iterate between 2 different SSA names causing an infinite loop in gimple_bitwise_inverted_equal_p. So we should cause a bound on gimple_bitwise_inverted_equal_p calling gimple_nop_convert and only look through one rather than al

Re: [PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2023-08-03 10:32 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang Subject: [PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API From: Pan Li Update in v2: * Sync with upstream for the vfmul duplicated declaration

[PATCH V4] VECT: Support CALL vectorization for COND_LEN_*

From: Ju-Zhe Zhong Hi, Richard and Richi. Base on the suggestions from Richard: https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625396.html This patch choose (1) approach that Richard provided, meaning: RVV implements cond_* optabs as expanders. RVV therefore supports both IFN_COND_ADD an

Re: Re: [PATCH V2] VECT: Support CALL vectorization for COND_LEN_*

Hi, Richi. I have fully tested in RISC-V port with adding gcc_unreachable () in V4 patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626133.html Bootstrap and regression on X86 passed. juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-08-02 16:33 To: juzhe.zh...@rivai.ai CC: r

Re: [PATCH 0/5] Recognize Zicond extension

On 7/28/23 00:34, Xiao Zeng wrote: What I like about yours is it keeps all the logic in riscv.cc rather than scattering it across riscv.cc and riscv.md. Yes, when I use enough test cases, I cannot find a concise way to optimize all test cases. When I enumerated all possible cases in the

RE: [PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, August 3, 2023 10:36 AM To: Li, Pan2 ; gcc-patches Cc: Kito.cheng ; Li, Pan2 ; Wang, Yanzhang Subject: Re: [PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API LGTM juzhe.zh.

[RFC] Combine zero_extract and sign_extend for TARGET_TRULY_NOOP_TRUNCATION

PR #104914 On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms, zero_extract (SI, SI) can be sign-extended. So, if a zero_extract (DI, DI) following with an sign_extend(SI, DI) can be merged to a single zero_extract (SI, SI). gcc/ChangeLog: PR: 104914. * combine.

[PATCH v1] RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API

From: Pan Li This patch would like to support the rounding mode API for the VFDIV and VFRDIV for the below samples. * __riscv_vfdiv_vv_f32m1_rm * __riscv_vfdiv_vv_f32m1_rm_m * __riscv_vfdiv_vf_f32m1_rm * __riscv_vfdiv_vf_f32m1_rm_m * __riscv_vfrdiv_vf_f32m1_rm * __riscv_vfrdiv_vf_f32m1_rm_m Sig

Re: [PATCH v1] RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API

I am considering whether it is better to have multiple macro define for FRM ? like: DECLARE_FRM_FUNCTION_BASE (NAME)\ extern const function_base *const NAME; extern const function_base *const NAME##_frm; DECLARE_FRM_FUNCTION (NAME, )\ DEF_RVV_FUNCTION (NAME##_frm, alu, ); DEF_RVV

Re: [RFC] Combine zero_extract and sign_extend for TARGET_TRULY_NOOP_TRUNCATION

YunQiang Su 于2023年8月3日周四 11:18写道： > > PR #104914 > > On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms, > zero_extract (SI, SI) can be sign-extended. So, if a zero_extract (DI, > DI) following with an sign_extend(SI, DI) can be merged to a single > zero_extract (SI, SI). > The

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On 7/29/23 03:14, Xiao Zeng wrote: 1 Thank you for Jeff's code review comments. I have made the modifications and submitted the V2-patch[3/5]. Yea. I'm adjusting my tree based on those updates. For testing I've actually got my compiler generating zicond by default and qemu allowing zicon

Re: [x86 PATCH] PR target/110792: Early clobber issues with rot32di2_doubleword.

On Thu, Aug 3, 2023 at 12:18 AM Roger Sayle wrote: > > > This patch is a conservative fix for PR target/110792, a wrong-code > regression affecting doubleword rotations by BITS_PER_WORD, which > effectively swaps the highpart and lowpart words, when the source to be > rotated resides in memory. Th

Re: [PATCH 1/2] Add virtual operand global liveness computation class

On 8/2/23 06:44, Richard Biener via Gcc-patches wrote: The following adds an on-demand global liveness computation class computing and caching the live-out virtual operand of basic blocks and answering live-out, live-in and live-on-edge queries. The flow is optimized for the intended use in c

Re: [PATCH 2/2] Improve sinking with unrelated defs

On 8/2/23 06:44, Richard Biener via Gcc-patches wrote: statement_sink_location for loads is currently confused about stores that are not on the paths we are sinking across. The following replaces the logic that tries to ensure we are not sinking across stores by instead of walking all immedia

Re: [PATCH] MATCH: first of the value replacement moving from phiopt

On 8/2/23 17:52, Andrew Pinski via Gcc-patches wrote: This moves a few simple patterns that are done in value replacement in phiopt over to match.pd. Just the simple ones which might show up in other code. This allows some optimizations to happen even without depending on sinking from happeni

Re: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

On 8/1/23 19:51, Wang, Yanzhang wrote: Hi Jeff, Do you have any further comments about this patch ? I thought we covered this in the meeting earlier this week. This is fine for the trunk. If you or Pan doesn't get around to committing it before I start my day tomorrow, I'll go ahead and

[PATCH v1] RISC-V: Support RVV VFWMUL rounding mode intrinsic API

From: Pan Li This patch would like to support the rounding mode API for the VFWMUL for the below samples. * __riscv_vfwmul_vv_f64m2_rm * __riscv_vfwmul_vv_f64m2_rm_m * __riscv_vfwmul_vf_f64m2_rm * __riscv_vfwmul_vf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-

RE: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

Thanks Jeff and nice dream, I will commit this patch. Pan -Original Message- From: Jeff Law Sent: Thursday, August 3, 2023 2:13 PM To: Wang, Yanzhang ; Kito Cheng Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 Subject: Re: [PATCH v3] RISCV: Add -m(

Re: [RFC] light expander sra for parameters and returns

Hi Richard, Richard Biener writes: > On Tue, 1 Aug 2023, Jiufu Guo wrote: > >> >> Hi, >> >> Richard Biener writes: >> >> > On Mon, 24 Jul 2023, Jiufu Guo wrote: >> > >> >> >> >> Hi Martin, >> >> >> >> Not sure about your current option about re-using the ipa-sra code >> >> in the light-e

RE: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

Committed, thanks Jeff and Kito. Pan -Original Message- From: Li, Pan2 Sent: Thursday, August 3, 2023 2:17 PM To: Jeff Law ; Wang, Yanzhang ; Kito Cheng Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com Subject: RE: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-po

Re: [PATCH] MATCH: first of the value replacement moving from phiopt

On Wed, Aug 2, 2023 at 11:10 PM Jeff Law via Gcc-patches wrote: > > > > On 8/2/23 17:52, Andrew Pinski via Gcc-patches wrote: > > This moves a few simple patterns that are done in value replacement > > in phiopt over to match.pd. Just the simple ones which might show up > > in other code. > > > >

[PATCH] s390: Enable vect_bswap test cases

This enables the following tests which rely on instruction vperm which is available since z13 with the initial vector support. testsuite/gcc.dg/vect/vect-bswap16.c 42:/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_bswap || sse4_runtime } } } } */ testsuite/gcc

[PATCH] s390: Try to emit vlbr/vstbr instead of vperm et al.

Bootstrapped and regtested on s390x. Ok for mainline? gcc/ChangeLog: * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate): New function which handles bswap patterns for vec_perm_const. (vectorize_vec_perm_const_1): Call new function. * config/s390/vector.

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