[committed] CRIS: Don't apply PATTERN to insn before validation (PR 110144)

Oops. The validation was there, but PATTERN was applied before that. Noticeable only with rtl-checking (for example as in the report: "--enable-checking=yes,rtl") as this statement was only a (one of many) straggling olde-C declare-and-initialize-at-beginning-of-block thing. PR target/11

[committed] testsuite: check_effective_target_lra: CRIS is LRA

Left-over from r14-383-gfaf8bea79b6256. * lib/target-supports.exp (check_effective_target_lra): Remove cris-*-* from expression for exceptions to LRA. --- gcc/testsuite/lib/target-supports.exp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/

[PATCH] A couple of va_gc_atomic tweaks

The only current user of va_gc_atomic is Ada's: vec It uses the generic gt_pch_nx routines (with gt_pch_nx being the “note pointers” hooks), such as: template void gt_pch_nx (vec *v) { extern void gt_pch_nx (T &); for (unsigned i = 0; i < v->length (); i++)

Re: Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

Ok. Plz go ahead commit this change with the testcases. Then it won't block the following patches. Thanks. juzhe.zh...@rivai.ai From: Richard Sandiford Date: 2023-06-29 04:42 To: Robin Dapp via Gcc-patches CC: 钟居哲; Jeff Law; Robin Dapp; kito.cheng; kito.cheng; palmer; palmer Subject: Re: [PATC

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

You can see here: https://godbolt.org/z/d78646hWb The first case can't genreate vfwmul.vv but second case succeed. Failed to match this instruction: (set (reg:VNx2DF 150 [ vect__11.50 ]) (if_then_else:VNx2DF (unspec:VNx2BI [ (const_vector:VNx2BI repeat [

Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering

Sure. https://godbolt.org/z/8857KzTno Failed to match this instruction: (set (reg:VNx2DF 134 [ vect__31.47 ]) (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ]))) (reg:VNx2DF 150 [ vect__8.12 ]) (reg:VNx2DF 171 [ vect__29.45 ]))) juzhe.zh...@riv

Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering

On 6/28/23 16:10, 钟居哲 wrote: Sure. https://godbolt.org/z/8857KzTno Failed to match this instruction: (set (reg:VNx2DF 134 [ vect__31.47 ])     (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))         (reg:VNx2DF 150 [ vect_

[r14-2159 Regression] FAIL: gcc.target/i386/pieces-memcmp-2.c scan-assembler-times vptest[ \\t]*%xmm 2 on Linux/x86_64

On Linux/x86_64, 4afbebcdc5780d28e52b7d65643e462c7c3882ce is the first bad commit commit 4afbebcdc5780d28e52b7d65643e462c7c3882ce Author: Roger Sayle Date: Wed Jun 28 11:11:34 2023 +0100 i386: Add cbranchti4 pattern to i386.md (for -m32 compare_by_pieces). caused FAIL: gcc.target/i386/pi

Re: [PATCH] analyzer: Fix regression bug after r14-1632-g9589a46ddadc8b [pr110198]

On Thu, 2023-06-22 at 21:55 +0200, priour...@gmail.com wrote: > From: benjamin priour > > Resend with proper subject line ... > > Hi, Hi Benjamin > > Below is the fix to regression bug > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110198 > Was bootstrapped and regtested successfully on x86_6

[PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching

From: Pan Li This patch would like to support the vfadd static round mode similar to the fixed-point. Then the related fsrm instructions will be inserted correlatively. Please *NOTE* this PATCH doesn't cover anything about FRM dynamic mode, it will be implemented in the underlying PATCH(s). Sig

[PATCH] PR gcc/110148:Avoid adding loop-carried ops to long chains

From: Lili Cui Hi Maintainer This patch is to fix TSVC242 regression related to loop-carried ops. Bootstrapped and regtested. Ok for trunk? Regards Lili. Avoid adding loop-carried ops to long chains, otherwise the whole chain will have dependencies across the loop iteration. Just keep loop-ca

Re: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-29 09:40 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw Subject: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching From: Pan Li This patch would like to support the vfadd static rou

Re: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching

LGTM, thanks :) On Thu, Jun 29, 2023 at 10:24 AM juzhe.zh...@rivai.ai wrote: > > LGTM > > > juzhe.zh...@rivai.ai > > > From: pan2.li > Date: 2023-06-29 09:40 > To: gcc-patches > CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw > Subject: [PATCH v1]

Re: [PATCH v1] RISC-V: Allow rounding mode control for RVV floating-point add

LGTM, thanks! On Tue, Jun 27, 2023 at 3:02 PM Li, Pan2 wrote: > > Ack, thanks Juzhe. > > > > Pan > > > > From: juzhe.zh...@rivai.ai > Sent: Tuesday, June 27, 2023 3:00 PM > To: Li, Pan2 ; gcc-patches > Cc: Kito.cheng ; Li, Pan2 ; Wang, > Yanzhang ; jeffreyalaw > Subject: Re: [PATCH v1] RISC-V

Re: Re: [PATCH v1] RISC-V: Allow rounding mode control for RVV floating-point add

Hi, Pan. I think the last step is to support dynamic mode switching which may need to change the mode-switching PASS. After this done, I suggest you go over all rounding mode API (including fixed-point and floating-point.) Check SPIKE implementation, make sure which API needs rounding mode, wh

[PATCH] i386: refactor macros.

Hi, all This patch aims to refactor macros in case some other thing is added to AMX_TILE_SET in future. OK for trunk? BRs, Lin gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Change OPTION_MASK_ISA2_AMX_TILE to OPTION_MASK_ISA2_AMX_TILE_SET.

RE: Re: [PATCH v1] RISC-V: Allow rounding mode control for RVV floating-point add

Sure thing, echo on below part. I think we need one place to put something like summary for this, for example, a table to indicate some information about this (aka rounding mode needed or not). I will try to summarize one draft then. > Check SPIKE implementation, make sure which API needs roundi

RE: [PATCH] x86: Update model values for Alderlake, Rocketlake and Raptorlake.

I will directly commit this patch, it can be considered as an obvious patch. Thanks, Lili. > -Original Message- > From: Gcc-patches On > Behalf Of Cui, Lili via Gcc-patches > Sent: Wednesday, June 28, 2023 6:52 PM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao > Subject: [PATCH] x86:

Re: [PATCH V3] Optimize '(X - N * M) / N' to 'X / N - M' if valid

Hi, Jiufu Guo writes: > Hi, > > Integer expression "(X - N * M) / N" can be optimized to "X / N - M" if > there is no wrap/overflow/underflow and "X - N * M" has the same sign > with "X". > > Compare with the previous version: > https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620896.html >

Re: [PATCH V3 1/4] rs6000: build constant via li;rotldi

Hi, Jiufu Guo via Gcc-patches writes: > Hi! > > Segher Boessenkool writes: > >> Hi! >> >> On Fri, Jun 16, 2023 at 04:34:12PM +0800, Jiufu Guo wrote: >>> +/* Check if value C can be built by 2 instructions: one is 'li', another is >>> + rotldi. >>> + >>> + If so, *SHIFT is set to the shift

RE: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

It seems this patch may result in many test ICE failures on RISC-V backend. Could you help to double confirm about it follow the possible reproduce steps like blow? Thank you! cd gcc && mkdir __BUILD__ && cd __BUILD__ ../configure \ --target=riscv64-unknown-elf \ --prefix= \ --disable-shar

RE: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching

Committed, thanks Kito and Juzhe. pan -Original Message- From: Kito Cheng Sent: Thursday, June 29, 2023 10:34 AM To: juzhe.zh...@rivai.ai Cc: Li, Pan2 ; gcc-patches ; Wang, Yanzhang ; jeffreyalaw Subject: Re: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching LG

RE: [PATCH v1] RISC-V: Allow rounding mode control for RVV floating-point add

Committed, thanks Kito and Juzhe. Pan -Original Message- From: Kito Cheng Sent: Thursday, June 29, 2023 10:35 AM To: Li, Pan2 Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang, Yanzhang ; jeffreyalaw Subject: Re: [PATCH v1] RISC-V: Allow rounding mode control for RVV floating-point add

RE: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

Sorry for disturbing, cc kito, juzhe and robin for awareness. Pan -Original Message- From: Li, Pan2 Sent: Thursday, June 29, 2023 12:05 PM To: Jakub Jelinek ; Richard Biener Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com Subject: RE: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs I

Re: [PATCH] i386: refactor macros.

On Thu, Jun 29, 2023 at 10:51 AM Hu, Lin1 via Gcc-patches wrote: > > Hi, all > > This patch aims to refactor macros in case some other thing is added to > AMX_TILE_SET in future. OK for trunk? Ok, thanks. > > BRs, > Lin > > gcc/ChangeLog: > > * common/config/i386/i386-common.cc (OPTION_MAS

Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

On 6/28/23 22:04, Li, Pan2 wrote: It seems this patch may result in many test ICE failures on RISC-V backend. Could you help to double confirm about it follow the possible reproduce steps like blow? Thank you! I've one ICE due to this change as well but it wasn't in the tree-ssa-math-opts.c

[PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal

From: Pan Li This patch would like to refactor the vxrm_mode attr for duplicated eq_attr condition. The common condition of attr is extraced to one place instead of many places. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector.md: Refactor the common condition. --- gcc/conf

Re: [PATCH v2] mips: Fix overaligned function arguments [PR109435]

Jovan Dmitrovic 于2023年6月27日周二 16:54写道： > > Hi, > I am sending a revised patch, now with different tests for N64/N32 and O32 > ABIs. > For the O32 ABI, I've skipped the -O0 and -Os pipelines, considering there is > a > difference between exact offsets for store instructions (the registers used >

Re: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal

It's meaningless. Drop this patch. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-29 14:00 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw Subject: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal From: Pan Li This patch would like to refacto

Re: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal

Oh. I see. You are not only changing the format. Sorry about that I didn't notice. originally, each rounding mode has "vsalu,vaalu,vsmul,vsshift,vnclip" Now, you change all rounding mode sharing same "vsalu,vaalu,vsmul,vsshift,vnclip". When we want to remove some of the insn, we don't need to

Re: [PATCH] A couple of va_gc_atomic tweaks

On Wed, Jun 28, 2023 at 11:37 PM Richard Sandiford via Gcc-patches wrote: > > The only current user of va_gc_atomic is Ada's: > > vec > > It uses the generic gt_pch_nx routines (with gt_pch_nx being the > “note pointers” hooks), such as: > > template > void > gt_pch_nx (vec *v) >

Re: [PATCH] PR gcc/110148:Avoid adding loop-carried ops to long chains

On Thu, Jun 29, 2023 at 3:49 AM Cui, Lili wrote: > > From: Lili Cui > > Hi Maintainer > > This patch is to fix TSVC242 regression related to loop-carried ops. > > Bootstrapped and regtested. Ok for trunk? OK. Thanks, Richard. > Regards > Lili. > > Avoid adding loop-carried ops to long chains,

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