Hi,
Integer expression "(X - N * M) / N" can be optimized to "X / N - M" if
there is no wrap/overflow/underflow and "X - N * M" has the same sign
with "X".
Compare with the previous version:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620896.html
This version changes:
1. Remove the behavi
On Wed, Jun 28, 2023 at 6:09 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 6/27/23 21:16, Kito Cheng wrote:
> > Do you mind giving some comments about what the difference between the
> > two versions?
> And I'd like a before/after assembly code with the example in the commit
> message. I didn't s
This testcase was fixed after r14-2135-gd915762ea9043da85 and
there was no testcase for it before so adding one is a good thing.
Committed as obvious after testing the testcase to make sure it works.
gcc/testsuite/ChangeLog:
PR tree-optimization/110444
* gcc.c-torture/compile/pr1
On Jun 26, 2023, Qing Zhao wrote:
>>> For hardbool variables, what 0x00 represents if it’s not false or true
>>> value?
>>
>> It depends on how hardbool is parameterized. One may pick 0x00 or 0xFE
>> as the representations for true or false, or neither, in which case the
>> trivial initializer
On Tue, Jun 27, 2023 at 4:05 PM Andrew Pinski wrote:
>
> On Tue, Jun 27, 2023 at 8:56 AM Robin Dapp via Gcc-patches
> wrote:
> >
> > > You can put it into the original one.
> >
> > Bootstrap and testsuite run were successful.
> > I'm going to push the attached, thanks.
>
> I am reducing a bug rep
>
> On 6/27/23 12:24, Jan Hubicka wrote:
> > > On 6/27/23 09:19, Jan Hubicka wrote:
> > > > Hi,
> > > > as shown in the testcase (which would eventually be useful for
> > > > optimizing std::vector's push_back), ipa-prop can use context dependent
> > > > ranger
> > > > queries for better value ra
Hi, Richi.
Thanks for taking care of this issue.
From my observation, VNx2BI is using 2-bit mask: 00 = 0, 01 = 1
VNx4BI is using 4-bit mask: = 0, 0001
= 1
This perfectly works for ARM SVE since this is the layout of ARM mask register.
However, RVV is al
> I think the __throw_bad_alloc() and __throw_bad_array_new_length()
> functions should always be rare, so marking them cold seems fine (users who
> define their own allocators that want to throw bad_alloc "often" will
> probably throw it directly, they shouldn't be using our __throw_bad_alloc()
>
Hi Jeevitha,
on 2023/6/24 00:49, P Jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile
> register. However, it can be used as volatile for PCREL addressing. Th
Hi, Richi.
After I dig into the codes and experiment:
https://godbolt.org/z/hMf5nsPeK
This example is VNx8QI, GCC works fine for RVV using 1-bit compact mask.
ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1));
ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2))
Hi Pat,
> On 6/27/23 1:52 PM, Pat Haugen via Gcc-patches wrote:
>> Updated from prior version to address review comments (update
>> rs6000_rtx_cost,
>> update scan strings of mod-1.c/mod-2.c)l.
>>
>> Disable generation of scalar modulo instructions.
>>
>> It was recently discovered that the scala
> If the user specified a different arch for callee than the caller,
> then the compiler will switch on different ISAs (-march is just a
> shortcut for different ISA packs), and the programmer is aware that
> inlining isn't intended here (we have -mtune, which is not as strong
> as -march, but even
Hello, Qing,
On Jun 27, 2023, Qing Zhao wrote:
> I am wondering why stack scrubbing, proposed in this patch series, cannot do
> the stack scrubbing in the routine’s epilogue similar as
> register scrubbing?
There were multiple considerations that led to this design decision:
- Stack scrubbing
On Wed, 28 Jun 2023 at 08:56, Jan Hubicka wrote:
> > I think the __throw_bad_alloc() and __throw_bad_array_new_length()
> > functions should always be rare, so marking them cold seems fine (users
> who
> > define their own allocators that want to throw bad_alloc "often" will
> > probably throw it
This patch adds combine pattern as follows:
1. (set (reg) (fma (float_extend:reg)(float_extend:reg)(reg)))
This pattern allows combine: vfwcvt + vfwcvt + vfmacc ==> vwfmacc.
2. (set (reg) (fma (float_extend:reg)(reg)(reg)))
This pattern is the intermediate IR that enhances the combine optim
LGTM
On Wed, Jun 28, 2023 at 4:28 PM Juzhe-Zhong wrote:
>
> This patch adds combine pattern as follows:
>
> 1. (set (reg) (fma (float_extend:reg)(float_extend:reg)(reg)))
>This pattern allows combine: vfwcvt + vfwcvt + vfmacc ==> vwfmacc.
>
> 2. (set (reg) (fma (float_extend:reg)(reg)(reg)))
Hi Carl,
on 2023/6/22 06:42, Carl Love wrote:
> On Mon, 2023-06-19 at 15:17 +0800, Kewen.Lin wrote:
>> Hi Carl,
>>
>> on 2023/5/31 04:46, Carl Love wrote:
>>> GCC maintainers:
>>>
>>> The following patch takes the tests in vsx-vector-6-p7.h, vsx-
>>> vector-
>>> 6-p8.h, vsx-vector-6-p9.h and reor
On Wed, Jun 28, 2023 at 10:20 AM Hongyu Wang wrote:
>
> > If the user specified a different arch for callee than the caller,
> > then the compiler will switch on different ISAs (-march is just a
> > shortcut for different ISA packs), and the programmer is aware that
> > inlining isn't intended her
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Wednesday, June 28, 2023 4:31 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com;
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp
The following prevents non-grouped load SLP in case the element
to splat is from a gather operation. While it should be possible
to support this it is not similar to the single element interleaving
case I was trying to mimic here.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
If GCC is configured with the default (soft) -mfloat-abi, and we don't
override the target_board test flags appropriately,
gcc.target/arm/mve/general-c/nomve_fp_1.c fails for lack of
-mfloat-abi=softfp or -mfloat-abi=hard, because it doesn't use
dg-add-options arm_v8_1m_mve (on purpose, see comment
This tests currently expect a directive containing .fpu fpv5-sp-d16
and thus may fail if the test is executed for instance with
-march=armv8.1-m.main+mve.fp+fp.dp
This patch accepts either fpv5-sp-d16 or fpv5-d16 to avoid the failure.
2023-06-28 Christophe Lyon
gcc/testsuite/
Iain Sandoe writes:
> Tested on various affected Darwin versions and on x86_64-linux-gnu
> OK for trunk?
> OK for 13.2?
> thanks
> Iain
lgtm - many thanks,
regards,
Gaius
Hi Harald,
I'll change to gfc_charlen_type_node.
Thanks for your patience in reviewing this patch :-)
Cheers
Paul
On Tue, 27 Jun 2023 at 20:27, Harald Anlauf wrote:
>
> Hi Paul,
>
> this is much better now.
>
> I have only a minor comment left: in the calculation of the
> size of a character
This bug blocks the following patches.
GCC doesn't know RVV is using compact mask model.
Consider this following case:
#define N 16
int
main ()
{
int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1};
int8_t out[N] = {0};
for (int8_t i = 0; i < N; ++i)
if (mask[i])
ou
Hi, after deeply diging into this issue:
I figure out what is happening, this is the V3 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/623052.html
There is a comprehensive explanation in commit log.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-28 11:16
To: juzhe.zh...@rivai
On 28/06/2023 10:26, Christophe Lyon via Gcc-patches wrote:
If GCC is configured with the default (soft) -mfloat-abi, and we don't
override the target_board test flags appropriately,
gcc.target/arm/mve/general-c/nomve_fp_1.c fails for lack of
-mfloat-abi=softfp or -mfloat-abi=hard, because it doe
On 28/06/2023 10:26, Christophe Lyon via Gcc-patches wrote:
This tests currently expect a directive containing .fpu fpv5-sp-d16
and thus may fail if the test is executed for instance with
-march=armv8.1-m.main+mve.fp+fp.dp
This patch accepts either fpv5-sp-d16 or fpv5-d16 to avoid the failure.
When NRV replaces a local variable with it also replaces
occurences in clobbers. This leads to being clobbered
before the return of it which is strictly invalid but harmless in
practice since there's no pass after NRV which would remove
earlier stores.
The following fixes this nevertheless.
Bo
Hi,
This patch implements clang's __has_feature and __has_extension in GCC.
This is a v2 of the original RFC posted here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617878.html
Changes since v1:
- Follow the clang behaviour where -pedantic-errors means that
__has_extension behaves ex
On Wed, Jun 28, 2023 at 10:21:45AM +, Richard Biener via Gcc-patches wrote:
> When NRV replaces a local variable with it also replaces
> occurences in clobbers. This leads to being clobbered
> before the return of it which is strictly invalid but harmless in
> practice since there's no pass
Hi Hongtao,
This patch is to update model values for Alderlake, Rocketlake and Raptorlake
according to SDM.
Ok for trunk?
Thanks.
Lili.
Update model values for Alderlake, Rocketlake and Raptorlake according to SDM.
gcc/ChangeLog
* common/config/i386/cpuinfo.h (get_intel_cpu): Remove
Hi,
Pinging that regression fix.
Is everything OK for trunk ?
Thanks,
Benjamin
On Thu, Jun 22, 2023 at 9:57 PM wrote:
From: benjamin priour
Resend with proper subject line ...
Hi,
Below is the fix to regression bug
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110198
Was b
Hi all,
I've revised the change to be much neater
>From 480954bc7d2b24e5d19a98260a2be0b49e112c42 Mon Sep 17 00:00:00 2001
From: TheShermanTanker
Date: Wed, 28 Jun 2023 19:11:34 +0800
Subject: [PATCH] asm not using extended syntax should always be volatile
---
gcc/cp/parser.cc | 2 +-
1 file ch
When a language is enabled but we run the testsuite against a tree in
which the frontend compiler is not present, help.exp fails. It
recognizes the output pattern for a disabled language, but not a
missing frontend. Extend the pattern so that it covers both cases.
Tested on x86_64-linux-gnu.
From: Richard Biener
Date: Tuesday, June 27, 2023 at 12:58 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Tue, Jun 27, 2023 at 8:30 AM Tejas Belagod wrote:
>
>
>
>
>
> From: Richard Biener
> Date: Monday, June 26, 2023 at
Similar to vfwmacc. Add combine patterns as follows:
For vfwnmsac:
1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
For vfwmsac:
1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) )))
On Wed, 28 Jun 2023, Jakub Jelinek wrote:
> On Wed, Jun 28, 2023 at 10:21:45AM +, Richard Biener via Gcc-patches
> wrote:
> > When NRV replaces a local variable with it also replaces
> > occurences in clobbers. This leads to being clobbered
> > before the return of it which is strictly inv
The following adjusts the cost model of invariant motion to consider
[VEC_]COND_EXPRs and comparisons producing a data value as expensive.
For 503.bwaves_r this avoids an unnecessarily high vectorization
factor because of an integer comparison besides data operations on
double.
Bootstrapped and te
On Wed, Jun 28, 2023 at 12:32:51PM +, Richard Biener wrote:
> As said there's nothing run after NRV.
There is expansion but in the case I strongly doubt we are trying
to stack reuse it for other vars, so maybe it is ok.
> > On the other side, could there be partial clobbers for the var -> ,
On Sat, Jun 10, 2023 at 7:53 PM Jeff Law wrote:
>
>
>
> On 4/28/23 00:23, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The XTheadMemIdx ISA extension provides a additional load and store
> > instructions with new addressing modes.
> >
> > The following memory accesses types are s
On Sat, Jun 10, 2023 at 7:54 PM Jeff Law wrote:
>
>
>
> On 4/28/23 00:23, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The XTheadFMemIdx ISA extension provides additional load and store
> > instructions for floating-point registers with new addressing modes.
> >
> > The following
The following adds an alternate way of expanding a uniform
mask vector constructor like
_55 = _2 ? -1 : 0;
vect_cst__56 = {_55, _55, _55, _55, _55, _55, _55, _55};
when the mask mode is a scalar int mode like for AVX512 or GCN.
Instead of piecewise building the result via shifts and ors
we ca
Hi All,
This patch adds initial support for early break vectorization in GCC.
The support is added for any target that implements a vector cbranch optab,
this includes both fully masked and non-masked targets.
Depending on the operation, the vectorizer may also require support for boolean
mask re
Hi,
With the patch enabling the vectorization of early-breaks, we'd like to allow
bitfield lowering in such loops, which requires the relaxation of allowing
multiple exits when doing so. In order to avoid a similar issue to PR107275,
the code that rejects loops with certain types of gimple_stmts
Hi All,
FORTRAN currently has a pragma NOVECTOR for indicating that vectorization should
not be applied to a particular loop.
ICC/ICX also has such a pragma for C and C++ called #pragma novector.
As part of this patch series I need a way to easily turn off vectorization of
particular loops, part
Hi All,
There's an existing bug in loop frequency scaling where the if statement checks
to see if there's a single exit, and records an dump file note but then
continues.
It then tries to access the null pointer, which of course fails.
For multiple loop exists it's not really clear how to scale
Hi All,
The bitfield vectorization support does not currently recognize bitfields inside
gconds. This means they can't be used as conditions for early break
vectorization which is a functionality we require.
This adds support for them by explicitly matching and handling gcond as a
source.
Testca
Hi All,
expand_vector_piecewise does not support VLA expansion as it has a hard assert
on the type not being VLA.
Instead of just failing to expand and so the call marked unsupported we ICE.
This adjust it so we don't and can gracefully handle the expansion in support
checks.
Bootstrapped Regtes
Hi All,
This patch splits off the vectorizer's understanding of the main loop exit off
from the normal loop infrastructure.
Essentially we're relaxing the use of single_exit() in the vectorizer as we will
no longer have a single single and need a well defined split between the main
and secondary
Hi All,
For early break vectorization we have to update niters analysis to record and
analyze all exits of the loop, and so all conds.
The niters of the loop is still determined by the main/natural exit of the loop
as this is the O(n) bounds. For now we don't do much with the secondary conds,
bu
Hi All,
Vectorization of a gcond starts off essentially the same as vectorizing a
comparison witht he only difference being how the operands are extracted.
This refactors vectorable_comparison such that we now have a generic function
that can be used from vectorizable_early_break. The refactorin
Hi All,
When performing early break vectorization we need to be sure that the vector
operations are safe to perform. A simple example is e.g.
for (int i = 0; i < N; i++)
{
vect_b[i] = x + i;
if (vect_a[i]*2 != x)
break;
vect_a[i] = x;
}
where the store to vect_b is not allowed
Hi All,
This implements vectorable_early_exit which is used as the codegen part of
vectorizing a gcond.
For the most part it shares the majority of the code with
vectorizable_comparison with addition that it needs to be able to reduce
multiple resulting statements into a single one for use in the
Hi All,
This patch updates the peeling code to maintain LCSSA during peeling.
The rewrite also naturally takes into account multiple exits and so it didn't
make sense to split them off.
For the purposes of peeling the only change for multiple exits is that the
secondary exits are all wired to the
Hi All,
I didn't want these to get lost in the noise of updates.
The following three tests now correctly work for targets that have an
implementation of cbranch for vectors so XFAILs are conditionally removed gated
on vect_early_break support.
Bootstrapped Regtested on aarch64-none-linux-gnu and
Hi All,
Advanced SIMD lacks flag setting vector comparisons which SVE adds. Since
machines
with SVE also support Advanced SIMD we can use the SVE comparisons to perform
the
operation in cases where SVE codegen is allowed, but the vectorizer has decided
to generate Advanced SIMD because of loop
Hi All,
This adds an implementation for conditional branch optab for MVE.
Unfortunately MVE has rather limited operations on VPT.P0, we are missing the
ability to do P0 comparisons and logical OR on P0.
For that reason we can only support cbranch with 0, as for comparing to a 0
predicate we don'
Hi All,
This adds an implementation for conditional branch optab for AArch32.
For e.g.
void f1 ()
{
for (int i = 0; i < N; i++)
{
b[i] += a[i];
if (a[i] > 0)
break;
}
}
For 128-bit vectors we generate:
vcgt.s32q8, q9, #0
vpmax.u32 d7,
Hi All,
This adds an implementation for conditional branch optab for AArch64.
For e.g.
void f1 ()
{
for (int i = 0; i < N; i++)
{
b[i] += a[i];
if (a[i] > 0)
break;
}
}
For 128-bit vectors we generate:
cmgtv1.4s, v1.4s, #0
umaxp v1.4s, v1.4s,
Hi All,
Advanced SIMD lacks a cmpeq for vectors, and unlike compare to 0 we can't
rewrite to a cmtst.
This operation is however fairly common, especially now that we support early
break vectorization.
As such this adds a pattern to recognize the negated any comparison and
transform it to an all.
Resending attached only due to size limit
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, June 28, 2023 2:42 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> Subject: [PATCH 3/19]middle-end clean up vect testsuite using pragma
> novecto
Adding proper maintainers.
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, June 28, 2023 2:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: [PATCH 9/19]AArch64 middle-end: refactor vec
When NRV replaces a local variable with it also replaces
occurences in clobbers. This leads to being clobbered
before the return of it which is strictly invalid but harmless in
practice since there's no pass after NRV which would remove
earlier stores.
The following fixes this nevertheless.
Bo
From: Manolis Tsamis
Fixes: 6a2e8dcbbd4bab3
Propagation for the stack pointer in regcprop was enabled in
6a2e8dcbbd4bab3, but set ORIGINAL_REGNO/REG_ATTRS/REG_POINTER for
stack_pointer_rtx which caused regression (e.g., PR 110313, PR 110308).
This fix adds special handling for stack_pointer_rtx
Thanks! Applied to master with the requested changes as
417b8379b32945d61f1ce3d8281bee063eea1937.
Note that the final version factors out the duplicated logic, so we
now have a single place to add the comments.
Philipp.
On Sun, 25 Jun 2023 at 06:09, Jeff Law wrote:
>
>
>
> On 6/22/23 05:11, Phi
On 6/28/23 04:21, Richard Biener via Gcc-patches wrote:
When NRV replaces a local variable with it also replaces
occurences in clobbers. This leads to being clobbered
before the return of it which is strictly invalid but harmless in
practice since there's no pass after NRV which would remov
Also change some internal variables to bool and change return type of
compute_alignments to void.
gcc/ChangeLog:
* output.h (leaf_function_p): Change return type from int to bool.
(final_forward_branch_p): Ditto.
(only_leaf_regs_used): Ditto.
(maybe_assemble_visibility): Ditto.
On 6/28/23 05:25, Alexandre Oliva via Gcc-patches wrote:
When a language is enabled but we run the testsuite against a tree in
which the frontend compiler is not present, help.exp fails. It
recognizes the output pattern for a disabled language, but not a
missing frontend. Extend the pattern
Hi, Tamar.
This is an amazing auto-vectorization flow.
I am thinking about whether RVV can also get benefits from this optimization.
IMHO, RVV should be also using this flow.
So, to allow RVV (target uses len as loop_control and mask as flow control),
I am not sure whether we can do this (Feel
> On Jun 28, 2023, at 3:26 AM, Alexandre Oliva wrote:
>
> I'd probably have arranged for the front-end to create the initializer
> value, because expansion time is too late to figure it out: we may not
> even have the front-end at hand any more, in case of lto compilation.
>>>
> The new optabs need to be documented in doc/md.texi.
Done.
> “Long” is a bit of an architecture-specific term. Maybe just:
>
>Try to find the following ABsolute Difference (ABD) or
>widening ABD (WIDEN_ABD) pattern:
Change made.
> >> - VTYPE x, y, out;
> >> + VTYPE x, y;
> >
From: oluade01
This updates vect_recog_abd_pattern to recognize the widening
variant of absolute difference (ABDL, ABDL2).
gcc/ChangeLog:
* internal-fn.cc (widening_fn_p, decomposes_to_hilo_fn_p):
Add IFN_VEC_WIDEN_ABD to the switch statement.
* internal-fn.def (VEC_WIDE
> > +(define_insn "aarch64_abdl_hi_internal"
> > + [(set (match_operand: 0 "register_operand" "=w")
> > + (minus:
> > + (USMAX:
> > + (:
> > + (vec_select:
> > + (match_operand:VQW 1 "register_operand" "w")
> > + (match_operand:VQW 3 "vect_par_cnst_hi_half"
From: oluade01
This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(vec_widen_abdl_lo_, vec_widen_abdl_hi_):
Expansions for abd vec widen optabs.
(aarch64_abdl_insn): VQW based abdl RTL.
* confi
On 5/3/23 09:50, Patrick Palka wrote:
This patch makes us coerce the arguments of a variable template-id ahead
of time, as we do for other template-ids, which allows us to immediately
diagnose template parameter/argument kind mismatches and arity mismatches.
Unfortunately this causes a regressio
On 6/28/23 11:28, Jason Merrill wrote:
On 5/3/23 09:50, Patrick Palka wrote:
This patch makes us coerce the arguments of a variable template-id ahead
of time, as we do for other template-ids, which allows us to immediately
diagnose template parameter/argument kind mismatches and arity
mismatche
On 6/23/23 12:23, Patrick Palka wrote:
On Fri, 23 Jun 2023, Jason Merrill wrote:
On 6/21/23 13:19, Patrick Palka wrote:
When stepping through the variable/alias template specialization code
paths, I noticed we perform template argument coercion twice: first from
instantiate_alias_template / fi
On 6/23/23 18:25, Marek Polacek wrote:
Here we get the "error reporting routines re-entered" ICE because
of an unguarded use of warning_at. While at it, I added a check
for a warning_at just above it.
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
OK.
PR c++/110175
gc
Hi,
The function being changed in this patch can be invoked on VECTOR_TYPE,
but the implementation assumes it works on integer types only.
To fix, added a check whether the type passed is any `__vector(T)' or
non-integral type, and return early by calling
`signed_or_unsigned_type_for()' instead.
The libstdc++ test suite checks whether gdb type printers are
available like so:
set do_whatis_tests [gdb_batch_check "python print(gdb.type_printers)" \
"\\\[\\\]"]
This regexp assumes that the list of printers is empty. However,
sometimes it's convenient to ship
Hi Juzhe,
>
> Hi, Tamar.
>
> This is an amazing auto-vectorization flow.
>
> I am thinking about whether RVV can also get benefits from this optimization.
> IMHO, RVV should be also using this flow.
>
> So, to allow RVV (target uses len as loop_control and mask as flow control),
> I
> am not
On 6/27/23 11:23, Andrew Pinski via Gcc-patches wrote:
On Tue, Jun 27, 2023 at 12:14 AM Richard Biener via Gcc-patches
wrote:
On Tue, Jun 27, 2023 at 5:26 AM Andrew Pinski via Gcc-patches
wrote:
The manual references asm goto as being implicitly volatile already
and that was done when as
On 6/27/23 22:15, Juzhe-Zhong wrote:
Consider the following complicate case:
#define TEST_TYPE(TYPE1, TYPE2)\
__attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (
\
TYPE1 *__restrict dst, TYPE1 *__restrict dst2, T
There's currently no cheap way to obtain the partial template
specialization (and arguments relative to it) that was selected for a
class or variable template specialization. Our only option is to
compute the result from scratch via most_specialized_partial_spec.
For class templates this isn't re
On Sat, Jun 24, 2023 at 9:24 AM Nathaniel Shead
wrote:
>
> On Fri, Jun 23, 2023 at 11:59:51AM -0400, Patrick Palka wrote:
> > Hi,
> >
> > On Sat, 22 Apr 2023, Nathaniel Shead via Gcc-patches wrote:
> >
> > > Bootstrapped and tested on x86_64-pc-linux-gnu.
> > >
> > > -- 8< --
> > >
> > > This patc
On Wed, 28 Jun 2023 at 16:58, Tom Tromey via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
> The libstdc++ test suite checks whether gdb type printers are
> available like so:
>
> set do_whatis_tests [gdb_batch_check "python print(gdb.type_printers)"
> \
>"\\\[\\\]"]
>
.string "\001"
.string "\001"
.string "\001"
.string "\001"
.string "\001"
.string "\001"
.ascii "\001"
.section .srodata,"a"
.align 3
.type
On 6/28/23 05:55, Juzhe-Zhong wrote:
Similar to vfwmacc. Add combine patterns as follows:
For vfwnmsac:
1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
For vfwmsac:
1. (set (reg) (fma (float_extend (r
On 6/28/23 06:39, Christoph Müllner wrote:
+;; XTheadMemIdx overview:
+;; All peephole passes attempt to improve the operand utilization of
+;; XTheadMemIdx instructions, where one sign or zero extended
+;; register-index-operand can be shifted left by a 2-bit immediate.
+;;
+;; The basic ide
On 6/21/23 18:19, Li, Pan2 wrote:
Hi there,
I try to verify the offloading following below doc.
https://gcc.gnu.org/wiki/Offloading#How_to_build_an_offloading-enabled_GCC
with some steps:
1. Build nvptx-tools.
2. Symbol link nvptx-newlib to gcc source code.
3. Build the Nividia PTX accel c
Hi,
Since r13-1104, structs in the D have had compute_record_mode called too
early on them, causing them to return differently depending on the order
that types are generated in, and whether there are forward references.
This patch moves the call to compute_record_mode into its own function,
and
Try this:
https://godbolt.org/z/x7bM5Pr84
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-29 02:11
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for
VNx1BI, VNx2BI and VNx4BI
Hi Juzhe,
I find the bug description rather confusing. What I can see is that
the constant in the literal pool is indeed wrong but how would DSE or
so play a role there? Particularly only for the smaller modes?
My suspicion would be that the constant in the literal/constant pool
is wrong from s
On Wed, Jun 28, 2023 at 11:50 AM Jason Merrill wrote:
>
> On 6/23/23 12:23, Patrick Palka wrote:
> > On Fri, 23 Jun 2023, Jason Merrill wrote:
> >
> >> On 6/21/23 13:19, Patrick Palka wrote:
> >>> When stepping through the variable/alias template specialization code
> >>> paths, I noticed we perfo
On 6/28/23 12:51, Patrick Palka wrote:
There's currently no cheap way to obtain the partial template
specialization (and arguments relative to it) that was selected for a
class or variable template specialization. Our only option is to
compute the result from scratch via most_specialized_partial
Robin Dapp via Gcc-patches writes:
> Hi Juzhe,
>
> I find the bug description rather confusing. What I can see is that
> the constant in the literal pool is indeed wrong but how would DSE or
> so play a role there? Particularly only for the smaller modes?
>
> My suspicion would be that the const
Dear all,
the previous patches to this PR unfortunately caused a regression,
seen on Power big-endian systems/-m32 (pr110419), and while trying
to investigate on x86 also showed a regression (ICE) on cases that
were not covered in the testsuite before.
The original fix did not properly handle the
Hi,
early inliner currently skips always_inline functions and moreover we ignore
calls from always_inline in ipa_reverse_postorder. This leads to disabling
most of propagation done using early optimization that is quite bad when
early inline functions are not leaf functions, which is now quite com
Hi Alex,
welcome to the gfortran community. It is great that you are trying
to get actively involved.
You already did quite a few things right: patches shall be sent to
the gcc-patches ML, but Fortran reviewers usually notice them only
where they are copied to the fortran ML.
There are some ge
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