Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, June 16, 2023 11:56 PM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches
Cc: Robin Dapp ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV integer reduction in ZVE32/64.
On 6/16/2
On 6/16/23 07:55, 钟居哲 wrote:
LGTM
OK for the trunk. Sorry for the delays.
jeff
On 6/14/23 15:15, 钟居哲 wrote:
Hi, Jeff. Thanks for quick approval.
When I reviewed the patch:
(define_expand "2"
[(set (match_operand:VF 0 "register_operand")
(any_float_unop_nofrm:VF
(match_operand:VF 1 "register_operand")))]
"TARGET_VECTOR"
{
insn_code icode = code_for_pred
On 6/16/23 07:44, juzhe.zhong wrote:
lgtm
Which is good enough for me. Ok for the trunk.
jeff
On 6/16/23 07:43, juzhe.zhong wrote:
lgtm
ACK for the trunk.
jeff
On 6/16/23 03:06, Kyrylo Tkachov via Gcc-patches wrote:
Hi all,
In the testcase for this patch we try to vec_concat the lowpart and highpart of
a vector, but the lowpart is expressed as a subreg.
simplify-rtx.cc does not recognise this and combine ends up trying to match:
Trying 7 -> 8:
On Fri, Jun 16, 2023 at 3:49 PM Ben Boeckel wrote:
>
> On Thu, Jun 08, 2023 at 21:59:13 +0400, Maxim Kuvyrkov wrote:
> > This patch series causes ICEs on arm-linux-gnueabihf. Would you
> > please investigate? Please let me know if you need any in reproducing
> > these.
>
> Finally back at it. I
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